阅读说明：本技术 一种分布式可拓展的小芯片设计架构 (Distributed extensible small chip design framework ) 是由 蔡宗宇 陈希恒 韦红芳 于 2020-12-25 设计创作，主要内容包括：本发明公开了一种分布式可拓展的小芯片设计架构,在分开的晶元上设计相同或不同的功能模块架构,实现的分布式可扩展计算；所述功能模块架构中通过小芯片的架构实现具体设计；所述小芯片间通过高速芯片互联链路实现互联互通以及协同工作。本发明打破了SoC在单一芯片面积的限制,以及伴随的性能及算力限制。提升利用小芯片的高生产良率,减低总体芯片成本,达到应用配置及性能上灵活的可扩展性。(The invention discloses a distributed extensible small chip design framework, which designs the same or different functional module frameworks on separate wafers to realize distributed extensible computation; the functional module architecture realizes specific design through the architecture of a small chip; and the small chips realize interconnection and cooperative work through a high-speed chip interconnection link. The invention breaks the limitation of the SoC on the area of a single chip and the accompanying performance and computational power limitation. The high production yield of the small chips is improved, the total chip cost is reduced, and the flexible expandability in application configuration and performance is achieved.)

1. A distributed extensible chiplet design architecture characterized by:

designing the same or different functional module architectures on separate wafers to realize distributed extensible computation;

the functional module architecture realizes specific design through the architecture of a small chip;

and the small chips realize interconnection and cooperative work through a high-speed chip interconnection link.

2. The distributed scalable chiplet design architecture of claim 1, wherein: in the distributed extensible computing, the distribution is specifically that one computing task is cooperatively executed by two or more separate chiplets.

3. The distributed scalable chiplet design architecture of claim 1, wherein: in the distributed extensible calculation, the number of small chips is increased according to the application scene requirements, and the distributed extensible calculation is not limited by the size and production of SoC chips.

4. The distributed scalable chiplet design architecture of claim 1, wherein: the functional module comprises a logic circuit, an analog circuit or a memory circuit.

5. The distributed scalable chiplet design architecture of claim 1, wherein: the number of the divided cells is two or more.

6. The distributed scalable chiplet design architecture of claim 1, wherein: the high-speed chip interconnection link requires that the bandwidth is larger than a set threshold, the time delay is smaller than the set threshold, and the power consumption is smaller than the set threshold.

7. The distributed scalable chiplet design architecture of claim 1, wherein: the high-speed chip interconnection link is a parallel link or a serial link.

8. The distributed scalable chiplet design architecture of claim 1, wherein: between two chiplets, one or more sets of high-speed chip interconnect links are provided.

9. The distributed scalable chiplet design architecture of claim 6, wherein: the selection of the parameter setting threshold values of the bandwidth, the time delay and the power consumption is obtained by comparing the mutual transmission state among the function modules corresponding to the small chips with the general bus connection realization state in the integrated chip when the plurality of separated small chips are realized in the integrated chip mode.

Technical Field

The invention discloses a distributed extensible small chip design framework and relates to the technical field of chip design.

Background

The chip design technology adopted in the market is mainly that only a single die (die) is provided in a single package, such as NVIDIA previous generation architecture Pascal and current latest architecture graphics (ringing), and the number of transistors (Transistor Count) is increased from 12 billion to as much as 18.6 billion, which is increased by 55%. The wafer area is increased from 471mm 2 to 754mm 2 by 60%, which is not the result of the computational advanced process scaling. This means that some designs cannot benefit from process scaling, but rather expensive processes are used for these designs. On the other hand, since the area of a single wafer is so large, the yield of the product is affected only by an atomic defect or a silk impurity in the wafer manufacturing process. In order to avoid the whole die from being scrapped, a backup design and repair circuit must be added to the die, which will significantly reduce the effective utilization rate of the die.

A conventional SoC architecture is shown in fig. 1, which includes several functional modules and functional blobs connected by a system bus. The functional module can be a logic module, an analog module or a memory module. The functional blocks are the aggregation of the same functional modules, and can cumulatively provide stronger functions. The system bus provides high bandwidth inter-module interconnections as a high speed direct path for data transfers.

In order to effectively use the advantages of advanced process technology, a single chip (chip) package is used to carry a plurality of small chips (also called chiplets), so that each small chip can be controlled to a good yield, and the design complexity and corresponding silicon area cost of the backup design and repair circuit are simplified. On the other hand, for designs such as analog circuits that cannot be advantageously implemented in a micro tape manufacturing process, such as a 12 nm or 7 nm process, the designs are concentrated on the chips of the mainstream manufacturing process, such as a 28 nm or 22 nm process, so as to improve the cost performance of the chips. And the flexibility of the chip is also improved by putting the interface function on the small chip. Furthermore, scalability in performance can also be achieved by packaging different numbers of chiplets for different target markets.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the defects of the prior art, a distributed extensible small chip design architecture is provided, the design limitation of SoC is broken through, an extensible computing scheme is provided by a small chip (chipset) architecture, flexible configurability and extensibility (scalability) in performance are achieved according to application requirements, and flexible controllable distributed computing capability is provided by distributed computing units and matched analog circuits/memories.

The invention adopts the following technical scheme for solving the technical problems:

a distributed extensible small chip design architecture is characterized in that the same or different functional module architectures are designed on separate wafers to realize distributed extensible computation; the functional module architecture realizes specific design through the architecture of a small chip; and the small chips realize interconnection and cooperative work through a high-speed chip interconnection link.

For a further preferred solution, in the distributed scalable computation, the distribution is specifically that a share of computation task is performed by two or more separate chiplets in a coordinated manner. The method can be expanded, particularly, the number of small chips is increased by design according to the application scene requirements, and the method is not limited by the chip size and production of the SoC.

For a further preferable scheme, the functional module includes a logic circuit, an analog circuit, or a memory circuit. The number of the divided cells is two or more.

For a further preferable scheme, the high-speed chip interconnection link requires that the bandwidth is greater than a set threshold, the time delay is less than the set threshold, and the power consumption is less than the set threshold. The high-speed chip interconnection link is a parallel link or a serial link.

As a further preferred scheme, one or more groups of high-speed chip interconnection links are arranged between the two small chips.

For a further preferred scheme, the selection of the parameter setting threshold values of the bandwidth, the time delay and the power consumption is obtained by comparing the mutual transmission state among the functional modules corresponding to the chiplets with the general bus connection realization state in the integrated chip when the plurality of separated chiplets are realized in the manner of the integrated chip.

Compared with the prior art, the invention adopting the technical scheme has the following technical effects: the invention breaks the limitation of the SoC on the area of a single chip and the accompanying performance and computational power limitation. The high production yield of the small chips is improved, the total chip cost is reduced, and the flexible expandability in application configuration and performance is achieved.

Drawings

Fig. 1 is a schematic diagram of a conventional SoC architecture.

FIG. 2 is a schematic diagram of the present invention, in which a small chip architecture is used to replace the SoC architecture.

FIG. 3 is a diagram illustrating a functional split implemented by a chiplet architecture in an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a functional replication implemented by a chiplet architecture in an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

The technical scheme of the invention is further explained in detail by combining the attached drawings:

in the present invention, a schematic diagram of replacing an SoC architecture with a chiplet architecture is shown in fig. 2, and when implementing design of a chiplet, the design can be implemented by dividing into two or more chiplets according to the division of functional modules and the planning of products. The small chips are connected in a butt joint mode through high-speed links, and high-speed interconnection and intercommunication among the small chips are achieved. The design framework can support task division and cooperation among the small chips, and the arrangement of the number of the small chips and the topological structure design can be adjusted according to application requirements by means of the characteristic of distributed computing, so that the calculation power of the scheme is flexibly expanded.

The distributed extensible small chip design architecture is characterized in that the same or different functional module architectures are designed on separate wafers to realize distributed extensible calculation; the functional module architecture realizes specific design through the architecture of a small chip; and the small chips realize interconnection and cooperative work through a high-speed chip interconnection link. In the distributed extensible computing, the distribution is specifically that one computing task is cooperatively executed by two or more separate chiplets. The method can be expanded, particularly, the number of small chips is increased by design according to the application scene requirements, and the method is not limited by the chip size and production of the SoC.

In an embodiment of the present invention, a structural diagram of a functional split implemented by a chiplet architecture is shown in fig. 3, which splits a function of an SoC into two or more chiplets, and has the greatest advantages of being able to develop several chiplets with different functions, adopting a suitable process, and obtaining a better production yield.

In a specific embodiment of the present invention, a schematic structural diagram of implementing function replication by a chiplet architecture is shown in fig. 4, and a key function of an SoC is repeatedly implemented to two or more chiplets, so that the number of chips can be flexibly expanded to meet different application requirements, in addition to the advantage of good yield.

In the design scheme of the invention, the functions can be divided into basic necessary functions and flexible and configurable functions according to the function plan of the small chip. The basic necessary functions in each chiplet can be the same, and the flexible configurable function can be configured in no way, in a single way, or in multiple ways according to the requirement.

The design of high-speed inter-chip interconnection needs to be added in the small chip to be used as a high-speed link for interconnection and intercommunication between chips. According to the interconnection quantity of the small chips and the interconnection bandwidth requirement, the interconnection design among the high-speed chips can be one group or multiple groups, and the design is mainly characterized in that the interconnection efficiency among the small chips is consistent with the efficiency grade of an SoC internal bus. The high-speed chip interconnection link requires that the bandwidth is larger than a set threshold, the time delay is smaller than the set threshold, and the power consumption is smaller than the set threshold.

The chiplets with different functions can be reused for different product combinations, and the design emphasis is that the high-speed inter-chip interconnection design needs to be compatible.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.