阅读说明：本技术 一种基于fpga的编码器滤波算法 (Encoder filtering algorithm based on FPGA ) 是由 陈诚 于 2020-11-25 设计创作，主要内容包括：本发明提供一种基于FPGA的编码器滤波算法,包括以下步骤：增量式编码器；FPGA；空闲状；计数状；判决状,该装置滤波效果好,能够完全滤除低于设定脉宽阈值的干扰信号,并对有用信号的边沿不产生影响；滤波的脉宽阈值灵活可配置,根据不同的应用场合选择不同的脉宽阈值即可移植使用,该滤波算法消耗的逻辑资源极少。(The invention provides an encoder filtering algorithm based on an FPGA (field programmable gate array), which comprises the following steps of: an incremental encoder; an FPGA; an idle state; counting; the device has good filtering effect, can completely filter interference signals lower than a set pulse width threshold value, and does not affect the edge of a useful signal; the filtering pulse width threshold is flexible and configurable, different pulse width thresholds can be selected according to different application occasions to be transplanted for use, and the filtering algorithm consumes few logic resources.)

1. An encoder filtering algorithm based on FPGA is characterized in that: the method comprises the following steps:

the method comprises the following steps: entering the inside of the incremental encoder, wherein the working frequency of the incremental encoder is generally less than 10KHz, namely the period is more than 100US, and the time of two adjacent edges is more than 50 US; the width of the interference pulse is generally less than 4US, so that a threshold value, for example, 5US, can be selected, the time widths of two adjacent edges in the encoder signal are detected in software, and the pulse with the width less than 5US is removed, so that a pure encoder signal can be obtained;

step two: enabling the encoder signal to enter a state machine for realizing a filtering algorithm by the FPGA;

step three: after the system is reset, firstly entering an idle state;

step four: when the jump is detected, the system enters a counting state; continuously detecting whether jumping arrives in a counting state;

step five: when the count value reaches 5US, the system enters a decision state.

2. The FPGA-based encoder filtering algorithm of claim 1, wherein: and fourthly, if the jump occurs, the counter is cleared and recounted.

3. The FPGA-based encoder filtering algorithm of claim 1, wherein: and step five, judging whether the current value S2 is equal to the state value S1 before jumping, and returning to the idle state.

Technical Field

The invention relates to the field of encoder filtering algorithm equipment based on an FPGA (field programmable gate array), in particular to an encoder filtering algorithm based on the FPGA.

Background

The encoder is used as one of common sensors, is mainly used for detecting angles, distances, speeds, positions or counting of mechanical movement, is a high-integration-level digital detection device, has the advantages of high precision, fast response, high resolution, reliable performance and the like, and in recent years, the encoder has been developed into a mature high-performance and multi-specification series industrial product, is mainly applied to various digital electronic circuits, products needing detection and servo control can be used as the encoder, the photoelectric encoder can be divided into an incremental photoelectric encoder, an absolute photoelectric encoder and a combined photoelectric encoder according to the difference between a pulse output mode and a photoelectric code disc scaling method, in practical industrial application, the incremental photoelectric encoder often cooperates with large electromechanical equipment, the electromagnetic environment is relatively complex, output signals of the encoder are relatively easily interfered to generate burrs, thereby causing false detection and affecting the control precision of the system.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide an encoder filtering algorithm based on an FPGA (field programmable gate array) to solve the problems in the background art.

In order to achieve the purpose, the invention is realized by the following technical scheme: an FPGA-based encoder filtering algorithm, comprising the steps of:

the method comprises the following steps: entering the inside of the incremental encoder, wherein the working frequency of the incremental encoder is generally less than 10KHz, namely the period is more than 100US, and the time of two adjacent edges is more than 50 US; the width of the interference pulse is generally less than 4US, so that a threshold value, for example, 5US, can be selected, the time widths of two adjacent edges in the encoder signal are detected in software, and the pulse with the width less than 5US is removed, so that a pure encoder signal can be obtained;

step two: enabling the encoder signal to enter a state machine for realizing a filtering algorithm by the FPGA;

step three: after the system is reset, firstly entering an idle state;

step four: when the jump is detected, the system enters a counting state; continuously detecting whether jumping arrives in a counting state;

step five: when the count value reaches 5US, the system enters a decision state.

As a preferred mode of the present invention, said step four is that the counter clears and counts again if there is a transition.

As a preferred mode of the present invention, the step five determines whether the current value S2 is equal to the state value S1 before the transition, and returns to the idle state.

The invention has the beneficial effects that:

1. the FPGA-based encoder filtering algorithm has a good filtering effect, can completely filter interference signals lower than a set pulse width threshold value, and does not affect the edges of useful signals.

2. The pulse width threshold value of the FPGA-based encoder filtering algorithm is flexible and configurable, different pulse width threshold values can be selected according to different application occasions to be transplanted for use, and the filtering algorithm consumes few logic resources.

Drawings

FIG. 1 is a schematic structural diagram of an FPGA-based encoder filtering algorithm according to the present invention;

FIG. 2 is a schematic structural diagram of an ideal waveform of an FPGA-based encoder filtering algorithm according to the present invention;

FIG. 3 is a schematic diagram of an actual waveform of an FPGA-based encoder filtering algorithm according to the present invention;

FIG. 4 is a state machine jump diagram of an FPGA-implemented filtering algorithm of an FPGA-based encoder filtering algorithm according to the present invention;

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.

Referring to fig. 1 to 4, the present invention provides a technical solution: an FPGA-based encoder filtering algorithm, comprising the steps of:

the method comprises the following steps: entering the inside of the incremental encoder, wherein the working frequency of the incremental encoder is generally less than 10KHz, namely the period is more than 100US, and the time of two adjacent edges is more than 50 US; the width of the interference pulse is generally less than 4US, so that a threshold value, for example, 5US, can be selected, the time widths of two adjacent edges in the encoder signal are detected in software, and the pulse with the width less than 5US is removed, so that a pure encoder signal can be obtained;

step two: enabling the encoder signal to enter a state machine for realizing a filtering algorithm by the FPGA;

step three: after the system is reset, firstly entering an idle state;

step four: when the jump is detected, the system enters a counting state; continuously detecting whether jumping arrives in a counting state;

step five: when the count value reaches 5US, the system enters a decision state.

As a preferred mode of the present invention, said step four is that the counter clears and counts again if there is a transition.

As a preferred mode of the present invention, the step five determines whether the current value S2 is equal to the state value S1 before the transition, and returns to the idle state.

The FPGA from the second step to the fifth step comprises the following main codes:

while there have been shown and described what are at present considered the fundamental principles and essential features of the invention and its advantages, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.