阅读说明：本技术 显示装置及其操作方法 (Display device and operation method thereof ) 是由 金建熙 朴常镐 全珠姬 郑荣哲 于 2019-05-22 设计创作，主要内容包括：一种显示装置包括：基板；和放置在基板上的晶体管,其中晶体管包括：半导体层；与半导体层重叠的栅电极；与沟道区重叠并且与栅电极接触的第一栅接触重叠层,栅电极和半导体层在沟道区处重叠；和与沟道区重叠并且与半导体层接触的半导体接触重叠层,并且第一栅接触重叠层和半导体接触重叠层在沟道区内由间隙物理地分开。(A display device includes: a substrate; and a transistor disposed on the substrate, wherein the transistor includes: a semiconductor layer; a gate electrode overlapping with the semiconductor layer; a first gate contact overlap layer overlapping the channel region and contacting the gate electrode, the gate electrode and the semiconductor layer overlapping at the channel region; and a semiconductor contact overlayer overlapping the channel region and in contact with the semiconductor layer, and the first gate contact overlayer and the semiconductor contact overlayer are physically separated by a gap within the channel region.)

1. A display device, comprising:

a substrate; and

a transistor disposed on the substrate and having a first terminal,

wherein the transistor includes:

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer;

a first gate contact overlap layer overlapping a channel region and contacting the gate electrode, the gate electrode and the semiconductor layer overlapping at the channel region; and

a semiconductor contact overlap layer overlapping the channel region and contacting the semiconductor layer, and

the first gate contact overlayer and the semiconductor contact overlayer are physically separated by a gap within the channel region.

2. The display device according to claim 1,

the transistor further includes:

a second gate contacting the overlap layer overlapping the channel region and contacting the gate electrode, and

in plan, the semiconductor contact overlap is arranged between the first gate contact overlap and the second gate contact overlap.

3. The display device according to claim 2,

in a plane, a width of an entire region including the first gate contact stack, the semiconductor contact stack, the second gate contact stack, and the gap is greater than a width of the channel region.

4. The display device according to claim 2,

in a plane, a width of an entire region including the first gate contact stack, the semiconductor contact stack, the second gate contact stack, and the gap is smaller than a width of the channel region.

5. The display device according to claim 2,

the transistor further includes a floating overlap layer overlapping the channel region and insulated from and unconnected to the semiconductor layer and the gate electrode.

6. The display device according to claim 1,

the semiconductor contact stack comprises:

a first overlapping portion overlapping with the channel region;

a second overlapping portion overlapping with the channel region;

a contact portion which is in contact with the semiconductor layer without overlapping with the gate electrode; and

an extension part connecting the first overlapping part, the second overlapping part, and the contact part to each other.

7. The display device according to claim 6,

the first gate contact stack is disposed between the first overlap and the second overlap.

8. The display device according to claim 6,

in a plane, a width of an entire region including the first gate contact overlap layer, the first overlap portion, the second overlap portion, and the gap is greater than a width of the channel region.

9. The display device according to claim 6,

in a plane, a width of an entire region including the first gate contact overlap layer, the first overlap portion, the second overlap portion, and the gap is smaller than a width of the channel region.

10. The display device according to claim 6,

the transistor further includes a floating overlap layer overlapping the channel region and insulated from and unconnected to the semiconductor layer and the gate electrode.

11. The display device according to claim 1,

the width of the first gate contact stack is the same as the width of the semiconductor contact stack.

12. The display device according to claim 1,

the width of the first gate contact stack and the width of the semiconductor contact stack are different from each other.

13. A display device, comprising:

a plurality of pixels, each of which is formed of a plurality of pixels,

wherein each of the plurality of pixels includes:

a light emitting diode; and

a driving transistor controlling an amount of current flowing from the first power voltage to the light emitting diode, and

the driving transistor includes:

a gate electrode connected to a first node;

a first electrode to which the first power supply voltage is applied;

a second electrode electrically connected to the light emitting diode;

a gate contact overlap layer overlapping a channel region of the driving transistor and connected to the gate electrode; and

a semiconductor contact overlap layer overlapping the channel region and connected to the first electrode, and

the gate contact stack and the semiconductor contact stack are physically separated by a gap.

14. The display device according to claim 13,

each of the plurality of pixels further includes:

a switching transistor connected between the data line and the driving transistor, and

the switching transistor includes:

a gate electrode connected to the first gate line, and

a gate contact overlap layer overlapping a channel region of the switching transistor and connected to the gate electrode of the switching transistor.

15. The display device according to claim 13,

each of the plurality of pixels further includes:

a compensation transistor connected between the second electrode and the gate electrode of the driving transistor, and

the compensation transistor includes:

a gate electrode connected to the first gate line; and

a gate contact overlap layer overlapping a channel region of the compensation transistor and connected to the gate electrode of the compensation transistor.

16. The display device according to claim 13,

each of the plurality of pixels further includes:

an initialization transistor applying an initialization voltage to the gate electrode of the driving transistor, and

the initialization transistor includes:

a gate electrode connected to the second gate line; and

a gate contact overlap layer overlapping a channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

17. A driving method of a display device including a driving transistor controlling an amount of current flowing from a first power voltage to a light emitting diode, a switching transistor transmitting a data voltage applied to a data line to the driving transistor according to a first gate signal applied to a first gate line, a compensation transistor diode-connecting the driving transistor according to the first gate signal, and an initialization transistor applying an initialization voltage to a gate electrode of the driving transistor according to a second gate signal applied to a second gate line, the driving method comprising:

applying the first power supply voltage to a first electrode of the driving transistor, causing a current to flow from the first power supply voltage to the light emitting diode in response to a voltage of a first node to which the gate electrode of the driving transistor is connected;

applying the first power supply voltage to a semiconductor contact overlap layer overlapping a channel region of the driving transistor and connected to the first electrode of the driving transistor; and

applying the voltage of the first node to a gate contact overlap layer overlapping the channel region of the driving transistor and connected to the gate electrode of the driving transistor.

18. The driving method of a display device according to claim 17, further comprising:

applying the first gate signal as a gate-on voltage to a gate electrode of the switching transistor to turn on the switching transistor; and is

Applying the first gate signal to a gate contact overlap layer overlapping a channel region of the switching transistor and connected to the gate electrode of the switching transistor.

19. The driving method of a display device according to claim 17, further comprising:

applying the first gate signal as a gate turn-on voltage to a gate electrode of the compensation transistor to turn on the compensation transistor; and is

Applying the first gate signal to a gate contact overlap layer overlapping a channel region of the compensation transistor and connected to the gate electrode of the compensation transistor.

20. The driving method of a display device according to claim 17, further comprising:

applying the second gate signal as a gate-on voltage to a gate electrode of the initialization transistor to turn on the initialization transistor; and is

Applying the second gate signal to a gate contact overlap layer overlapping a channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

Technical Field

Embodiments of the present invention relate to a display device and a driving method thereof. More particularly, the present invention relates to a display device including a transistor having improved characteristics and a driving method thereof.

Background

A display device is a device for displaying an image, and recently, an organic light emitting diode display has attracted attention.

The organic light emitting diode display has a self-emission characteristic and, unlike the liquid crystal display, it does not require a separate light source, and thus can be reduced in thickness and weight. In addition, the organic light emitting diode display exhibits high quality characteristics such as low power consumption, high luminance, and high reaction speed.

In general, an organic light emitting diode display includes a substrate, a plurality of transistors disposed on the substrate, and organic light emitting elements connected to the transistors. The transistor is a switching element, and is a basic configuration of the display device.

The transistor having characteristics such as a large data range and a large current flowing in an on state is advantageous for improving the display quality of the display device.

The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

Embodiments of the present invention provide a display device including a transistor having characteristics such as a large data range and a large current flowing in an on state, and a driving method thereof.

A display device according to an embodiment of the present invention includes: a substrate; and a transistor disposed on the substrate, wherein the transistor includes: a semiconductor layer; a gate electrode overlapping with the semiconductor layer; a first gate contact overlap layer overlapping the channel region and contacting the gate electrode, the gate electrode and the semiconductor layer overlapping at the channel region; and a semiconductor contact overlayer overlapping the channel region and in contact with the semiconductor layer, and the first gate contact overlayer and the semiconductor contact overlayer are physically separated by a gap within the channel region.

The transistor may further include a second gate contact overlap layer overlapping the channel region and contacting the gate electrode, and the semiconductor contact overlap layer is disposed between the first gate contact overlap layer and the second gate contact overlap layer on a plane.

In a plane, a width of an entire region including the first gate contact stack, the semiconductor contact stack, the second gate contact stack, and the gap may be greater than a width of the channel region.

In a plane, a width of an entire region including the first gate contact stack, the semiconductor contact stack, the second gate contact stack, and the gap may be less than a width of the channel region.

The transistor may further include a floating overlap layer overlapping the channel region and insulated from the semiconductor layer and the gate electrode without being connected.

The semiconductor contact stack may include: a first overlapping portion overlapping with the channel region; a second overlapping portion overlapping the channel region; a contact portion which is in contact with the semiconductor layer without overlapping with the gate electrode; and an extension portion connecting the first overlapping portion, the second overlapping portion, and the contact portion to each other.

The first gate contact stack may be disposed between the first overlap and the second overlap.

In a plane, a width of an entire region including the first gate contact overlap layer, the first overlap portion, the second overlap portion, and the gap may be greater than a width of the channel region.

In a plane, a width of an entire region including the first gate contact overlap layer, the first overlap portion, the second overlap portion, and the gap may be less than a width of the channel region.

The transistor may further include a floating overlap layer overlapping the channel region and insulated from the semiconductor layer and the gate electrode without being connected.

The width of the first gate contact stack may be the same as the width of the semiconductor contact stack.

The width of the first gate contact stack and the width of the semiconductor contact stack may be different from each other.

A display device according to another embodiment of the present invention includes a plurality of pixels, wherein each of the plurality of pixels includes: a Light Emitting Diode (LED); and a driving transistor controlling an amount of current flowing from the first power voltage to a Light Emitting Diode (LED), and the driving transistor includes: a gate electrode connected to a first node; a first electrode to which a first power supply voltage is applied; a second electrode electrically connected to a Light Emitting Diode (LED); a gate contact overlap layer overlapping the channel region of the driving transistor and connected to the gate electrode; and a semiconductor contact overlap layer overlapping the channel region and connected to the first electrode, and the gate contact overlap layer and the semiconductor contact overlap layer are physically separated by a gap.

Each of the plurality of pixels may further include a switching transistor connected between the data line and the driving transistor, and the switching transistor includes: a gate electrode connected to the first gate line; and a gate contact overlapping layer overlapping with a channel region of the switching transistor and connected to a gate electrode of the switching transistor.

Each of the plurality of pixels may further include a compensation transistor connected between the second electrode and the gate electrode of the driving transistor, and the compensation transistor includes: a gate electrode connected to the first gate line; and a gate contact overlapping layer overlapping with a channel region of the compensation transistor and connected to a gate electrode of the compensation transistor.

Each of the plurality of pixels may further include an initialization transistor applying an initialization voltage to the gate electrode of the driving transistor, and the initialization transistor may include: a gate electrode connected to the second gate line; and a gate contact overlapping layer overlapping the channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

A driving method of a display device according to another embodiment of the present invention, including a driving transistor controlling an amount of current flowing from a first power voltage to a Light Emitting Diode (LED), a switching transistor transmitting a data voltage applied to a data line to the driving transistor according to a first gate signal applied to a first gate line, a compensation transistor diode-connecting the driving transistor according to the first gate signal, and an initialization transistor applying an initialization voltage to a gate electrode of the driving transistor according to a second gate signal applied to a second gate line, includes: applying a first power supply voltage to a first electrode of the driving transistor; causing a current to flow from a first power voltage to a Light Emitting Diode (LED) in response to a voltage of a first node to which a gate electrode of a driving transistor is connected; applying a first power supply voltage to a semiconductor contact overlap layer overlapping a channel region of the driving transistor and connected to a first electrode of the driving transistor; and applying a voltage of the first node to a gate contact overlap layer overlapping a channel region of the driving transistor and connected to a gate electrode of the driving transistor.

May further include: applying a first gate signal as a gate-on voltage to a gate electrode of the switching transistor to turn on the switching transistor; and applying a first gate signal to a gate contact overlap layer overlapping a channel region of the switching transistor and connected to a gate electrode of the switching transistor.

May further include: applying a first gate signal as a gate-on voltage to a gate electrode of the compensation transistor to turn on the compensation transistor; and applying a first gate signal to a gate contact overlap layer overlapping a channel region of the compensation transistor and connected to a gate electrode of the compensation transistor.

May further include: applying a second gate signal as a gate-on voltage to a gate electrode of the initialization transistor to turn on the initialization transistor; and applying a second gate signal to a gate contact overlap layer overlapping a channel region of the initialization transistor and connected to a gate electrode of the initialization transistor.

The data range of the transistor used in the display device and the current flowing in the on state can be increased, and thus the display quality of the display device can be improved.

By increasing the data range of the driving transistor, more various gray images can be displayed. By increasing the current flowing through the transistor serving as the switching element, the charging efficiency of voltage can be improved, and high-speed driving of the display device can be realized.

Drawings

Fig. 1 is a plan view showing a transistor according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view of the transistor taken along line II-II' of fig. 1.

Fig. 3 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 1 are modified.

Fig. 4 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 1 are modified.

Fig. 5 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 1 are modified.

Fig. 6 is a top view showing a transistor according to another embodiment of the present invention.

Fig. 7 is a sectional view taken along line VII-VII' of fig. 6.

Fig. 8 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified.

Fig. 9 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified.

Fig. 10 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified.

Fig. 11 is a top view showing a transistor according to another embodiment of the present invention.

Fig. 12 is a top view showing a transistor according to another embodiment of the present invention.

Fig. 13 is a block diagram of a display device according to an embodiment.

Fig. 14 is a circuit diagram showing one pixel of a display device according to an embodiment of the present invention.

Fig. 15 is a sectional view showing the structure of a display device according to an embodiment of the present invention.

Fig. 16 is a timing chart illustrating a driving method of a display device according to an embodiment.

Fig. 17 is a graph showing characteristics of a transistor according to an embodiment of the present invention.

Fig. 18 is a circuit diagram showing a pixel according to the embodiment.

Detailed Description

Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In order to clearly explain the present invention, portions that are not directly related to the present disclosure are omitted throughout the specification, and the same reference numerals are attached to the same or similar constituent elements.

In addition, the size and thickness of each configuration shown in the drawings are arbitrarily illustrated for better understanding and ease of description, but the present invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for better understanding and ease of description.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Further, the words "on … …" or "above … …" mean placed on or above the object part, and do not necessarily mean placed on the upper side of the object part based on the direction of gravity.

Additionally, unless explicitly described to the contrary, the word "comprise", and variations such as "comprises" or "comprising", will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, in the specification, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a sectional view" means when a section taken by perpendicularly cutting the object portion is viewed from a side.

Now, transistors included in a display device according to an embodiment of the present invention are described with reference to fig. 1 and 2.

Fig. 1 is a plan view showing a transistor according to an embodiment of the present invention. Fig. 2 is a cross-sectional view of the transistor taken along line II-II' of fig. 1.

Referring to fig. 1 and 2, the display device includes a plurality of transistors disposed on a substrate 110. The plurality of transistors respectively include the overlapping layer ML, the semiconductor layer 120, the gate electrode 130, the first electrode 151, and the second electrode 153.

The substrate 110 may include a material such as glass, plastic, or Polyimide (PI). A barrier layer 111 is placed on the substrate 110, and an overlapping layer ML made of a metal having conductivity or a semiconductor material having conductivity characteristics equivalent thereto is placed on the barrier layer 111.

The stack ML comprises gate contact stacks MG1 and MG2 and semiconductor contact stack MS 1. The gate contact stacks MG1 and MG2 may include: a first gate contact overlap layer MG1 partially overlapping the semiconductor layer 120 and contacting the gate electrode 130 through a first gate contact hole CG 1; and a second gate contact overlap layer MG2 partially overlapping the semiconductor layer 120 and contacting the gate electrode 130 through a second gate contact hole CG 2.

As shown in fig. 1, the gate electrode 130 extends in the first direction D1, and the semiconductor layer 120 extends in the second direction D2 so as to partially overlap the gate electrode 130. The second direction D2 may intersect the first direction D1. The second direction D2 may be orthogonal to the first direction D1. For example, the first direction D1 may be a row direction, and the second direction D2 may be a column direction. However, according to the embodiment, the arrangement direction and the arrangement shape of the transistors may be changed differently, and the first direction D1 and the second direction D2 are not always orthogonal, nor are they always the row direction and the column direction. The overlapping portion of the semiconductor layer 120 and the gate electrode 130 becomes a channel region of the transistor. A channel region of the transistor corresponds to the channel portion 121 of the semiconductor layer 120, and the channel region of the transistor may be referred to as a channel region of the semiconductor layer 120.

The first gate contact overlap layer MG1 extends in the first direction D1 along one side of the gate electrode 130 to overlap the channel region. The first gate contact overlap layer MG1 includes a first extension portion MG1-1, the first extension portion MG1-1 extends further than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The first gate contact hole CG1 is placed at a position overlapping the first extension portion MG1-1, and the first gate contact overlap layer MG1 may be directly connected to the gate electrode 130 through the first gate contact hole CG 1.

The second gate contact overlap layer MG2 extends in the first direction D1 along the other side of the gate electrode 130 to overlap the channel region. The second gate contact overlap layer MG2 includes a second extension portion MG2-1, the second extension portion MG2-1 extends further than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The second gate contact hole CG2 is placed at a position overlapping the second extension portion MG2-1, and the second gate contact overlap layer MG2 may be directly connected to the gate electrode 130 through the second gate contact hole CG 2.

Semiconductor contact stack MS1 includes a first overlap MS1-1, an extension MS1-2 and a contact MS 1-3. The first overlap MS1-1 extends in parallel to the first gate contact overlap MG1 and the second gate contact overlap MG2 in a plane, and may overlap the semiconductor layer 120 and the gate electrode 130. The first overlapping portion MS1-1 overlaps with the channel region of the semiconductor layer 120. In plan, the first overlap MS1-1 may be placed between the first gate contact overlay MG1 and the second gate contact overlay MG 2. The contact MS1-3 does not overlap with the gate electrode 130, but overlaps with the semiconductor layer 120. Semiconductor contact hole CS1 is placed at a position overlapping contact portion MS1-3, and contact portion MS1-3 may contact semiconductor layer 120 through semiconductor contact hole CS 1. The extension MS1-2 has a structure connecting the first overlap MS1-1 and the contact MS1-3 to each other. The extension MS1-2 may not overlap with the semiconductor layer 120.

In plan, the first overlap MS1-1 of the first gate contact stack MG1 and the semiconductor contact stack MS1 are arranged spaced apart from each other by a gap GP. The first overlap MS1-1 of the first gate contact stack MG1 and the semiconductor contact stack MS1 is physically separated by a gap GP within the channel region. In plan, the first overlap MS1-1 of the second gate contact stack MG2 and the semiconductor contact stack MS1 are spaced apart from each other by a gap GP. The second gate contact stack MG2 and the first overlap MS1-1 of the semiconductor contact stack MS1 are physically separated by a gap GP within the channel region.

The first overlap MS1-1 of the first gate contact overlap MG1, the second gate contact overlap MG2 and the semiconductor contact overlap MS1 overlaps the channel region of the semiconductor layer 120. The overlap layer ML does not overlap with the channel region of the semiconductor layer 120 in the gap GP. That is, the gap GP is a region where the overlap layer ML does not overlap with the channel region of the semiconductor layer 120.

In plan, the width Wg1 of the first gate contact overlap MG1, the width Wg2 of the second gate contact overlap MG2, and the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be the same. Further, in plan, the width WT of the entire region including the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the overlapping channel region of the semiconductor layer 120 and the gate electrode 130. Each dimension of the plurality of gaps GP may be about 0.1 μm to 10 μm.

Here, the widths Wg1, Wg2, Ws1, WT, and W130 may be lengths in a second direction D2 intersecting the first direction D1, and the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the gate electrode 130 extend in the first direction D1.

Referring to fig. 2, the buffer layer 112 is disposed on the overlap layer ML. The semiconductor contact hole CS1 is formed in the buffer layer 112. A portion of contact MS1-3 of semiconductor contact stack MS1 may be exposed through semiconductor contact hole CS 1. The barrier layer 111 and the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide. In addition, the barrier layer 111 and the buffer layer 112 may include an organic insulating material such as polyimide and polyacrylate (added with epoxy resin). The semiconductor layer 120 is disposed on the buffer layer 112. The semiconductor layer 120 includes a channel portion 121 and a doped portion 122 disposed at both sides of the channel portion 121. The channel part 121 may correspond to a channel region of the transistor, and the doping part 122 may correspond to a source region and a drain region of the transistor. Any one of the dopings 122 of the semiconductor layer 120 may be connected to the contact MS1-3 of the semiconductor contact overlap layer MS1 through the semiconductor contact hole CS 1. A first gate insulating layer 141 is disposed on the semiconductor layer 120, and a gate electrode 130 is disposed on the first gate insulating layer 141. The gate electrode 130 overlaps with a channel region of the semiconductor layer 120.

Although not shown in fig. 2, the first gate contact hole CG1 and the second gate contact hole CG2 are formed in the buffer layer 112 and the first gate insulating layer 141. A portion of the first gate stack MG1 is exposed by the first gate contact hole CG 1. The gate electrode 130 overlaps the first gate contact hole CG1 and may be connected to the first gate contact overlap layer MG1 through the first gate contact hole CG 1. A portion of the second gate contact overlap MG2 is exposed by the second gate contact hole CG 2. The gate electrode 130 may overlap the second gate contact hole CG2 and may be connected to the second gate contact overlap layer MG2 through the second gate contact hole CG 2.

The second gate insulating layer 142 may be disposed on the gate electrode 130, and the first electrode 151 and the second electrode 153 may be disposed on the second gate insulating layer 142. The first electrode 151 may overlap one doped portion 122 of the semiconductor layer 120 and may be connected to the one doped portion 122 of the semiconductor layer 120 through a first electrode contact hole CE1 formed in the first and second gate insulating layers 141 and 142. The second electrode 153 may overlap the other doped portion 122 of the semiconductor layer 120 and may be connected to the other doped portion 122 of the semiconductor layer 120 through a second electrode contact hole CE2 formed in the first and second gate insulating layers 141 and 142.

Depending on the direction of the applied voltage or current, one of the first electrode 151 and the second electrode 153 may be a source electrode of a transistor, and the other may be a drain electrode. That is, the semiconductor contact overlayer MS1 may be connected to a source or drain electrode of a transistor.

As described above, the overlap layer ML is composed of two or more separated structures within the channel region of the semiconductor layer 120, and the channel region may include a region (e.g., the gap GP) that does not overlap with the overlap layer ML. A portion of the overlayer ML (e.g., gate contact overlayer MG1 and MG2) may be connected to the gate electrode 130 of the transistor, while another portion (e.g., semiconductor contact overlayer MS1) may be connected to the source or drain electrode of the transistor. According to this configuration, the data range of the transistor can be increased, and the current that can flow while the transistor is on can be increased. This will be described later.

Hereinafter, a transistor of an embodiment in which some configurations of fig. 1 are modified in the transistor is described with reference to fig. 3.

Fig. 3 is a top view of a transistor illustrating an embodiment in which some of the configurations of fig. 1 are modified. Focus is on the differences compared to the above described embodiment of fig. 1 and 2.

Referring to fig. 3, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be greater than the width Wg1 of the first gate contact overlap MG 1. In addition, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be greater than the width Wg2 of the second gate contact overlap MG 2. That is, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be different from the width Wg1 of the first gate contact overlap MG1 and the width Wg2 of the second gate contact overlap MG2 in plan view. The width Wg1 of the first gate contact stack MG1 and the width Wg2 of the second gate contact stack MG2 may be the same or different. Even in this case, the width WT of the entire region including the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120 on a plane.

Meanwhile, in contrast to the example of fig. 3, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be smaller than the width Wg1 of the first gate contact overlap MG1 and may be smaller than the width Wg2 of the second gate contact overlap MG 2. At this time, in plane, the width WT of the entire region including the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

In addition to these differences, the features of the embodiments described with reference to fig. 1 and 2 may be applied to all of the embodiments described with reference to fig. 3, and the repeated description between the embodiments is omitted.

Hereinafter, a transistor of an embodiment in which some configurations are modified in the transistor of fig. 1 is described with reference to fig. 4.

Fig. 4 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 1 are modified. Focus is on the differences compared to the above described embodiment of fig. 1 and 2.

Referring to fig. 4, in plan, the width WT of the entire region including the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the plurality of gaps GP may be less than the width W130 of the channel region of the semiconductor layer 120. In this case, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be greater than the width Wg1 of the first gate contact overlap MG1 and the width Wg2 of the second gate contact overlap MG2, respectively. Alternatively, the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1 may be equal to or less than the width Wg1 of the first gate contact overlap MG1 and the width Wg2 of the second gate contact overlap MG2, respectively.

In addition to these differences, since the features of the embodiment described with reference to fig. 1 and 2 may be all applied to the embodiment described with reference to fig. 4, a repetitive description between the embodiments is omitted.

Hereinafter, a transistor of an embodiment in which some configurations are modified in the transistor of fig. 1 is described with reference to fig. 5.

Fig. 5 is a top view of a transistor illustrating an embodiment in which some of the configurations of fig. 1 are modified. Focus is on the differences compared to the above described embodiment of fig. 1 and 2.

Referring to fig. 5, the stack ML may further include a floating stack MF not connected to the semiconductor layer 120 and the gate electrode 130 and overlapping the channel region of the semiconductor layer 120. The floating stack MF is insulated from other conductors and no voltage is applied to the floating stack MF.

The floating stack MF may be disposed on the same layer as the gate contact stacks MG1 and MG2 and the semiconductor contact stack MS 1. Further, in plane, the floating overlap MF may be disposed close to at least one of the gate contact overlaps MG1 and MG2 and the first overlap MS1-1 of the semiconductor contact overlap MS1 via the gap GP.

Fig. 5 shows that the floating overlay MF is adjacent to the first gate contact overlay MG 1. Floating stack MF and first gate contact stack MG1 are disposed separated from each other by a gap GP, and floating stack MF and first gate contact stack MG1 are physically separated by gap GP. The floating overlap MF may overlap the channel region of the semiconductor layer 120 and extend in parallel with the first gate contact overlap MG1 in the first direction D1.

The width Wf of the floating overlap MF may be the same as at least any one of the width Wg1 of the first gate contact overlap MG1, the width Wg2 of the second gate contact overlap MG2, and the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS 1. Alternatively, the width Wf of the floating overlap MF may be different from the width Wg1 of the first gate contact overlap MG1, the width Wg2 of the second gate contact overlap MG2, and the width Ws1 of the first overlap MS1-1 of the semiconductor contact overlap MS1, respectively. At this time, the width Wg1 of the first gate contact overlap MG1, the width Wg2 of the second gate contact overlap MG2, and the width Ws1 of the first overlap portion MS1-1 of the semiconductor contact overlap MS1 may be the same as or different from each other. Also, the width WT' of the entire region including the floating overlap MF, the first gate contact overlap MG1, the second gate contact overlap MG2, the first overlap MS1-1 of the semiconductor contact overlap MS1, and the plurality of gaps GP may be equal to, greater than, or less than the width W130 of the channel region of the semiconductor layer 120.

In addition to these differences, since the features of the embodiment described with reference to fig. 1 and 2 may be all applied to the embodiment described with reference to fig. 5, a repetitive description between the embodiments is omitted.

Next, a transistor of another embodiment is described with reference to fig. 6 and 7.

Fig. 6 is a top view showing a transistor according to another embodiment of the present invention. Fig. 7 is a sectional view taken along line VII-VII' of fig. 6. Focus is on the differences compared to the above described embodiment of fig. 1 and 2.

Referring to fig. 6 and 7, the stack ML comprises a first gate contact stack MG1 and a semiconductor contact stack MS 1. The first gate contact overlap layer MG1 partially overlaps the semiconductor layer 120 and contacts the gate electrode 130 through the first gate contact hole CG 1.

The first gate contact overlap layer MG1 is disposed at a central portion of the gate electrode 130, and extends in the first direction D1 to overlap the channel region. The first gate contact overlap layer MG1 includes a first extension portion MG1-1, the first extension portion MG1-1 extends further than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The first gate contact hole CG1 is placed at a position overlapping the first extension portion MG1-1, and the first gate contact overlap layer MG1 may be directly connected to the gate electrode 130 through the first gate contact hole CG 1.

The semiconductor contact stack MS1 may include a first overlap MS1-1a, a second overlap MS1-1b, an extension MS1-2, and a contact MS 1-3. The first overlapping portion MS1-1a extends in the first direction D1 along one side of the gate electrode 130 to overlap the channel region. The first overlapping portion MS1-1a may overlap the semiconductor layer 120 and the gate electrode 130. The second overlapping portion MS1-1b extends in the first direction D1 along the other side of the gate electrode 130 to overlap the channel region. The second overlapping portion MS1-1b may overlap the semiconductor layer 120 and the gate electrode 130. The contact MS1-3 does not overlap the gate electrode 130 but overlaps the semiconductor layer 120. Semiconductor contact hole CS1 is placed in contact portion MS1-3, and contact portion MS1-3 may contact semiconductor layer 120 through semiconductor contact hole CS 1. Extension MS1-2 has a structure connecting first overlap MS1-1a, second overlap MS1-1b, and contact MS1-3 to each other. The extension MS1-2 may not overlap with the semiconductor layer 120.

In plan, the first gate contact stack MG1 may be disposed between the first and second overlapping portions MS1-1a and MS1-1b of the semiconductor contact stack MS1, and in parallel to the first and second overlapping portions MS1-1a and MS1-1 b.

In plan, the first overlap MS1-1a of the first gate contact stack MG1 and the semiconductor contact stack MS1 is arranged to be separated by a gap GP. Also, the first gate contact stack MG1 and the second overlap MS1-1b of the semiconductor contact stack MS1 are spaced apart from each other by a gap GP. The first overlap MS1-1a of the first gate contact stack MG1 and the semiconductor contact stack MS1 are physically separated by a gap GP within the channel region. In addition, the first gate contact stack MG1 and the second overlap MS1-1b of the semiconductor contact stack MS1 are physically separated by a gap GP within the channel region.

The first gate contact overlap MG1, the first overlap MS1-1a and the second overlap MS1-1b of the semiconductor contact overlap MS1 overlap with the channel region of the semiconductor layer 120, and the overlap layer ML does not overlap with the channel region of the semiconductor layer 120 in the gap GP.

The width Wg1 of the first gate contact overlap MG1, the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1, and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS1 may be identical to each other. Also, the width WT of the entire region including the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1, the second overlap MS1-1b of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

Although not shown in fig. 7, the first gate contact hole CG1 is formed in the buffer layer 112 and the first gate insulating layer 141. A portion of the first gate stack MG1 is exposed by the first gate contact hole CG 1. The gate electrode 130 overlaps the first gate contact hole CG1 and may be connected to the first gate contact overlap layer MG1 through the first gate contact hole CG 1. In fig. 6 and 7, the second gate contact hole CG2 described in fig. 1 and 2 is not required.

In addition to these differences, since the features of the embodiment described with reference to fig. 1 and 2 may be all applied to the embodiment described with reference to fig. 6 and 7, a repetitive description between the embodiments is omitted.

Hereinafter, a transistor of an embodiment in which some configurations are modified in the transistor of fig. 6 is described with reference to fig. 8.

Fig. 8 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified. The differences compared to the above described embodiment of fig. 1 and 2 are mainly described.

Referring to fig. 8, the width Wg1 of the first gate contact stack MG1 may be greater than the width Ws1 of the first overlap MS1-1a of the semiconductor contact stack MS 1. Also, the width Wg1 of the first gate contact overlap MG1 may be greater than the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS 1. That is, the width Wg1 of the first gate contact overlap MG1 may be different from the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1 and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS 1. The width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1 and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS1 may be the same or different. Even in this case, the width WT of the entire region including the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1, the second overlap MS1-1b of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

Meanwhile, in contrast to the example of fig. 8, the width Wg1 of the first gate contact overlap MG1 may be smaller than the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1 and may be smaller than the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS1, and the width WT of the entire region including the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1, the second overlap MS1-1b of the semiconductor contact overlap MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

Except for these differences, since the features of the embodiment described with reference to fig. 6 and 7 may be all applied to the embodiment described with reference to fig. 8, a repetitive description between the embodiments is omitted.

Hereinafter, a transistor of an embodiment in which some configurations are modified in the transistor of fig. 6 is described with reference to fig. 9.

Fig. 9 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified. The differences compared to the above-described embodiment of fig. 6 and 7 are mainly described.

Referring to fig. 9, the width WT of the entire region including the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1, the second overlap MS1-1b of the semiconductor contact overlap MS1, and the plurality of gaps GP may be less than the width W130 of the channel region of the semiconductor layer 120. At this time, the width Wg1 of the first gate contact overlap MG1 may be greater than the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1 and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS 1. Alternatively, the width Wg1 of the first gate contact stack MG1 may be equal to or less than the width Ws1 of the first overlap MS1-1a of the semiconductor contact stack MS1 and the width Ws2 of the second overlap MS1-1b of the semiconductor contact stack MS 1.

Except for these differences, since the features of the embodiment described with reference to fig. 6 and 7 may be all applied to the embodiment described with reference to fig. 9, repeated descriptions between the embodiments are omitted.

Hereinafter, a transistor of an embodiment in which some configurations are modified in the transistor of fig. 6 is described with reference to fig. 10.

Fig. 10 is a top view showing a transistor of an embodiment in which some of the configurations in fig. 6 are modified. The differences compared to the above-described embodiment of fig. 6 and 7 are mainly described.

Referring to fig. 10, the overlap layer ML may further include a floating overlap layer MF overlapping the channel region without being connected to the semiconductor layer 120 and the gate electrode 130. The floating stack MF is insulated from other conductors and no voltage is applied to the floating stack MF.

The floating stack MF may be placed on the same layer as the first gate contact stack MG1 and the semiconductor contact stack MS 1. In plane, the floating overlap MF may be spaced apart from each other by a gap GP with at least one of the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1 and the second overlap MS1-1b of the semiconductor contact overlap MS 1.

Fig. 10 shows the first overlap MS1-1a of the floating overlap MF adjacent to the semiconductor contact overlap MS 1. The first overlap MS1-1a of the floating overlap MF and the semiconductor contact overlap MS1 are spaced apart from each other by a gap GP, and the floating overlap MF and the semiconductor contact overlap MS1 are physically separated by the gap GP. The floating overlap MF may overlap the channel region of the semiconductor layer 120, and may extend in parallel with the first overlap MS1-1a of the semiconductor contact overlap MS1 in the first direction D1.

The width Wf of the floating overlap MF may be the same as at least any one of the width Wg1 of the first gate contact overlap MG1, the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1, and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS 1. Alternatively, the width Wf of the floating overlap MF may be different from the width Wg1 of the first gate contact overlap MG1, the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1, and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS1, respectively. At this time, the width Wg1 of the first gate contact overlap MG1, the width Ws1 of the first overlap MS1-1a of the semiconductor contact overlap MS1, and the width Ws2 of the second overlap MS1-1b of the semiconductor contact overlap MS1 may be the same or different. Further, the width WT' of the entire region including the floating overlap MF, the first gate contact overlap MG1, the first overlap MS1-1a of the semiconductor contact overlap MS1, the second overlap MS1-1b of the semiconductor contact overlap MS1, and the plurality of gaps GP may be equal to or greater than the width W130 of the channel region of the semiconductor layer 120, or may be smaller than the width W130 of the channel region.

Except for these differences, since the features of the embodiment described with reference to fig. 6 and 7 may be all applied to the embodiment described with reference to fig. 10, a repetitive description between the embodiments is omitted.

In the above-described embodiments of fig. 1 to 4 and 6 to 9, the overlapping layer ML in the channel region of the semiconductor layer 120 is composed of three separate structures separated by two gaps GP, whereas in the above-described embodiments of fig. 5 and 10, the overlapping layer ML in the channel region of the semiconductor layer 120 is composed of four separate structures separated by three gaps GP. In this way, the overlap layer ML may be formed of a plurality of separate structures within the channel region of the semiconductor layer 120. The number of the separation structures of the overlapping layer ML in the channel region of the semiconductor layer 120 is not limited.

Hereinafter, an embodiment of two separate structures in which the overlapping layers ML are separated by a gap GP is described with reference to fig. 11.

Fig. 11 is a top view showing a transistor according to another embodiment of the present invention. The differences compared to the embodiment of fig. 1 and 2 are mainly described.

Referring to fig. 11, in contrast to the embodiment of fig. 1, the second gate contact overlayer MG2 is omitted. The first overlap MS1-1 of the semiconductor contact stack MS1 extends in the first direction D1 along the other side of the gate electrode 130. The first overlap MS1-1 of the first gate contact overlap MG1 and the semiconductor contact overlap MS1 are spaced apart from each other by a gap GP, and the first overlap MS1-1 of the first gate contact overlap MG1 and the semiconductor contact overlap MS1 may be physically separated by the gap GP.

In addition to these differences, the features of the embodiment described with reference to fig. 1 and 2 may all be applied to the embodiment described with reference to fig. 11. Also, features of the embodiments in which some of the configurations described with reference to fig. 3 to 5 are modified may all be applied to the embodiment described with reference to fig. 11. Therefore, a repetitive description between the embodiments is omitted.

Now, an embodiment in which the overlapping layer ML is formed as one is described with reference to fig. 12.

Fig. 12 is a top view showing a transistor according to another embodiment of the present invention. The differences compared to the above described embodiment of fig. 1 and 2 are mainly described.

Referring to fig. 12, the stack ML may comprise only the first gate contact stack MG1, and not the semiconductor contact stack MS1 described in fig. 1 and 2. The width Wg1 of the first gate contact stack MG1 may correspond to the width WT of the entire stack ML. The width Wg1 of the first gate contact overlap MG1 may be greater than the width W130 of the gate electrode 130. That is, the first gate contact overlap layer MG1 may overlap the entire channel region of the transistor.

Except for these differences, since the features of the embodiment described with reference to fig. 1 and 2 may be all applied to the embodiment described with reference to fig. 11, a repetitive description between the embodiments is omitted.

Hereinafter, a display device according to an embodiment is described with reference to fig. 13, and a pixel according to an embodiment of the present invention included in the display device is described with reference to fig. 14.

Fig. 13 is a block diagram of a display device according to an embodiment.

Referring to fig. 13, the display device includes a signal controller 100, a gate driver 200, a data driver 300, a light emission control driver 400, a power supply unit 500, and a display unit 600.

The signal controller 100 receives image signals R, G and B input from an external device and an input control signal controlling the display thereof. The image signals R, G and B store luminance information of each pixel PX, and the luminance has a predetermined number of gray levels. Examples of the input control signals include a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a main clock signal MCLK, and the like.

The signal controller 100 appropriately processes the input image signals R, G and B according to the operating conditions of the display unit 600 and the data driver 300 based on the input image signals R, G and B and the input control signals, and generates a first control signal CONT1, a second control signal CONT2, an image data signal DAT, and a third control signal CONT 3. The signal controller 100 transmits the first control signal CONT1 to the gate driver 200, the second control signal CONT2 and the image data signal DAT to the data driver 300, and the third control signal CONT3 to the light emission control driver 400.

The display unit 600 includes a plurality of gate lines SL1-SLn, a plurality of data lines DL1-DLm, a plurality of light emission control lines EL1-ELn, and a plurality of pixels PX. The plurality of pixels PX are connected to the plurality of gate lines SL1-SLn, the plurality of data lines DL1-DLm, and the plurality of emission control lines EL1-ELn, and may be arranged in a suitable matrix form. The plurality of gate lines SL1-SLn may extend in a general row direction and may be parallel to each other. The plurality of emission control lines EL1-ELn may extend in the approximate row direction and may be parallel to each other. The plurality of data lines DL1-DLm may extend in a general column direction and may be parallel to each other. The display unit 600 may correspond to a display area in which a plurality of pixels PX are disposed and an image is displayed.

The gate driver 200 is connected to the plurality of gate lines SL1-SLn, and transmits a gate signal composed of a combination of a gate-on voltage and a gate-off voltage to the plurality of gate lines SL1-SLn according to the first control signal CONT 1. The gate driver 200 may sequentially apply gate signals of a gate-on voltage to the plurality of gate lines SL 1-SLn.

The gate driver 200 may be disposed in a non-display area around the display area. That is, the gate driver 200 may be placed on the substrate 110 included in the display device in the non-display region. The gate driver 200 includes a plurality of transistors for sequentially applying gate signals of a gate-on voltage to the plurality of gate lines SL1-SLn, and at least one of the plurality of transistors may include any one of the transistors described above in fig. 1 to 12.

The data driver 300 is connected to the plurality of data lines DL1-DLm, and samples and holds the image data signal DAT and applies data voltages to the plurality of data lines DL1-DLm according to the second control signal CONT 2. The data driver 300 may apply a data voltage having a predetermined voltage range to the plurality of data lines DL1-DLm in response to a gate signal of a gate-on voltage.

The light emission control driver 400 is connected to the plurality of light emission control lines EL1-ELn, and may apply a light emission control signal consisting of a combination of a gate-on voltage and a gate-off voltage to the plurality of light emission control lines EL1-ELn according to the third control signal CONT 3. The light emission control driver 400 may sequentially apply the light emission control signals of the gate-on voltage to the plurality of light emission control lines EL 1-ELn.

The light emission control driver 400 may be placed on the substrate 110 included in the display device in the non-display region. The light emission control driver 400 includes a plurality of transistors for sequentially applying the light emission control signal of the gate-on voltage to the plurality of light emission control lines EL1-ELn, and at least one of the plurality of transistors may include any one of the transistors described above in fig. 1 to 12.

The power supply unit 500 supplies the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint to the plurality of pixels PX. The first power voltage ELVDD may be a high-level voltage supplied to an anode of the light emitting diode LED included in each of the plurality of pixels PX. The second power supply voltage ELVSS may be a low-level voltage supplied to the cathode of the light emitting diode LED included in each of the plurality of pixels PX. The first power supply voltage ELVDD and the second power supply voltage ELVSS are driving voltages for causing the plurality of pixels PX to emit light.

Fig. 14 is a circuit diagram showing one pixel of a display device according to an embodiment of the present invention. As an example, a pixel PX disposed in an nth pixel row and an mth pixel column among a plurality of pixels PX included in the display device of fig. 13 is described.

Referring to fig. 14, the pixel PX includes a light emitting diode LED and a pixel circuit 10 for controlling a current flowing from the first power voltage ELVDD to the light emitting diode LED. The first gate line SLn, the second gate line SLIn, the third gate line SLBn, the data line DLm, and the emission control line ELn may be connected to the pixel circuit 10. The second gate line SLIn may be a gate line to which a gate signal is applied one pixel row before the first gate line SLn. The third gate line SLBn may be a gate line to which a gate signal is applied one pixel row before the second gate line SLIn, a gate line to which the same gate signal as the second gate line SLIn is applied, a gate line to which the same gate signal as the first gate line SLn is applied, or a gate line to which a gate signal is applied one pixel row later than the first gate line SLn. The gate signal applied to the third gate line SLBn may be variously changed according to a driving method of the display device.

The pixel circuit 10 may include a driving transistor TR11, a switching transistor TR12, a compensation transistor TR13, a first light emission control transistor TR14, a second light emission control transistor TR15, an initialization transistor TR16, a reset transistor TR17, and a storage capacitor Cst.

The driving transistor TR11 includes a gate electrode connected to the first node N11, a first electrode connected to the third node N13, and a second electrode connected to the second node N12. The driving transistor TR11 is connected between the first power voltage ELVDD and the light emitting diode LED, and controls the amount of current flowing from the first power voltage ELVDD to the light emitting diode LED in response to the voltage of the first node N11. The drive transistor TR11 may further include a gate contact stack MG connected to the gate electrode and a semiconductor contact stack MS1 connected to the second electrode. The gate contact stack MG of the driving transistor TR11 may be electrically connected to the first node N11, and the semiconductor contact stack MS1 of the driving transistor TR11 may be electrically connected to the second node N12. The gate contact overlap MG and the semiconductor contact overlap MS1 of the drive transistor TR11 overlap the channel region of the drive transistor TR 11. The gate contact stack MG may comprise the first gate contact stack MG1 and the second gate contact stack MG2 described above in fig. 1 to 4. That is, the driving transistor TR11 may be formed of the transistor structure described in fig. 6 to 9. In addition, according to an embodiment, the driving transistor may be formed of the transistor structure described in fig. 1 to 5.

The switching transistor TR12 includes a gate electrode connected to the first gate line SLn, a first electrode connected to the data line DLm, and a second electrode connected to the second node N12. The switching transistor TR12 is connected between the data line DLm and the driving transistor TR11 and turned on according to a first gate signal of a gate-on voltage applied to the first gate line SLn to transmit the data voltage Vdat applied to the data line DLm to the second node N12. The switching transistor TR12 may further include a gate contact overlap layer MG connected to the gate electrode. The gate contact overlap layer MG of the switching transistor TR12 overlaps with the channel region of the switching transistor TR 12. The gate contact overlap layer MG of the switching transistor TR12 may be electrically connected to the first gate line SLn. The switching transistor TR12 may be formed by a transistor structure shown in fig. 12.

The compensation transistor TR13 includes a first compensation transistor TR13-1 and a second compensation transistor TR 13-2. The first compensating transistor TR13-1 includes a gate electrode connected to the first gate line SLn, a first electrode connected to the second electrode of the second compensating transistor TR13-2, and a second electrode connected to the first node N11. The second compensation transistor TR13-2 includes a gate electrode connected to the first gate line SLn, a first electrode connected to the third node N13, and a second electrode connected to the first electrode of the first compensation transistor TR 13-1. The first and second compensation transistors TR13-1 and TR13-2 are connected between the second electrode and the gate electrode of the driving transistor TR11 and are turned on according to a first gate signal of a gate-on voltage applied to the first gate line SLn. The first and second compensation transistors TR13-1 and TR13-2 may diode-connect the driving transistor TR11 to compensate for a threshold voltage of the driving transistor TR 11. The first and second compensating transistors TR13-1 and TR13-2 may further include a gate contact stack MG, respectively. Each of the gate contact overlapping layers MG of the first and second compensating transistors TR13-1 and TR13-2 may be electrically connected to the first gate line SLn. Each gate contact overlap layer MG of the first and second compensation transistors TR13-1 and TR13-2 overlaps each channel region of the first and second compensation transistors TR13-1 and TR 13-2. The first and second compensation transistors TR13-1 and TR13-2 may be formed of a transistor structure shown in fig. 12. In fig. 14, it is shown that the compensation transistor TR13 includes a first compensation transistor TR13-1 and a second compensation transistor TR13-2, but the compensation transistor TR13 may be formed as one according to an embodiment.

The first light emission controlling transistor TR14 includes a gate electrode connected to the light emission control line ELn, a first electrode connected to the first power voltage ELVDD, and a second electrode connected to the second node N12. The first light emitting control transistor TR14 is connected between the first power voltage ELVDD and the driving transistor TR11, and is turned on according to a light emission control signal applied to a gate-on voltage of the light emission control line ELn to transmit the first power voltage ELVDD to the driving transistor TR 11.

The second light emission controlling transistor TR15 includes a gate electrode connected to the light emission control line ELn, a first electrode connected to the third node N13, and a second electrode connected to the anode electrode of the light emitting diode LED. The second light emission controlling transistor TR15 is connected between the driving transistor TR11 and the light emitting diode LED, and is turned on according to a light emission control signal of a gate-on voltage applied to the light emission control line ELn to transmit a current flowing through the driving transistor TR11 to the light emitting diode LED.

The initialization transistor TR16 includes a first initialization transistor TR16-1 and a second initialization transistor TR 16-2. The first initialization transistor TR16-1 includes a gate electrode connected to the second gate line SLIn, a first electrode connected to the second electrode of the second initialization transistor TR16-2, and a second electrode connected to the first node N11. The second initialization transistor TR16-2 includes a gate electrode connected to the second gate line SLIn, a first electrode connected to an initialization voltage Vint, and a second electrode connected to the first electrode of the first initialization transistor TR 16-1. The first and second initialization transistors TR16-1 and TR16-2 are connected between the gate electrode of the driving transistor TR11 and the initialization voltage Vint and are turned on according to a second gate signal applied to the gate-on voltage of the second gate line SLIn to transmit the initialization voltage Vint to the first node N11, thereby initializing the gate voltage of the driving transistor TR11 to the initialization voltage Vint. The first and second initializing transistors TR16-1 and TR16-2 may further include a gate contact overlap layer MG connected to the gate electrode, respectively. Each of the gate contact overlapping layers MG of the first and second initialization transistors TR16-1 and TR16-2 may be electrically connected to the second gate line SLIn. Each gate contact overlap layer MG of the first and second initialization transistors TR16-1 and TR16-2 overlaps each channel region of the first and second initialization transistors TR16-1 and TR 16-2. The first and second initializing transistors TR16-1 and TR16-2 may be formed of a transistor structure shown in fig. 12. Fig. 14 shows that the initialization transistor TR16 includes a first initialization transistor TR16-1 and a second initialization transistor TR16-2, but the initialization transistor TR16 may be formed as one according to an embodiment.

The reset transistor TR17 includes a gate electrode connected to the third gate line SLBn, a first electrode connected to the initialization voltage Vint, and a second electrode connected to the anode electrode of the light emitting diode LED. The reset transistor TR17 is connected between the anode of the light emitting diode LED and the initialization voltage Vint, and is turned on by a third gate signal of a gate-on voltage applied to the third gate line SLBn. The reset transistor TR17 may transmit the initialization voltage Vint to the anode of the light emitting diode LED to reset the light emitting diode LED to the initialization voltage Vint. According to an embodiment, the reset transistor TR17 may be omitted.

The driving transistor TR11, the switching transistor TR12, the compensation transistor TR13, the first light emission controlling transistor TR14, the second light emission controlling transistor TR15, the initialization transistor TR16, and the reset transistor TR17 may each be a p-channel electric field effect transistor. The gate-on voltage for turning on the p-channel electric field effect transistor is a low-level voltage, and the gate-off voltage for turning it off is a high-level voltage.

According to an embodiment, at least one of the driving transistor TR11, the switching transistor TR12, the compensation transistor TR13, the first light emission control transistor TR14, the second light emission control transistor TR15, the initialization transistor TR16, and the reset transistor TR17 may be an n-channel electric field effect transistor. The gate-on voltage for turning on the n-channel electric field effect transistor is a high-level voltage, and the gate-off voltage for turning it off is a low-level voltage.

The storage capacitor Cst includes a first electrode connected to the first power voltage ELVDD and a second electrode connected to the first node N11. The data voltage compensated for the threshold voltage of the driving transistor TR11 is transmitted to the first node N11, and the storage capacitor Cst serves to maintain the voltage of the first node N11.

The light emitting diode LED includes an anode connected to the second electrode of the second light emission controlling transistor TR15 and a cathode connected to the second power voltage ELVSS. The light emitting diode LED is connected between the pixel circuit 10 and the second power supply voltage ELVSS to emit light at a luminance corresponding to the current supplied from the pixel circuit 10. The light emitting diode LED may include an emission layer including at least one of an organic light emitting material and an inorganic light emitting material. Holes and electrons are injected from the anode and the cathode into the organic emission layer, and when excitons, which are combinations of the injected holes and electrons, drop from an excited state to a ground state, emission of light from the organic emission layer occurs. The light emitting diode LED may emit one of primary color and white color. For example, the primary colors may be three primary colors of red, green, and blue. Another example of a primary color may be yellow, cyan, magenta, etc.

Now, a structure of a display device including a pixel in which the driving transistor TR11 is formed by the transistor structure shown in fig. 6 and 7 is described with reference to fig. 15.

Fig. 15 is a sectional view showing the structure of a display device according to an embodiment of the present invention.

Referring to fig. 15, an organic layer 161 may be disposed on the first electrode 151, the second electrode 153, and the second gate insulating layer 142.

The pixel electrode 171 may be disposed on the organic layer 161, and the pixel electrode 171 may be electrically connected to the first electrode 151 of the driving transistor TR11 through a contact hole (not shown) passing through the organic layer 161. That is, the first electrode 151 of the driving transistor TR11 may be electrically connected to the light emitting diode LED through the second light emission controlling transistor TR15, and in this case, the pixel electrode 171 (e.g., anode) of the light emitting diode LED may be connected to the second electrode of the second light emission controlling transistor TR15 through the contact hole of the organic layer 161.

An emission layer 172 is disposed on the pixel electrode 171, and a power supply electrode 173 is disposed on the emission layer 172. The power supply electrode 173 may be formed of a transparent conductor such as ITO, IZO, or the like. The pixel electrode 171, the emission layer 172, and the power supply electrode 173 form a light emitting diode LED.

A definition layer 162 defining a region of the light emitting diode may be disposed around the pixel electrode 171. An encapsulation layer 180 for protecting the light emitting diode LED may be placed on the light emitting diode LED. The encapsulation layer 180 may be formed of alternately stacked inorganic layers and organic layers. According to an embodiment, the encapsulation layer 180 may be provided with an encapsulation member such as transparent glass or plastic, and the encapsulation member is bonded to the insulating substrate 110 using a sealant (not shown), thereby sealing the inner space and protecting the light emitting diode LED.

Since the features of the embodiment described above with reference to fig. 6 and 7 may be all applied to the embodiment described with reference to fig. 15, a repetitive description between the embodiments is omitted.

Now, a driving method of a display device including a pixel according to the embodiment of fig. 14 will be described with reference to fig. 16, and characteristics of a transistor according to an embodiment of the present invention will be described with reference to fig. 17 and 18.

Fig. 16 is a timing chart illustrating a driving method of a display device according to an embodiment. Fig. 17 is a graph showing characteristics of a transistor according to an embodiment of the present invention. Fig. 18 is a circuit diagram showing a pixel according to the embodiment.

Referring to fig. 16 and 17, a driving method of a display device according to an embodiment may include an initialization period T1, a data writing period T2, a reset period T3, and a light emitting period T4.

During the initialization period T1, the second gate signal SLI [ n ] is applied as the gate-On voltage On. In this case, the first gate signal SL [ n ], the third gate signal SLB [ n ], and the light emission control signal E [ n ] are applied as the gate-Off voltage Off. The first and second initialization transistors TR16-1 and TR16-2 are turned On by the second gate signal SLI [ N ] of the gate-On voltage On, and the initialization voltage Vint is transferred to the first node N11. The gate voltage of the driving transistor TR11 may be initialized by the initialization voltage Vint.

Each of the first and second initializing transistors TR16-1 and TR16-2 includes a gate contact overlap layer MG. The second gate signal SLI [ n ] is applied to each gate contact overlap layer MG of the first and second initialization transistors TR16-1 and TR 16-2. Accordingly, when the first and second initialization transistors TR16-1 and TR16-2 are fully turned on, the current flowing through the first and second initialization transistors TR16-1 and TR16-2 increases. This is described with reference to fig. 17 and 18.

Fig. 17 is a graph showing the characteristic curves of a general transistor TR _ N and a transistor TR _ S according to an embodiment of the invention comprising a gate contact overlap MG and a semiconductor contact overlap MS 1. The pixel circuit 20 including the general transistor TR _ N is the same as the pixel circuit 20 illustrated in fig. 18. In the pixel circuit 20 of fig. 18, in comparison with the pixel circuit 10 of fig. 14, all the transistors included in the pixel circuit 20 are the general transistors TR _ N without the gate contact overlap MG and the semiconductor contact overlap MS1 described in fig. 14.

In fig. 17, the horizontal axis represents the gate-source voltage difference Vgs of the transistor, and the vertical axis represents the current Ids flowing to the transistor.

Since the gate contact overlap MG is included in the transistor TR _ S according to the embodiment of the present invention, the current flowing through the transistor TR _ S according to the embodiment of the present invention increases more than the current flowing through the general transistor TR _ N because of the gate-source voltage difference Vgs of the fully-on transistor. The gate-source voltage difference Vgs of the fully turned on transistor may represent the gate-source voltage difference Vgs at which the transistor may flow the maximum current. In other words, the voltage required to increase the current through the transistor TR _ S according to the present embodiment is lower than the voltage required to increase the current through the general transistor TR _ N.

Referring to fig. 16 again, in other words, since each of the first and second initialization transistors TR16-1 and TR16-2 includes the gate contact overlap layer MG, the current flowing through the first and second initialization transistors TR16-1 and TR16-2 increases in a state where the first and second initialization transistors TR16-1 and TR16-2 are fully turned on.

During the data write period T2, the first gate signal SL [ n ] is applied as the gate-On voltage On. In this case, the second gate signal SLI [ n ], the third gate signal SLB [ n ], and the emission control signal E [ n ] are applied as the gate-Off voltage Off. The switching transistor TR12, the first compensating transistor TR13-1, and the second compensating transistor TR13-2 are turned On by a first gate signal SL [ n ] of a gate-On voltage On. The data voltage Vdat is transmitted to the second node N12 through the turned-on switching transistor TR 12. When the first and second compensation transistors TR13-1 and TR13-2 are turned on, the driving transistor TR11 is diode-connected, and the data voltage in which the threshold voltage of the driving transistor TR11 is compensated is transmitted to the first node N11. The voltage transmitted to the first node N11 may be charged in the storage capacitor Cst.

The switching transistor TR12 includes a gate contact overlap layer MG, and the first gate signal SL [ n ] is applied to the gate contact overlap layer MG of the switching transistor TR 12. Since the switching transistor TR12 includes the gate contact overlap layer MG, when the switching transistor TR12 is fully turned on, the current flowing through the switching transistor TR12 increases. Also, each of the first and second compensation transistors TR13-1 and TR13-2 includes a gate contact stack MG, and the first gate signal SL [ n ] is applied to each of the gate contact stacks MG of the first and second compensation transistors TR13-1 and TR 13-2. Since each of the first and second compensation transistors TR13-1 and TR13-2 includes the gate contact overlap MG, a current flowing through the first and second compensation transistors TR13-1 and TR13-2 increases in a state where the first and second compensation transistors TR13-1 and TR13-2 are fully turned on. In addition, since the driving transistor TR11 includes the gate contact overlap layer MG, the current flowing through the driving transistor TR11 can also be increased.

The data voltage Vdat applied to the data line DLm may be more quickly transferred to the first node N11 through the switching transistor TR12, the first compensating transistor TR13-1, and the second compensating transistor TR13-2, and the data voltage in which the threshold voltage of the driving transistor TR11 is compensated may be more quickly charged in the storage capacitor Cst.

During the reset period T3, the third gate signal SLB [ n ] of the gate-On voltage On is applied to the third gate line SLBn. In this case, the first gate signal SL [ n ] applied to the first gate line SLn, the second gate signal SLI [ n ] applied to the second gate line SLIn, and the light emission control signal E [ n ] applied to the light emission control line ELn are applied as the gate Off voltage Off. The reset transistor TR17 is turned On by the third gate signal SLB [ n ] of the gate-On voltage On, and the initialization voltage Vint is transmitted to the anode of the light emitting diode LED. The light emitting diode LED may be reset by an initialization voltage Vint.

During the light emission period T4, the light emission control signal E [ n ] is applied as the gate-On voltage On. In this case, the first gate signal SL [ n ], the second gate signal SLI [ n ], and the third gate signal SLB [ n ] are applied as the gate-Off voltage Off. The first and second light emission control transistors TR14 and TR15 are turned On by a light emission control signal E [ n ] of a gate-On voltage On. The first power voltage ELVDD is transmitted to the second node N12 through the turned-on first light emission controlling transistor TR14, and the driving transistor TR11 and the light emitting diode LED may be electrically connected by the turned-on second light emission controlling transistor TR 15. A current corresponding to the voltage of the first node N11 flows from the first power voltage ELVDD to the light emitting diode LED through the driving transistor TR11, and the light emitting diode LED may emit at a luminance corresponding to the amount of current. In this case, the voltage of the first node N11 is applied to the gate contact overlap MG of the driving transistor TR11 connected to the first node N11. Also, the first power supply voltage ELVDD is applied to the semiconductor contact stack MS1 of the driving transistor TR11 connected to the second node N12. Since the driving transistor TR11 includes the semiconductor contact overlap layer MS1, the data range of the driving transistor TR11 is increased. This is described with reference to fig. 17 and 18.

In fig. 17, V0 and V255 denote positions of a current value representing the minimum gradation (0 gradation) and a current value representing the maximum gradation (255 gradation) based on 256 gradations. Since the semiconductor contact overlap MS1 is included in the transistor TR _ S according to the embodiment of the present invention, as the gate-source voltage difference Vgs increases in the range of displaying gray scales, the slope of the characteristic curve of the transistor TR _ S changes more gradually than that of a general transistor TR _ N (e.g., a transistor included in the pixel circuit 20 of fig. 17). Thus, the data range DR2 of the transistor TR _ S according to the present embodiment becomes larger than the data range DR1 of the general transistor TR _ N. The data range is an interval between the gate-source voltage difference Vgs for supplying the current value representing the minimum gradation and the gate-source voltage difference Vgs for supplying the current value representing the maximum gradation. In other words, the driving range in which the transistor TR _ S according to the present embodiment is driven to display the minimum gradation and the maximum gradation is increased.

As described above, as the data range of the driving transistor TR11 increases, the output of the driving transistor TR11 changes less sensitively to changes in the gate-source voltage difference Vgs, and as a result, the output change according to the characteristics included in the driving transistor TR11 also becomes less sensitive. Thus, the characteristic variation among the plurality of pixels PX which emit light in the light emission period T4 is reduced, so that the display quality can be uniform and the display quality can be improved. In addition, since the data range of the driving transistor TR11 is increased, an image of more various gradations can be displayed.

The detailed description set forth above with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the invention defined by the claims and their equivalents. It includes various specific details to aid understanding, but these are to be regarded as examples only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Accordingly, the scope of the invention should be determined only by the following claims and their equivalents.