阅读说明：本技术 嵌入式服务器子系统及其配置方法 (Embedded server subsystem and configuration method thereof ) 是由 赖振楠 于 2020-12-14 设计创作，主要内容包括：本申请公开一种嵌入式服务器子系统及其配置方法,所述嵌入式服务器子系统包括：可编程逻辑门阵列芯片,用于根据应用需求,通过编程动态配置若干可编程逻辑运算单元；存储器,设置于所述可编程逻辑门阵列芯片外部,与所述可编程逻辑门阵列芯片连接,所述存储器用于提供支持所述可编程逻辑运算单元功能的程序和/或数据,且根据各可编程逻辑运算单元的配置切换所述程序和/或数据。所述嵌入式服务器子系统能够灵活配置硬件参数,满足多种应用场景的需求。(The application discloses an embedded server subsystem and a configuration method thereof, wherein the embedded server subsystem comprises: the programmable logic gate array chip is used for dynamically configuring a plurality of programmable logic operation units through programming according to application requirements; and the memory is arranged outside the programmable logic gate array chip and connected with the programmable logic gate array chip, and is used for providing programs and/or data supporting the functions of the programmable logic operation units and switching the programs and/or data according to the configuration of each programmable logic operation unit. The embedded server subsystem can flexibly configure hardware parameters and meet the requirements of various application scenes.)

1. An embedded server subsystem, comprising:

the programmable logic gate array chip is used for dynamically configuring a plurality of programmable logic operation units through programming according to application requirements;

and the memory is arranged outside the programmable logic gate array chip and connected with the programmable logic gate array chip, and is used for providing programs and/or data supporting the functions of the programmable logic operation units and switching the programs and/or data according to the configuration of each programmable logic operation unit.

2. The embedded server subsystem of claim 1, wherein the plurality of programmable logic units comprise: at least one of a programmable CPU, a programmable GPU, a programmable NPU, a programmable TPU, and a codec unit.

3. The embedded server subsystem of claim 1, wherein the programs and/or data comprise: at least one of an operating system, algorithm parameters, configuration parameters, and system configuration.

4. The embedded server subsystem of claim 2, wherein the configurable contents of the programmable logic unit comprise: at least one of the number of cores, the size of the cores, the architecture of the cores, the size of the cache, the routing path, and the configuration of the artificial intelligence algorithm.

5. The embedded server subsystem of claim 1, further comprising: the circuit board is provided with the programmable logic gate array chip and at least part of the memory; and the circuit board is also provided with various types of interfaces.

6. The embedded server subsystem of claim 1, wherein a memory is pluggably connected to the programmable gate array chip via the interface.

7. The embedded server subsystem of claim 1, wherein the memory comprises: at least one of SSD, GDDR, DDR, DRAM, SCM; at least part of the programmable logic operation units are connected to a matching type memory.

8. The embedded server subsystem of claim 1, wherein the memory is connected to the array of programmable gate arrays (PLD) chip via a PCle bus.

9. The embedded server subsystem of claim 1, further comprising a network-on-chip subsystem connected to the programmable gate array chip for providing network connection functions with the outside.

10. A configuration method of an embedded server subsystem is characterized by comprising the following steps:

providing an embedded server sub-system as claimed in any one of claims 1 to 9;

according to application requirements, carrying out programming reconstruction on a programmable logic gate array chip in the embedded server subsystem, and configuring a plurality of programmable logic operation units in the programmable logic gate array chip so that the configuration of the programmable logic operation units is dynamically changed along with the change of the application requirements;

and switching programs and/or data in the memory along with the configuration change of the programmable logic operation unit so as to support the operation of the programmable logic operation unit after the configuration change.

11. The method for configuring an embedded server subsystem according to claim 10, further comprising: and restarting the embedded server subsystem to enable the programmable logic operation unit to reload the switched programs and/or data from the corresponding memory.

Technical Field

The application relates to the technical field of computers, in particular to an embedded server subsystem and a configuration method thereof.

Background

An existing intelligent server system generally configures hardware with a specific specification, such as a CPU, an NPU, or a GPU, for a specific application scenario. The parameters of these hardware structures are determined by the hardware structures themselves, and cannot be adjusted, so that they usually need to be customized according to different requirements.

The customized server system has limited application range and no universality, and the server systems with specific architectures and performances need to be customized respectively according to various application requirements, so that the cost is higher and the flexibility is poorer.

Disclosure of Invention

In view of this, the present application provides an embedded server subsystem and a configuration method thereof, so as to solve the problem of poor flexibility of the existing server system.

The application provides an embedded server subsystem, includes: the programmable logic gate array chip is used for dynamically configuring a plurality of programmable logic operation units through programming according to application requirements; and the memory is arranged outside the programmable logic gate array chip and connected with the programmable logic gate array chip, and is used for providing programs and/or data supporting the functions of the programmable logic operation units and switching the programs and/or data according to the configuration of each programmable logic operation unit.

Optionally, the plurality of programmable logic operation units include: at least one of a programmable CPU, a programmable GPU, a programmable NPU, a programmable TPU, and a codec unit.

Optionally, the program and/or data includes: at least one of an operating system, algorithm parameters, and system configuration.

Optionally, the configurable content of the programmable logic operation unit includes: at least one of the number of cores, the size of the cores, the architecture of the cores, the size of the cache, the routing path, and the configuration of the artificial intelligence algorithm.

Optionally, the method further includes: the circuit board is provided with the programmable logic gate array chip and at least part of the memory; and the circuit board is also provided with various types of interfaces.

Optionally, the memory is connected to the programmable gate array chip through the interface in a pluggable manner.

Optionally, the memory includes: at least one of SSD, GDDR, DDR, DRAM, SCM; at least part of the programmable logic operation units are connected to a matching type memory.

Optionally, the memory is connected to the programmable gate array chip through a PCle bus.

Optionally, the parameters of the programmable logic operation unit are configured by programming the programmable logic gate array chip.

Optionally, the system further comprises an on-chip network subsystem, connected to the programmable gate array chip, for providing a network connection function with the outside.

The application also provides a configuration method of the embedded server subsystem, which comprises the following steps: the embedded server subsystem of any of the above; according to application requirements, carrying out programming reconstruction on a programmable logic gate array chip in the embedded server subsystem, and configuring a plurality of programmable logic operation units in the programmable logic gate array chip so that the configuration of the programmable logic operation units is dynamically changed along with the change of the application requirements; and switching programs and/or data in the memory along with the configuration change of the programmable logic operation unit so as to support the operation of the programmable logic operation unit after the configuration change.

Optionally, the method further includes: and restarting the embedded server subsystem to enable the programmable logic operation unit to reload the switched programs and/or data from the corresponding memory.

The embedded server subsystem comprises a programmable gate Array (FPGA) chip and a memory, and the FPGA chip is programmed to flexibly configure the programmable logic operation unit inside the FPGA chip so as to meet the requirements of different application scenes, so that the embedded server subsystem is high in flexibility and has a wider application range.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an embedded server subsystem according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of an embedded server subsystem according to an embodiment of the present application;

FIG. 3 is a block diagram of an embedded server subsystem according to an embodiment of the present application;

FIG. 4 is a block diagram of an embedded server subsystem according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a configuration method of an embedded server subsystem according to an embodiment of the present application.

Detailed Description

As described in the background art, the server system in the prior art has poor flexibility and cannot flexibly meet different application requirements. The invention provides a core embedded server subsystem, which can adjust a system architecture and related parameters according to different application requirements.

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.

Fig. 1 is a schematic structural diagram of an embedded server subsystem according to an embodiment of the present invention.

The embedded server subsystem includes a programmable gate Array (FPGA) chip 110 and a memory 120.

The programmable logic gate array chip (hereinafter referred to as FPGA chip) is at least provided with a plurality of programmable logic operation units through programming. Specifically, the FPGA chip 110 includes a programmable logic unit array therein, and a plurality of logic units can be combined to form a programmable logic operation unit capable of executing a specific logic operation function by programming the programmable logic unit array and connecting the logic units.

In this embodiment, the FPGA chip 110 is programmed with four programmable logic operation units 111a, 111b, 111c, and 111 d. Each of the programmable logic operation units 111a to 111d may be different types of logic operation units, or may be the same type of logic operation units, and the number and the type of the logic operation units are not limited herein, and may be configured according to specific requirements.

The connection relationship between the programmable logic units can also be customized for the programming of the FPGA chip as required, which is only illustrated in fig. 1.

The programmable logic operation units 111a to 111d respectively include: programmable CPU, programmable GPU, programmable NPU, programmable TPU, coding and decoding unit and the like.

The embedded server subsystem further includes a memory 120, which is disposed outside the FPGA chip 110, connected to the FPGA chip 110, and specifically connected to a programmable logic operation unit inside the FPGA chip 110. The memory 120 stores therein programs and/or data supporting the functions of the programmable logic operation units 111a to 111 d. For example, algorithm parameters, operating systems, configuration parameters, and the like may be stored.

The memory 120 includes: at least one of SSD, GDDR, DDR, DRAM, SCM. In some embodiments, a plurality of different types of memory are typically included to meet the requirements of different types of programmable logic arithmetic units. For example, in one embodiment, the programmable logic unit 111a is a GPU, and the corresponding memory 120 for storing the programmable logic unit 111a needs to be a GDDR. The connection relationship between the memory 120 and the FPGA chip 110 can also be adjusted by programming.

According to the change of application requirements, the programmable logic operation units in the programmable logic gate array chip 110 can be dynamically reconfigured through programming, and the hardware configuration of each logic operation unit can be adjusted. Meanwhile, the memory 120 switches programs and/or data according to the adjusted configuration of the programmable logic unit to continuously support the operation of the programmable logic unit.

Fig. 2 is a schematic structural diagram of an embedded server subsystem according to another embodiment of the present invention.

In this embodiment, the embedded server subsystem further includes a network on chip (NOC internet) subsystem 130, which is used for providing an internet data transmission function, and implementing data interaction between external data and the FPGA chip 110 through internet data transmission.

The programmable logic operation unit connected with the network-on-chip subsystem 130 has an encoding and decoding function, and is used for decoding received information to perform other logic operation processing; and encoding the data after the logical operation processing and then transmitting the encoded data to the outside through the on-chip sub-network system 130.

The connection relationship between the interior of the FPGA chip 110 and the network-on-chip subsystem 130 can also be configured in a programming manner.

Fig. 3 is a schematic structural diagram of an embedded server subsystem according to an embodiment of the present invention.

In this embodiment, the FPGA chip 110 is programmed with four programmable logic operation units, which are a CPU211a, a codec unit 211b, an NPU211c, and a GPU 211 d.

The CPU211a is used as a core processor, and is connected to the codec unit 111b, the NPU 111c, and the GPU111d, respectively, for data transmission. The coding and decoding unit 111b is connected to the network-on-chip subsystem 130, and is configured to perform coding and decoding processing on information.

The embedded server subsystem also includes various types of memory, SSD (solid state disk) 223, DRAM (dynamic random access memory) 224, GDDR (double data rate memory for graphics) 221, and GDDR222, respectively. The SSD223 and the DRAM 224 are both connected to the CPU211a in the FPGA chip 110, and are used for storing programs and data required by the CPU211a during operation, for example, the DRAM 224 may be used as a cache, and the SSD223 is used for storing nonvolatile storage. The GDDR 221 and the GDDR222 are respectively connected to the NPU211c and the GPU111d, and the GDDR has high data transmission efficiency, so that the requirement of large data volume transmission of the NPU211c and the GPU111d in the logic operation process can be met.

The SSD223 may be connected to the FPGA chip 110 through a pci (high speed serial computer extension) bus, and the DRAM 224 may be connected to the FPGA chip 110 through a DRAM bus corresponding to the DRAM.

In this embodiment, fig. 3 is an example of an artificial intelligence server architecture, where the GPU 211d is used to analyze and process graphics data, the NPU211c is used to perform artificial intelligence learning and calculation, training parameters and the like required in the process of the artificial intelligence learning and calculation performed by the NPU211c may be stored in the GDDR222, and algorithms and parameter data and the like required when the GPU 211d performs image processing may be stored in the GDDR 221.

According to different application requirements, parameters of each programmable logic operation unit in the FPGA chip 110 can be configured through programming. The parameters include: at least one of the number of cores, the size of the cores, the architecture of the cores, the size of the cache, the routing path, and the configuration of the artificial intelligence algorithm.

In one embodiment, the CPU211a may be configured by programming to be a single core, dual core, 4 core, 8 core, 16 core, 64 core, etc. CPU that meets the requirements, and the size of the single core may also be configured by programming. The architecture of the CPU211a can also be configured by programming, and can be configured as various types of architectures such as ARM, Power or X86. It is also possible to allocate a memory space of a specified size as a cache for the CPU211a by a programmed configuration. When the hardware configuration of the CPU211a is changed, the operating system program and other related data in the SSD223 need to be switched. In some embodiments, a reboot of the system is required to cause the CPU211a to reload the adapted operating system program. In other embodiments, a hot-swap approach may also be used, and the operating system and related data in SSD223 need not be rebooted after replacement.

In other embodiments, the neural network structure of the NPU211c may also be reconstructed by programming, for example, may be configured as any one of a plurality of neural network models such as CNN, RNN, Yolo, and DNN according to requirements. The calculation modules in the NPU211c include multiply-add, activation function, two-dimensional data operation, decompression and other modules, and can be flexibly configured according to requirements, and the hardware resources of each calculation module can also be flexibly configured through programming. After the NPU211c is reconfigured, information such as related training parameters stored in the corresponding GDDR222 also needs to be updated correspondingly to support the normal operation of the NPU211 c. Similarly, the GPU 211d may also be configured according to the graphics processing requirement, and the related supporting programs and/or data stored in the GDDR 221 are updated accordingly.

The routing path inside the FPGA chip 110 may also be configured by programming, and accordingly, the network transmission mode or transmission path between the FPGA chip and the network-on-chip subsystem 130 is changed.

Besides the internal memory, the embedded server subsystem may also be connected to an external memory through an interface, for example, an external SSD memory, to expand the storage space.

Referring to fig. 4, an embedded server subsystem according to another embodiment of the present invention is shown.

In this embodiment, the embedded server subsystem further includes: the circuit board 300, the FPGA chip 110, the memory 120 and the on-chip network subsystem 130 are all disposed on the circuit board 300; various types of interfaces are also configured on the circuit board 300.

As an example, in this embodiment, the circuit board 300 is configured with a pce interface 311, an ethernet interface 312, and a QSFP (four-channel SFP) interface 313 for different interface requirements. Each interface is connected with other modules on the circuit board through electrical connection traces on the circuit board 300. Each interface and the trace on the circuit board 300 are fixed, and flexible configuration cannot be performed, so that a variety of common and general interfaces can be configured on the circuit board 300, and the trace on the circuit 300 can be reasonably involved, so as to support flexible configuration of the FPGA chip 110.

The QSFP (four-channel SFP) interface 313 may connect the memory to the FPGA chip 110 in a pluggable manner, and after the configuration of each logic operation unit in the FPGA chip 110 is changed, the external memory may be directly replaced, and the replaced memory stores a corresponding Operating System (OS) or other programs and/or data corresponding to the current configuration.

The embedded server subsystem can be flexibly applied to different application scenes such as edge calculation of different artificial intelligence inferences, monitoring aiming at different transaction algorithms, cache sizes required by different application program sizes, different architectures aiming at hardware requirements of different response delays and the like, and is configured through software programming so as to be flexibly applied to various functional requirements.

The embodiment of the invention also provides a configuration method of the embedded server subsystem.

Fig. 5 is a flowchart illustrating a configuration method of an embedded server subsystem according to an embodiment of the present invention.

In this embodiment, the configuration method includes the following steps:

step S501: an embedded server subsystem is provided.

The embedded service subsystem is as described in the above embodiments, and is not described herein in detail.

Step S502: according to application requirements, a programmable logic gate array (FPGA) chip in the embedded server subsystem is subjected to programming reconstruction, and a plurality of programmable logic operation units are configured in the FPGA chip, so that the configuration of the programmable logic operation units is dynamically changed along with the change of the application requirements.

The FPGA chip internally comprises a programmable logic unit array, and a plurality of logic units can be combined to form a programmable logic operation unit with intelligent specific logic operation function by programming the programmable logic unit array and connecting the logic units. The connection relation between the programmable logic units can also realize customization of the programming of the FPGA chip according to the requirement. And with the change of the application requirement, the programming in the FPGA chip can be dynamically changed at any time, and the configuration of the programmable logic unit is changed.

The programmable logic operation unit comprises: programmable CPU, programmable GPU, programmable NPU, programmable TPU, coding and decoding unit and the like. According to different application scenarios, parameters of each programmable logic operation unit in the FPGA chip can be configured through programming, wherein the parameters comprise: at least one of the number of cores, the size of the cores, the architecture of the cores, the size of the cache, the routing path, and the configuration of the artificial intelligence algorithm.

Step S503: and switching programs and/or data in the memory along with the configuration change of the programmable logic operation unit so as to support the operation of the programmable logic operation unit after the configuration change.

Each programmable logic operation unit configured in the FPGA in the embedded server subsystem is connected to a corresponding memory, and when the configuration of the programmable logic operation unit changes, programs and/or data stored in the corresponding memory need to be updated synchronously so as to support the function of the reconfigured programmable logic operation unit. The method can be realized by updating the content in the original memory or directly replacing the memory. If necessary, it can be restarted so that the programmable logic unit reloads the necessary programs and/or data.

The routing path inside the FPGA chip can also be configured through programming, and the network transmission mode or transmission path between the FPGA chip and the on-chip network subsystem is correspondingly changed.

The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.