阅读说明：本技术 加速提取电阻的方法、电子设备及计算机可读存储介质 (Method for accelerating extraction of resistance, electronic device and computer-readable storage medium ) 是由 莫文韬 谢林君 李相启 陆涛涛 刘伟平 于 2020-12-14 设计创作，主要内容包括：一种加速提取电阻的方法,包括以下步骤：将版图图形转化为图像矩阵；对图像矩阵进行计算,分割出阵列区域图形；对图像矩阵进行识别,对分割后的版图图形进行分组；计算每一组电阻,获得版图图形的电阻。本发明的加速提取电阻的方法,可以自动的对图形进行分割,将大量的阵列图形的电阻计算简化为几组图形的电阻计算,从而大大缩减电阻提取的时间。同时因为阵列图形的相似性,也可以保证电阻提取的精度不受太大影响,确保电阻提取的正确性。(A method of accelerating the extraction of a resistance, comprising the steps of: converting the layout graph into an image matrix; calculating an image matrix and segmenting an array region graph; identifying the image matrix, and grouping the divided layout graphs; and calculating each group of resistance to obtain the resistance of the layout graph. The method for accelerating the extraction of the resistance can automatically segment the graph, and simplify the resistance calculation of a large number of array graphs into the resistance calculation of a plurality of groups of graphs, thereby greatly shortening the time for extracting the resistance. Meanwhile, due to the similarity of the array patterns, the accuracy of resistance extraction can be guaranteed not to be greatly influenced, and the correctness of resistance extraction is guaranteed.)

1. A method of accelerating electrical resistance extraction, comprising the steps of:

converting the layout graph into an image matrix;

calculating an image matrix and segmenting an array region graph;

identifying the image matrix, and grouping the divided layout graphs;

and calculating each group of resistance to obtain the resistance of the layout graph.

2. The method for accelerating electrical resistance extraction according to claim 1, wherein said step of converting layout patterns into image matrices further comprises,

carrying out grid division on the calculation area to divide the calculation area into a plurality of unit areas;

and assigning a value to each unit area according to the position of the layout graph in the calculation area to obtain a graph matrix of the calculation area.

3. The method for accelerating resistance extraction according to claim 2, wherein the step of assigning a value to each unit region according to the position of the layout pattern in the calculation region further comprises setting the unit region to 1 if there is an intersection between the layout pattern and the unit region, and otherwise setting the unit region to 0.

4. The method of claim 1, wherein the step of computing an image matrix to segment the pattern of array regions further comprises,

traversing each layer of graph matrix, and recording the start and end coordinates of the continuous non-zero element area;

and judging the relationship between the two adjacent layers of element graphs according to the continuous area coordinates of the two adjacent layers of graph matrixes, and storing the positions of the non-overlapped graph matrixes.

5. The method of claim 1, wherein the step of computing an image matrix to segment the pattern of array regions further comprises,

and judging the relation of the graphics of the two overlapped layers according to the distance difference of the boundaries of the overlapped regions of the two adjacent layers, cutting at the junction of the graphics, obtaining the divided layout graphics, and respectively storing the matrix positions.

6. The method for accelerating electrical resistance extraction according to claim 1, wherein said steps of identifying an image matrix, grouping the segmented layout patterns further comprises,

according to the divided graph matrix, identifying all stored layout graphs, and dividing the layout graphs similar to the graph matrix into a group;

one pattern in each group is selected for resistance calculation, and the resistance of other patterns in the group is regarded as the same.

7. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for accelerating resistance extraction according to any one of claims 1 to 6.

8. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program executes the steps of the method of accelerating electrical resistance extraction according to any one of claims 1 to 6.

Technical Field

The invention relates to the technical field of automatic design of semiconductor integrated circuits, in particular to a method for extracting resistors in back-end layout design and graphic processing.

Background

In the chip design process, in order to check the design performance and find out the problem in advance, simulation needs to be performed according to the layout, the circuit characteristics and the expected performance of the layout are calculated, and errors are conveniently found and design optimization is conveniently performed. In order to calculate different characteristics of the layout, the calculation of the resistance is necessary, and the resistance corresponding to each position of the layout needs to be calculated according to the graph. The resistance calculation generally adopts a method of regional integral solution, and the calculated amount of the resistance calculation is positively correlated with the scale and the complexity of the layout. In order to meet the performance requirement which is continuously improved, more special-shaped graphs are adopted in the layout during design, the graphs are complex in structure and large in quantity, a large amount of time is consumed for all calculation, along with the further improvement of the complexity of the layout, the time for calculating the special-shaped graphs is also continuously increased, and the extraction speed of the part needs to be accelerated.

Disclosure of Invention

In order to solve the defects of the prior art, the invention aims to provide a method for accelerating the extraction of the resistor, which identifies the special-shaped pattern of the array by identifying and dividing the layout pattern, calculates the resistor of only one pattern in the array and other array patterns, and directly multiplexes the resistance value of a single pattern on the premise of ensuring the precision, thereby reducing the calculation time of the special-shaped pattern and accelerating the extraction speed of the resistor.

In order to achieve the above object, the present invention provides a method for accelerating extraction of resistance, comprising the following steps:

converting the layout graph into an image matrix;

calculating an image matrix and segmenting an array region graph;

identifying the image matrix, and grouping the divided layout graphs;

and calculating each group of resistance to obtain the resistance of the layout graph.

Further, the step of converting the layout graph into the image matrix further comprises,

carrying out grid division on the calculation area to divide the calculation area into a plurality of unit areas;

and assigning a value to each unit area according to the position of the layout graph in the calculation area to obtain a graph matrix of the calculation area.

Further, the step of assigning a value to each unit region according to the position of the layout graph in the calculation region further includes setting the unit region to 1 if the intersection exists between the layout graph and the unit region, and otherwise setting the unit region to 0.

Further, the step of calculating the image matrix and segmenting the array region graph further comprises,

traversing each layer of graph matrix, and recording the start and end coordinates of the continuous non-zero element area;

and judging the relationship between the two adjacent layers of element graphs according to the continuous area coordinates of the two adjacent layers of graph matrixes, and storing the positions of the non-overlapped graph matrixes.

Further, the step of calculating the image matrix and segmenting the array region graph further comprises,

and judging the relation of the graphics of the two overlapped layers according to the distance difference of the boundaries of the overlapped regions of the two adjacent layers, cutting at the junction of the graphics, obtaining the divided layout graphics, and respectively storing the matrix positions.

Furthermore, the step of identifying the image matrix and grouping the divided layout graphs further comprises,

and identifying all stored layout graphs according to the divided graph matrix, and dividing the layout graphs similar to the graph matrix into a group.

One pattern in each group is selected for resistance calculation, and the resistance of other patterns in the group is regarded as the same.

To achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to execute the steps of the method for accelerating the resistance extraction.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when running, performs the steps of the method of accelerating the extraction of a resistance as described above.

The method for accelerating the extraction of the resistor has the following beneficial effects:

since all patterns in the special-shaped array must be integrated to accurately calculate the resistance before the image is not segmented, when the layout scale is large, the number of patterns in the array is increased, resulting in long calculation time.

The method for accelerating the extraction of the resistance can automatically segment the graph, and simplify the resistance calculation of a large number of array graphs into the resistance calculation of a plurality of groups of graphs, thereby greatly shortening the time for extracting the resistance. Meanwhile, due to the similarity of the array patterns, the accuracy of resistance extraction can be guaranteed not to be greatly influenced, and the correctness of resistance extraction is guaranteed.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a method of accelerating resistance extraction according to the present invention;

FIG. 2 is a schematic diagram of a grid-divided graphical region according to the present invention;

FIG. 3 is a schematic diagram of matrixing a graph according to graph position according to the present invention;

FIG. 4 is a schematic diagram illustrating determining an overlap position according to boundary coordinates according to the present invention;

FIG. 5 is a diagram illustrating a graph divided according to a variation difference according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

For the resistance calculation of the layout, after the graph is triangulated, the resistance of the corresponding area is separately calculated for each triangle in an integral manner. When the layout scale is large, a layer of graphics may be divided into tens of thousands of small triangles, each of which is calculated separately. For non-standard special-shaped graphs, the corresponding graph characteristics can be correctly described only by adopting more detailed subdivision, and when the number of the special-shaped graphs is more, the number of triangles needing to be calculated is also more huge, and the time consumption is more. According to the pattern characteristics of a layout in chip design, the special-shaped patterns in the layout mostly exist in an array mode, namely, a large number of multiplexing patterns exist. These multiplexed patterns have the same shape and the same resistivity, so their resistances can also be considered to be the same. In consideration of the characteristics of the pattern, in the embodiment of the invention, the layout pattern is identified and divided, the special-shaped patterns of the array are all identified independently, the resistance of only one pattern in the array is calculated, and the resistance value of a single pattern is directly reused on the premise of ensuring the precision, so that the calculation time of the special-shaped pattern is shortened, and the resistance extraction speed is accelerated.

In the embodiment of the invention, when the resistor is calculated for the layout with the special-shaped array, the boundary between the special-shaped pattern and the regular pattern is identified by calculating the image matrix according to the pattern characteristics, and the special-shaped pattern and the regular pattern are divided and respectively calculated.

Fig. 1 is a flowchart of a method for accelerating resistance extraction according to the present invention, and the method for accelerating resistance extraction according to the present invention will be described in detail with reference to fig. 1.

First, in step 101, a calculation region is subjected to meshing.

In the embodiment of the present invention, assuming that the width of the calculation region is W and the height is H, the calculation region of W × H is divided into (W/n) × (H/n) unit regions by meshing the calculation region with unit cells having a side length of n. Wherein the side length n of the unit square is far less than W and H. As shown in fig. 2, the lower "sugarcoated haws" graphical area is gridded.

In step 102, the unit area is assigned to obtain a graphic matrix of the calculation area.

In the embodiment of the invention, assignment is performed on a unit region according to the position of a layout graph in a calculation region, if the graph and the unit region have intersection, the unit region is set to be 1, otherwise, the unit region is set to be 0, after assignment is completed on all the unit regions, a graph matrix M of the calculation region is obtained, and the mapping relation between the graph matrix M and the position of the unit region is recorded, as shown in FIG. 3.

In step 103, whether two layers of elements are overlapped is judged according to the continuous area coordinates of two adjacent layers of matrixes, and the non-overlapped graph is stored.

In the embodiment of the invention, the graph matrixes are traversed layer by layer from bottom to top, the start and end coordinates of the continuous non-zero element area are recorded, whether the two layers of elements are overlapped or not is judged according to the continuous area coordinates of the two adjacent layers of matrixes, if the two layers of elements are not overlapped, the two layers of elements belong to different graphs and are respectively stored, otherwise, the next step is carried out. As shown in fig. 4, the coordinates of the red region boundary are all within the blue region boundary, so there is overlap between the red region and the blue region, and the red region boundary is not related to the green region boundary, so the red and green regions belong to different patterns.

In step 104, different graphs are identified according to the distance difference of the boundary of the overlapped area of the two adjacent layers, and the overlapped graphs are divided and stored.

In the embodiment of the invention, the distance difference of the boundary of the overlapped area of two adjacent layers is calculated, and if the distance difference of the two sections is smaller than a threshold value, the two layers belong to the same graph; otherwise, the patterns do not belong to the same pattern, cutting is carried out, the upper layer and the lower layer are divided into two patterns, and the matrix positions are stored respectively. As shown in fig. 5, since the coordinate distances of the red and blue boundaries are both 1, the red and green colors are the same pattern. The red and violet border distances are 5 and 16, so red and violet are not the same graphic, separating it from the red layer.

In step 105, all the stored patterns are identified and grouped, and the resistance is calculated.

In the embodiment of the present invention, the above steps 103 and 104 are repeated, after all the steps are completed, the divided graph matrix is obtained, all the stored graphs are identified, the graphs with basically similar graph matrices are divided into one group, only one graph in each group needs to be subjected to resistance calculation, the resistance is set to be R, because the graphs are basically the same, and the resistance values of other graphs in the same group are also set to be R. As shown in fig. 5, the resistance of only one "sugarcoated haws" shaped area needs to be calculated.

At step 106, the resistance of the complete pattern is calculated from the relative positions of the various patterns.

The method for accelerating the resistance extraction can divide the layout graph, identify the graph of the array according to the characteristics of the graph, reduce the total number of the graphs needing to be calculated and accelerate the resistance extraction speed.

The example graph proportion is only used for the visual explanation of the method provided by the text, and the value of n should be a very small value in order to ensure the precision in the actual calculation, so that the method is suitable for calculating all layout resistors.

To achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to execute the steps of the method for accelerating resistance extraction.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when running, performs the steps of the method of accelerating resistance extraction as described above.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.