阅读说明：本技术 一种半导体器件及其制作方法 (Semiconductor device and manufacturing method thereof ) 是由 薛广杰 于 2020-12-07 设计创作，主要内容包括：本发明提供一种半导体器件及其制作方法,半导体器件的制作方法包括：提供第一晶圆,第一晶圆具有相对的第一表面和第二表面,所述第一晶圆包括多个第一器件区域以及多个第二器件区域,第一器件区域与第二器件区域间隔设置；在第一晶圆的第一表面对应第一器件区域的位置处刻蚀出凹槽；在凹槽的侧壁形成隔离层；在凹槽的底壁生长外延层；在每一第一器件区域以及第二器件区域上制备一个器件单元；从第二表面对所述第一晶圆进行减薄,使得隔离层从所述第二表面暴露,相邻的器件单元被所述隔离层完全隔离。通过上述方法避免相邻的器件单元之间信号串扰,进而提高器件的性能,并且能够将隔离层的厚度微缩,替代深沟槽工艺。(The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite, the first wafer comprises a plurality of first device areas and a plurality of second device areas, and the first device areas and the second device areas are arranged at intervals; etching a groove at a position, corresponding to the first device area, of the first surface of the first wafer; forming an isolation layer on the side wall of the groove; growing an epitaxial layer on the bottom wall of the groove; preparing a device unit on each of the first device region and the second device region; thinning the first wafer from a second surface such that an isolation layer is exposed from the second surface, adjacent device units being completely isolated by the isolation layer. By the method, signal crosstalk between adjacent device units is avoided, the performance of the device is improved, and the thickness of the isolation layer can be reduced to replace a deep groove process.)

1. A method for manufacturing a semiconductor device, comprising:

providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of first device areas and a plurality of second device areas, and the first device areas and the second device areas are arranged at intervals;

etching a groove at a position, corresponding to the first device region, of the first surface of the first wafer;

forming an isolation layer on the side wall of the groove;

growing an epitaxial layer on the bottom wall of the groove;

preparing a device unit on each of the first device region and the second device region;

thinning the first wafer from the second surface such that the isolation layer is exposed from the second surface, the adjacent device units being completely isolated by the isolation layer.

2. The method of claim 1, wherein forming an isolation layer on sidewalls of the recess comprises:

and forming the isolation layer on the side wall and the bottom wall of the groove by adopting a thermal oxidation or chemical vapor deposition process.

3. The method of claim 2, wherein the isolation layer is an oxide layer.

4. The method of claim 2, wherein the isolation layer is removed from the bottom wall of the recess before the epitaxial layer is grown on the bottom wall of the recess.

5. The method of claim 1, wherein the thickness of the spacer layer on the sidewall is 15nm to 25 nm.

6. The method of claim 1, wherein after growing an epitaxial layer on the bottom wall of the recess and before fabricating a device cell on each of the first and second device regions, further comprising:

and carrying out planarization treatment on the first surface of the first wafer.

7. The method of claim 1, wherein thinning the second surface of the first wafer such that the isolation layer is exposed from the second surface comprises:

providing a second wafer;

and bonding the second wafer and the first surface of the first wafer.

8. The method of claim 2, wherein before providing the recess on the first surface of the first wafer at the location corresponding to the first device region, further comprising:

depositing a protective layer on the first surface of the first wafer;

after the epitaxial layer grows on the bottom wall of the groove, the method also comprises the following steps before the device unit is prepared:

and removing the protective layer.

9. A semiconductor device, comprising:

the wafer comprises a first wafer, a second wafer and a plurality of first and second semiconductor chips, wherein the first wafer is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of first device areas and a plurality of second device areas, the first device areas and the second device areas are arranged at intervals, and device units are arranged on the first device areas and the second device areas;

and the isolation layer is positioned between the two adjacent first device areas and the second device area, extends from the first surface to the second surface of the wafer, completely isolates the two adjacent device units, and has the thickness of 15 nm-25 nm.

10. The semiconductor device according to claim 9, wherein the isolation layer is an oxide layer.

11. The semiconductor device of claim 9, wherein the semiconductor device comprises a second wafer bonded to the first wafer.

12. The semiconductor device according to claim 9, wherein the semiconductor device is a back-illuminated image sensor.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

The conversion efficiency of light in a semiconductor device (such as a backside illuminated sensor) is the most important performance parameter, and there are often extremely high requirements on the dark current requirement and the light absorption scattering rate, and in the backside illuminated process, crosstalk often exists between device units, which affects the performance of the device. In the prior art, in order to solve the problem of crosstalk between device units, a deep trench process is generally used for arranging deep trenches between the device units and filling an isolation layer, but because the size of the deep trench isolation process is shrunk to have a process limit, the existing deep trench isolation process cannot be shrunk continuously in the process of developing a semiconductor along with moore's law, only a shallow region can be isolated, the requirements cannot be met, and the deep trench isolation effect is poor.

Disclosure of Invention

The invention provides a semiconductor device and a manufacturing method thereof, which are used for avoiding signal crosstalk between adjacent device units so as to improve the performance of the device, and can shrink the thickness of an isolation layer to replace a deep trench process.

In order to solve the above technical problems, a first technical solution provided by the present invention is: provided is a method for manufacturing a semiconductor device, comprising: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of first device areas and a plurality of second device areas, and the first device areas and the second device areas are arranged at intervals; etching a groove at a position, corresponding to the first device region, of the first surface of the first wafer; forming an isolation layer on the side wall of the groove; growing an epitaxial layer on the bottom wall of the groove; preparing a device unit on each of the first device region and the second device region; thinning the first wafer from the second surface such that the isolation layer is exposed from the second surface, the adjacent device units being completely isolated by the isolation layer.

Wherein forming an isolation layer on sidewalls of the recess comprises: forming the isolation layer on the side wall and the bottom wall of the groove by adopting a thermal oxidation or chemical vapor deposition process;

wherein the isolation layer is an oxide layer.

And removing the isolating layer on the bottom wall of the groove before the epitaxial layer grows on the bottom wall of the groove.

Wherein the thickness of the isolation layer on the side wall is 15 nm-25 nm.

After an epitaxial layer is grown on the bottom wall of the groove and before a device unit is prepared in each of the first device region and the second device region, the method further comprises the following steps: and carrying out planarization treatment on the first surface of the first wafer.

Wherein thinning the second surface of the first wafer such that the isolation layer is exposed from the second surface comprises: providing a second wafer; and bonding the second wafer and the first surface of the first wafer.

Before the groove is arranged at the position, corresponding to the first device region, of the first surface of the first wafer, the method further comprises the following steps: depositing a protective layer on the first surface of the first wafer; after the epitaxial layer grows on the bottom wall of the groove, the method also comprises the following steps before the device unit is prepared: and removing the protective layer.

In order to solve the above technical problems, a second technical solution provided by the present invention is: provided is a semiconductor device including: the wafer comprises a first wafer, a second wafer and a plurality of first and second semiconductor chips, wherein the first wafer is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of first device areas and a plurality of second device areas, the first device areas and the second device areas are arranged at intervals, and device units are arranged on the first device areas and the second device areas; and the isolation layer is positioned between the two adjacent first device areas and the second device area, extends from the first surface to the second surface of the wafer, completely isolates the two adjacent device units, and has the thickness of 15 nm-25 nm.

Wherein the isolation layer is an oxide layer.

Wherein the semiconductor device includes a second wafer bonded to the first wafer.

Wherein the semiconductor device is a back-illuminated image sensor.

The method has the beneficial effects that the method is different from the prior art, grooves are etched in the positions, corresponding to the first device areas, of the first device areas and the second device areas which are arranged at intervals on the first wafer; forming an isolation layer on the side wall of the groove; growing an epitaxial layer on the bottom wall of the groove; preparing a device unit on each of the first device region and the second device region; thinning the first wafer from the second surface such that the isolation layer is exposed from the second surface, the adjacent device units being completely isolated by the isolation layer. The isolation layer is prepared by the method, so that the thickness of the isolation layer is reduced, a deep groove process is replaced, signal isolation between adjacent device units is realized, and crosstalk is prevented.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

fig. 1 is a schematic structural diagram of a semiconductor device in the prior art;

FIG. 2 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention;

FIG. 3 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a schematic flow chart illustrating a method for fabricating a semiconductor device according to a third embodiment of the present invention;

FIGS. 5 a-5 g are schematic structural diagrams illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship. Further, the term "plurality" herein means two or more than two.

The terms "first", "second" and "third" in the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include at least one of the described features. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. All directional indicators such as up, down, left, right, front, and rear … … in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly. The terms "comprising" and "having" and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or may alternatively include other steps or elements inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In the prior art, a back-illuminated Deep Trench Isolation (DTI) process is usually used to solve the crosstalk problem between device units, but since the first silicon wafer is thick, the size of the deep trench isolation process is shrunk to have a process limit, and in the process of developing a semiconductor along with moore's law, the existing deep trench isolation process cannot be shrunk continuously, can only isolate a shallow region, and cannot meet the requirements. Referring to fig. 1, an isolation structure in the prior art is shown. In the prior art, the isolation structure 10 is generally formed on the front surface by using a shallow trench isolation process, and the device unit 11 and the device unit 12 are isolated by using the isolation structure 10, as shown in fig. 1, the isolation structure 10 cannot completely isolate the device unit 11 from the device unit 12. After the back surface is thinned, the isolation structure 13 is manufactured by using a deep trench isolation process, as shown in fig. 1, the isolation structure 13 manufactured by the deep trench isolation process has a large area and is limited in size shrinkage. Therefore, there is a need for an improved semiconductor device and a method for fabricating the same to solve the above problems, which will be described in detail with reference to the accompanying drawings and embodiments.

Referring to fig. 2, a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention includes:

step S21: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite, the first surface comprises a plurality of first device areas and a plurality of second device areas, and the first device areas and the second device areas are arranged at intervals.

Specifically, referring to fig. 5a, the first wafer 81 has a first surface 811 and a second surface 812 opposite to each other, and referring to fig. 5b, the first surface 811 includes a plurality of first device regions 814 and a plurality of second device regions 813, and the first device regions 814 and the second device regions 813 are disposed at intervals. The material of the first wafer 81 may be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, etc., or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be another material such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, etc., or may be a combination of the above materials. Doped epitaxial layers, graded semiconductor layers, and semiconductor layers overlying other semiconductor layers of different types (e.g., a silicon layer on a silicon germanium layer) may also be included. The first wafer 81 is a silicon substrate, for example, and may be a doped substrate. The size and thickness of the first wafer 81 are not limited and may be selected as desired. In one embodiment, first wafer 81 is a single crystal silicon wafer. In another embodiment, the first wafer 81 includes a silicon wafer and an epitaxial layer grown on the surface of the silicon wafer.

Step S22: and etching a groove at the position of the first surface of the first wafer, which corresponds to the first device area.

Specifically, referring to fig. 5c, a groove 84 is etched on the first surface 811 of the first wafer 81 at a position corresponding to the first device region 814.

In one embodiment, to protect the first surface 811 of the first wafer 81, a protective layer 83 may be formed on the first surface 811 of the first wafer 81 before the grooves 84 are formed, as shown in fig. 5a, and the protective layer 83 is used to protect the first surface 811 of the first wafer 81 from being damaged during the process of etching the grooves 84. In one embodiment, the protection layer 83 may be a sacrificial oxide layer.

In one embodiment, a photoresist is formed on the first surface 811 of the first wafer 81, exposed and developed to expose the position where the groove 84 needs to be made, the exposed position is etched to form the groove 84, the photoresist on the first surface 811 is removed by ashing and cleaning, and the groove 84 is cleaned.

Step S23: and forming an isolation layer on the side wall of the groove.

Specifically, referring to fig. 5c, an isolation layer 85 is formed on the sidewall and the bottom wall of the recess 84. In one embodiment, the isolation layer 85 may be formed on the sidewalls and bottom wall of the recess 84 by thermal oxidation or chemical vapor deposition; the material of the isolation layer 85 may be an oxide layer. In another embodiment, the isolation layer 85 may be formed by depositing an oxide layer on the entire wall surface of the groove 84 using a thin film deposition process, or may also be formed by oxidizing the entire wall surface of the groove 84 through an oxidation process. For example, the entire wall surface of the silicon recess 84 is oxidized by a thermal oxidation process to form a silicon oxide layer. The spacers 85 on the bottom wall of the recess 84 are removed, leaving the spacers 85 on the sidewalls of the recess 84 as shown in fig. 5 d.

The isolation layer 85 is formed to be thin, and in one embodiment, the thickness D of the isolation layer 85 is 15nm to 25 nm; preferably, the thickness D of the isolation layer 85 may be 20 nm. The thickness D of the isolation layer 85 is a dimension in a direction parallel to the first surface 811 of the first wafer 81. In one embodiment, the isolation layer 85 can withstand voltages greater than 20V.

Step S24: and growing an epitaxial layer on the bottom wall of the groove.

Specifically, referring to fig. 5d, an epitaxial layer 86 is grown from the bottom wall of the recess 84 by an epitaxial growth process, and the material of the epitaxial layer 86 is the same as that of the first wafer 81. The thickness of the epitaxial layer 86 is equal to or greater than the depth of the recess 84, and in the present embodiment, the thickness of the epitaxial layer 86 may be made equal to the depth of the recess 84. I.e., the epitaxial layer 86 just fills the recess 84 completely so that the epitaxial layer 86 fill area is flush with the surface of the second device region 813 and the first device region 814.

In another embodiment, the thickness of the epitaxial layer 86 may be made larger than the depth of the recess 84, so as to, in conjunction with fig. 3, in step S34: the method also comprises the following steps after the epitaxial layer grows on the bottom wall of the groove:

step S35: the first surface of the first wafer is planarized.

Specifically, the first surface 811 of the first wafer 81 is planarized to remove the portion of the epitaxial layer 86 protruding from the recess 84, so that the filling area of the epitaxial layer 86 is flush with the surfaces of the second device region 813 and the first device region 814. Specifically, in one embodiment, the protective layer 83 is further removed during the planarization process for the first surface 811 of the first wafer 81.

It should be understood that, in the embodiment shown in fig. 3, steps S31 to S34 and steps S36 to S37 are the same as those shown in fig. 2, and detailed description thereof is omitted.

Step S25: and preparing a device unit on each of the first device region and the second device region.

Specifically, one device unit 87 is prepared on the first surface of the first wafer 81 corresponding to the first device region 814 and the second device region 813. A doped region, which may be a photodoped region of opposite conductivity type to the dopant ions in the substrate, is formed in the device region to form a photodiode for converting photons in incident light into electrons, with each device cell 87 being located on the doped region in the substrate. The device unit is an electronic device, such as a transistor, manufactured by a semiconductor process. In an embodiment, the device unit 87 may be a semiconductor device fabricated based on the material of the first wafer 81, which may be processed to form the device unit 87 by processing the material of the first wafer 81. Further, after the device unit 87 is manufactured, an interconnection structure connected to the device unit 87 may be further manufactured. The interconnect structure is used to connect the device unit 87 with an external circuit. The interconnect structure is the same as that in the prior art and will not be described herein.

The first wafer 81 is a backside illuminated image sensor wafer.

Step S26: thinning the first wafer from the second surface such that the isolation layer is exposed from the second surface, the adjacent device units being completely isolated by the isolation layer.

Specifically, when the second surface 812 of the first wafer 81 is thinned, the second surface 812 of the first wafer 81 needs to be exposed so as to be etched. Referring to fig. 4, the method for manufacturing a semiconductor device further includes:

step S47: a second wafer is provided.

Specifically, the second wafer 90 may be made of the same material as the first wafer 81, or may be made of a different material. The second wafer 90 may be a blank wafer for carrying only or a device-capable structure wafer.

Step S48: and bonding the second wafer and the first surface of the first wafer.

Referring to fig. 5f, a second wafer 90 is bonded to the first surface 811 of the first wafer 81, or the second wafer 90 is bonded to the side of the device unit 87. After bonding is complete, it is flipped over to expose second surface 812. At this time, the first wafer 81 is thinned from the second surface 812 side. Specifically, the second surface 812 is thinned to expose the isolation layer 85 from the second surface 812, so that the adjacent device units 87 are completely isolated by the isolation layer 85, and further signal crosstalk between the adjacent device units 87 is prevented, as shown in fig. 5 g.

The steps 41 to S46 and S49 shown in fig. 4 are the same as the steps S31 to S37 shown in fig. 3, and are not repeated here.

By means of the present application, the sidewall of one groove 84 is provided with an isolation layer 85, which can isolate the device unit 87 around the position of the groove 84 from the device unit 87 formed at the position of the groove 84, specifically, the isolation layer 85 is used for completely isolating the signal between the device unit 87 around the position of the groove 84 and the device unit 87 formed at the position of the groove 84, so as to reduce the crosstalk between the device units 87, thereby improving the performance of the device.

In one embodiment, to enable the isolation layer 85 to completely isolate the device unit 87, the depth of the recess 84 is greater than or equal to the thickness of the doped region in the substrate, i.e., the depth of the recess is greater than or equal to the thickness of the doped region below the device unit, so as to completely isolate the device unit.

According to the manufacturing method of the semiconductor device, the grooves are arranged, the isolation layers are arranged on the side walls of the grooves, so that the two adjacent device units are completely isolated, the size of the deep groove isolation process can be reduced, the shallow groove isolation process is replaced, the crosstalk between the device units is avoided, and the performance of the device is improved.

Fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention. Specifically, the semiconductor device includes: the first wafer 20, the first wafer 20 having a first surface 211 and a second surface 212 opposite to each other, the first surface 211 including a plurality of first device regions 213 and a plurality of second device regions 214, the first device regions 213 being spaced apart from the second device regions 214. In one embodiment, the material of the first wafer 20 may be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, etc., or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be other materials such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, etc., or may be a combination thereof. Doped epitaxial layers, graded semiconductor layers, and semiconductor layers overlying other semiconductor layers of different types (e.g., a silicon layer on a silicon germanium layer) may also be included. The first wafer 20 is here, for example, a silicon substrate, which may be a doped substrate. The size and thickness of the first wafer 20 are not limited and may be selected as desired. In one embodiment, the first wafer 20 is a monocrystalline silicon wafer. In another embodiment, the first wafer 20 includes a silicon wafer and an epitaxial layer grown on the surface of the silicon wafer.

An isolation layer 23 is further disposed between two adjacent first device regions 213 and second device regions 214, and device units 24 are disposed on the first device regions 213 and the second device regions 214; the isolation layer 23 extends from the first surface 211 to the second surface 212 of the first wafer 20, and the isolation layer 20 completely isolates two adjacent device units 24, in an embodiment, a thickness D of the isolation layer 23 is 15nm to 25nm, and preferably, a thickness D of the isolation layer 23 is 20 nm. The material of the isolation layer 23 may be an oxide layer. In one embodiment, the isolation layer 23 can withstand a voltage greater than 20V.

In one embodiment, the semiconductor device is a back-illuminated image sensor.

Further, the semiconductor device further includes a second wafer 21 bonded to the first wafer 20, the second wafer 21 being bonded to the first surface of the first wafer 20, wherein the second wafer 21 and the first wafer 20 may be made of the same material or different materials. The second wafer 21 may be a blank wafer for carrying only or a structural wafer with device function.

According to the semiconductor device, the isolation layer which completely isolates the two adjacent device units is arranged between the two adjacent device units, and the thickness of the isolation layer is 15 nm-25 nm, so that the purpose of avoiding crosstalk of the adjacent device units can be achieved, the size of a deep trench isolation process can be reduced, and the shallow trench isolation process is replaced.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.