阅读说明：本技术 Cmos图像传感器 (CMOS image sensor ) 是由 陈翔 许隽 金立培 于 2020-12-14 设计创作，主要内容包括：本申请涉及半导体集成电路制造技术领域,具体涉及一种CMOS图像传感器。所述CMOS图像传感器包括：像素区,所述像素区包括光电二极管,所述光电二极管上覆盖有金属硅化物阻挡层,所述金属硅化物阻挡层包括富硅氧化物；所述光电二极管的源漏区的表层形成耗尽层,所述耗尽层与所述金属硅化物阻挡层接触。本申请提供的CMOS图像传感器,能够缓解因杂质离子过量而引起的白色像素问题,同时该金属硅化物阻挡层能够有效地防止外部金属离子进入该像素区,防止因金属离子进入像素区而引起的白色像素问题。(The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a CMOS image sensor. The CMOS image sensor includes: the pixel region comprises a photodiode, a metal silicide blocking layer covers the photodiode, and the metal silicide blocking layer comprises silicon-rich oxide; and a depletion layer is formed on the surface layer of the source drain region of the photodiode, and the depletion layer is in contact with the metal silicide barrier layer. The CMOS image sensor provided by the application can relieve the white pixel problem caused by excessive impurity ions, and meanwhile, the metal silicide barrier layer can effectively prevent external metal ions from entering the pixel region and prevent the white pixel problem caused by the fact that the metal ions enter the pixel region.)

1. A CMOS image sensor, comprising:

the pixel region comprises a photodiode, a metal silicide blocking layer covers the photodiode, and the metal silicide blocking layer comprises silicon-rich oxide; and a depletion layer is formed on the surface layer of the source drain region of the photodiode, and the depletion layer is in contact with the metal silicide barrier layer.

2. The CMOS image sensor as in claim 1, wherein the pixel region comprises a plurality of photodiodes, the plurality of photodiodes being arranged in an array.

3. The CMOS image sensor according to claim 1, wherein the source and drain regions of the photodiode include a first-conductivity-type doped region, a second-conductivity-type doped region is formed around the first-conductivity-type doped region, and the second-conductivity-type doped region located on an upper surface of the first-conductivity-type doped region is the depletion layer.

4. The CMOS image sensor according to claim 3, wherein the depletion layer is formed by implanting second conductivity type impurity ions into an upper surface of the first conductivity type doped region, the second conductivity type impurity ions neutralizing a surface layer of the first conductivity type doped region.

5. The CMOS image sensor of claim 1, wherein the depletion layer has a thickness of 200A to 300A.

6. The CMOS image sensor of claim 1, further comprising:

the semiconductor device comprises a logic area, wherein the logic area comprises a first conduction type device and a second conduction type device, and an isolation groove is arranged between the first conduction type device and the second conduction type device at an interval.

7. The CMOS image sensor of claim 1, wherein a metal silicide blocking layer is formed on the logic region, the metal silicide blocking layer comprising a silicon rich oxide.

8. The CMOS image sensor as in claim 7, wherein the metal silicide blocking layer of the logic region is etched to form a metal silicide pattern, and a metal silicide layer is deposited at the metal silicide pattern.

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a CMOS image sensor.

Background

At present, CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in the fields of cameras and the like. In order to obtain better photographing effect, the performance requirements for the CMOS image sensor are also increasing. The CMOS image sensor comprises a plurality of pixel units which are arranged in an array mode, and photoelectric conversion is achieved through the pixel units.

White Pixels (WP) are one of the key parameters for evaluating the performance of CMOS image sensors. Theoretically, the CMOS image sensor does not generate a photocurrent when receiving light, but in the manufacturing process of the CMOS image sensor, due to the influence of various factors such as the change of raw materials, process fluctuation, impurity ion contamination, etc., even if no light irradiates the pixel unit, the pixel unit itself generates charges, and the charges are continuously increased and aggregated together to form a dark current. When the dark current of a pixel unit exceeds the photocurrent generated by photoelectric conversion, the pixel unit is a white pixel unit.

The white pixel cell adversely affects the imaging of the CMOS image sensor.

Disclosure of Invention

The present application provides a CMOS image sensor that can improve the problem of white pixels in the related art.

The present application provides a CMOS image sensor, which includes:

the pixel region comprises a photodiode, a metal silicide blocking layer covers the photodiode, and the metal silicide blocking layer comprises silicon-rich oxide; and a depletion layer is formed on the surface layer of the source drain region of the photodiode, and the depletion layer is in contact with the metal silicide barrier layer.

Optionally, the pixel region includes a plurality of photodiodes, and the photodiodes are arranged in an array.

Optionally, the source-drain region of the photodiode includes a first conductive type doped region, a second conductive type doped region is formed around the first conductive type doped region, and the second conductive type doped region located on the upper surface of the first conductive type doped region is the depletion layer.

Optionally, second conductive type impurity ions are implanted into the upper surface of the first conductive type doped region, and the depletion layer is formed after the second conductive type impurity ions neutralize the surface layer of the first conductive type doped region.

Optionally, the thickness of the depletion layer is 200A to 300A.

Optionally, the CMOS image sensor further includes:

the semiconductor device comprises a logic area, wherein the logic area comprises a first conduction type device and a second conduction type device, and an isolation groove is arranged between the first conduction type device and the second conduction type device at an interval.

Optionally, a metal silicide blocking layer is formed on the logic region, and the metal silicide blocking layer includes a silicon-rich oxide.

Optionally, a metal silicide pattern is formed on the metal silicide blocking layer of the logic region by etching, and a metal silicide layer is formed at the metal silicide pattern by deposition.

The technical scheme at least comprises the following advantages: the technical scheme that this application provided can alleviate the white pixel problem that arouses because of impurity ion is excessive, and this metal silicide barrier layer can prevent outside metal ion entering this pixel area effectively simultaneously, prevents the white pixel problem that arouses because of metal ion entering pixel area.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a cross-sectional structure of a CMOS image sensor according to an embodiment of the present application;

fig. 2 shows an enlarged structural diagram of the source and drain regions of fig. 1.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

The first conductivity type and the second conductivity type described in this application are opposite, and in this embodiment, the first conductivity type is an N-type, and the second conductivity type is a P-type. In other embodiments of the present application, the first conductive type may also be a P-type, and the second conductive type is an N-type. Where N-type refers to a type of semiconductor material in which an impurity ion of a pentavalent type, such as phosphorus, is doped to replace the silicon atom sites in the crystal lattice, and in N-type semiconductors, free electrons are majority electrons and holes are minority electrons, and conduction is primarily by free electrons. The free electrons are mainly provided by impurity ion atoms; p-type refers to a type of semiconductor material in which impurity ions of a trivalent type, such as boron, are doped to replace silicon atom sites in the lattice, and in P-type semiconductors, holes are majority and free electrons are minority, and conduction is mainly by holes. The holes are mainly provided by impurity ion atoms.

In this embodiment, the technical solution of the present application is described by taking the first conductive type as an N-type and the second conductive type as a P-type as an example.

Fig. 1 is a cross-sectional structure of a CMOS image sensor according to an embodiment of the present application, where the CMOS image sensor includes:

a pixel region including a photodiode, the photodiode being covered with a metal silicide blocking layer, the metal silicide blocking layer including a silicon-rich oxide; and a depletion layer is formed on the surface layer of the source drain region of the photodiode, and the depletion layer is in contact with the metal silicide barrier layer.

The depletion layer formed on the surface layer of the source and drain region of the photodiode can block a current path on the surface layer of the source and drain region, reduce the surface leakage current of the photodiode and avoid the problem of leakage current generated on the surface state of the source and drain region of a device. If the impurity ions forming the depletion layer are implanted excessively, the leakage current is increased and the white pixel is caused. The metal silicide blocking layer including the silicon-rich oxide is capable of capturing an excess of impurity ions due to the excess silicon atoms in the silicon-rich oxide, which form dangling bonds. Optionally, after the metal silicide blocking layer including the silicon-rich oxide is formed, rapid thermal annealing treatment is performed on the metal silicide blocking layer, after the metal silicide blocking layer including the silicon-rich oxide is annealed, the metal silicide blocking layer is more compact, can capture more impurity ions, and alleviates the problem of white pixels caused by excessive impurity ions, and meanwhile, the metal silicide blocking layer can effectively prevent external metal ions from entering the pixel region, and prevent the problem of white pixels caused by metal ions entering the pixel region.

Fig. 2 shows an enlarged schematic structural diagram of the source-drain region of fig. 1, and referring to fig. 2, the source-drain region of the photodiode includes an N-type doped region 1121, a P-type doped region 1122 is formed around the N-type doped region 1121, and the P-type doped region 1122 located on the upper surface of the N-type doped region 1121 is the depletion layer 1123. In this embodiment, the method for manufacturing the source/drain regions 112 includes the following steps:

p-type impurity ions are implanted into the substrate 113 at the source-drain regions 112 to form P-type doped regions 1122. The P-type doped region 1122 extends downward from the upper surface of the substrate 113.

Then, N-type impurity ions are implanted into the P-type doped region 1122 to form an N-type doped region 1121 in the P-type doped region 1122, and the N-type doped region 1121 extends downward from the upper surface of the P-type doped region 1122 so that the P-type doped region 1122 surrounds the bottom surface and the lateral periphery of the N-type doped region 1121.

Finally, P-type impurity ions are implanted into the upper surface of the N-type doped region 1121, and the depletion layer 1123 is formed after the P-type impurity ions neutralize the surface layer of the N-type doped region.

In this embodiment, the thickness of the depletion layer is 200A to 300A.

With continued reference to fig. 1, the CMOS image sensor further includes: the logic region 102, the logic region 102 includes an N-type MOS device 120 and a P-type MOS device 130, and an isolation trench 140 is isolated between the N-type MOS device 120 and the P-type MOS device 130.

The logic region 102 is covered with a metal silicide blocking layer 111, and the metal silicide blocking layer 111 comprises silicon-rich oxide. In this embodiment, the step of forming the metal silicide blocking layer 111 on the logic region 102 includes the following steps:

firstly, a silicon-rich oxide layer is deposited on the surface of the whole CMOS image sensor to be used as a metal silicide barrier layer of the device. So that the metal silicide barrier layer covers the surface of the pixel region and the surface of the logic region. And the metal silicide barrier layer covering the surface of the pixel region is in contact with the depletion layer of the source drain region in the pixel region. In this embodiment, a silicon-rich oxide layer may be deposited on the surface of the CMOS image sensor by a plasma enhanced chemical vapor deposition process using silane and nitrous oxide as reactive sources. The silicon-rich oxide layer has a refractive index of 1.560 to 1.563. After the silicon-rich oxide layer is deposited, the silicon-rich oxide layer needs to be densified by a rapid thermal annealing process.

A metal silicide pattern is then defined on the metal silicide barrier layer by a photosensitive material, such as photoresist. And removing the photosensitive material covered on the metal silicide pattern through a developing process. It is to be explained that the metal silicide pattern is only located in the logic region, where the metal silicide needs to be formed in a subsequent process.

And then, according to the metal silicide pattern, etching and removing the metal silicide barrier layer at the corresponding position in the logic area to expose the device layer.

It can be seen from the foregoing that, the technical solution provided by the present application can alleviate the white pixel problem caused by the excess impurity ions, and at the same time, the metal silicide blocking layer can effectively prevent external metal ions from entering the pixel region, thereby preventing the white pixel problem caused by the metal ions entering the pixel region.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.