阅读说明：本技术 一种微型发光二极管垂直芯片结构、其制备方法及应用 (Vertical chip structure of micro light-emitting diode, preparation method and application thereof ) 是由 毕文刚 王国斌 徐科 于 2020-12-28 设计创作，主要内容包括：本发明公开了一种微型发光二极管(micro-LED)垂直芯片结构、其制备方法及应用。所述垂直芯片结构包括外延结构,所述外延结构包括沿设定方向依次设置的第一半导体层、有源区和第二半导体层；所述第一、第二半导体层分别与第一、第二电极配合,所述第一电极分布于第一半导体层周围且与第一半导体层的侧壁形成电性接触。本发明的micro-LED垂直芯片结构通过采用侧壁电极结构,可以避免因电极设置在出光面上而对LED芯片所发光的吸收,增加器件发光效率,同时还可以起到光反射的作用,从而进一步提高器件的光提取效率和亮度,并且还可以减少各芯片之间的光串扰,避免色坐标偏移,提高显示色纯度,以及,还可以使芯片尺寸得以进一步缩小,提高显示分辨率。(The invention discloses a micro-light emitting diode (micro-LED) vertical chip structure, a preparation method and application thereof. The vertical chip structure comprises an epitaxial structure, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially arranged along a set direction; the first semiconductor layer and the second semiconductor layer are respectively matched with the first electrode and the second electrode, and the first electrodes are distributed around the first semiconductor layer and form electrical contact with the side wall of the first semiconductor layer. The micro-LED vertical chip structure provided by the invention has the advantages that the side wall electrode structure is adopted, the absorption of the light emitted by the LED chip due to the arrangement of the electrode on the light-emitting surface can be avoided, the light-emitting efficiency of the device is increased, the light reflection effect can be realized, the light extraction efficiency and the brightness of the device are further improved, the optical crosstalk among the chips can be reduced, the color coordinate offset is avoided, the display color purity is improved, the size of the chip can be further reduced, and the display resolution is improved.)

1. The utility model provides a vertical chip architecture of miniature emitting diode which characterized in that: the vertical chip structure of the micro light-emitting diode comprises an epitaxial structure, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially arranged along a set direction; the first semiconductor layer and the second semiconductor layer are respectively matched with the first electrode and the second electrode, and the first electrode is distributed around the first semiconductor layer and is electrically contacted with the side wall of the first semiconductor layer.

2. The vertical chip structure of micro led according to claim 1, wherein: either one of the first semiconductor layer and the second semiconductor layer is p-type, and the other is n-type; and/or the first electrode is arranged around the first semiconductor layer to form an optical retaining wall structure; and/or the first electrode forms ohmic contact with the side wall of the first semiconductor layer; and/or a heavily doped region which is continuously arranged in a surrounding mode is formed on the side wall of the first semiconductor layer, and the heavily doped region and the first electrode form ohmic contact.

3. The vertical micro led chip structure according to any one of claims 1-2, wherein: a carrier barrier layer is further arranged between the first semiconductor layer and the active region, and the first electrode is arranged on the carrier barrier layer; and/or the first semiconductor layer and the second semiconductor layer are respectively a p-type layer and an n-type layer, and a conductive substrate is distributed between the second semiconductor layer and the second electrode, or the second electrode is arranged on the second semiconductor layer and forms ohmic contact with the second semiconductor layer.

4. The vertical micro led chip structure according to any one of claims 1-2, wherein: the first semiconductor layer is an n-type layer, and the first electrode is arranged on the active layer; and/or the first semiconductor layer and the second semiconductor layer are an n-type layer and a p-type layer respectively, and the second electrode is arranged on the second semiconductor layer and forms ohmic contact with the second semiconductor layer.

5. The vertical chip structure of micro led according to claim 1, wherein: the active region comprises a multi-quantum well active region; and/or the vertical chip structure of the micro light-emitting diode further comprises a light conversion structure and/or an insulating isolation structure, wherein the light conversion structure is arranged on the first semiconductor layer, and the insulating isolation structure at least surrounds the first semiconductor layer and the active region.

6. The vertical micro led chip structure of claim 5, wherein: the light conversion structure comprises a quantum dot light conversion material layer coated on the first semiconductor layer.

7. The method for preparing a vertical chip structure of a micro light emitting diode according to any one of claims 1 to 6, comprising:

providing an epitaxial structure for manufacturing an LED chip, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially stacked along a set direction;

manufacturing a first electrode and a second electrode which are matched with the epitaxial structure;

wherein the step of fabricating the first electrode comprises:

etching a pattern channel in a selected area of the first semiconductor layer;

and arranging a first metal layer at least in the pattern channel, and forming a first electrode on the side wall of the first semiconductor layer by using the first metal layer.

8. The method of claim 7, wherein the step of fabricating the first electrode further comprises:

arranging a mask corresponding to the pattern channel on the first semiconductor layer, exposing a selected region of the first semiconductor layer from the mask, carrying out heavy doping treatment on the selected region, etching the pattern channel in the selected region, and arranging the pattern channel around the remaining heavy doping region;

and/or, the first electrode is manufactured and formed by adopting a metal stripping process;

and/or after the first electrode is formed, thinning the first semiconductor layer until the top height of the first semiconductor layer is lower than that of the first electrode, so that the first electrode is formed into an optical retaining wall structure surrounding the first semiconductor layer.

9. The method of claim 7, further comprising:

etching the first semiconductor layer and the active region at the pattern channel until the groove bottom of the formed etching groove reaches or enters the second semiconductor layer, thereby forming an insulating isolation structure;

and/or, a light conversion structure is arranged on the first semiconductor layer;

and/or the second semiconductor layer is grown on the substrate, and the step of manufacturing the second electrode comprises the following steps:

separating the substrate from the second semiconductor layer, and then manufacturing a second electrode on the second semiconductor layer;

or, a second electrode is manufactured on the substrate, the substrate is a conductive substrate, and the conductivity type of the substrate is the same as that of the second semiconductor layer.

10. The method of claim 9, further comprising: and filling an insulating medium in the etching groove so as to form the insulating isolation structure.

11. A light emitting assembly, comprising: the light emitting assembly comprises a plurality of light emitting units, wherein at least one light emitting unit has the vertical chip structure of the micro light emitting diode of any one of claims 1 to 6; preferably, the radial dimension of the light emitting unit is 5 μm or less.

Technical Field

The invention relates to an LED chip, in particular to a micro-LED vertical chip structure, a preparation method and application thereof.

Background

With the development requirements of applications such as ultra-high definition small-spacing large-screen commercial display and the like and the rise of novel display applications such as AR (Augmented Reality), VR (Virtual Reality), MR (mixed Reality technology) and the like, challenges are provided for the size reduction of LED light sources. Especially, in order to improve the display resolution, the size of the LED chip is usually required to be smaller than several tens of micrometers, even 1 to 5 μm. In addition, the development of visible light communication also requires that the LED chip size be advanced to micro size. However, since the LED chip requires two electrodes, positive and negative, for its operation, the vertical structure is an ideal choice for preparing such a chip with a small size due to the limitation of the size of the electrodes. However, the electrodes on the light emitting surface of the LED in the vertical structure seriously affect the light emitting efficiency of the LED, resulting in the loss of the brightness of the LED. Although the light-emitting surface of the LED flip-chip structure has no brightness loss caused by the electrodes, the structure needs to prepare a positive electrode and a negative electrode on the same surface/side of the LED, so that the size of an LED chip is limited, and the LED with the size less than 5 μm is difficult to realize.

Disclosure of Invention

The invention aims to provide a vertical chip structure of a micro light-emitting diode, a preparation method and application thereof, so as to overcome the defects in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

some embodiments of the present invention provide a vertical chip structure of a micro light emitting diode, which includes an epitaxial structure including a first semiconductor layer, an active region, and a second semiconductor layer sequentially arranged along a set direction; the first semiconductor layer and the second semiconductor layer are respectively matched with the first electrode and the second electrode, and the first electrode is distributed around the first semiconductor layer and is electrically contacted with the side wall of the first semiconductor layer.

In some embodiments, the first electrode is disposed around the first semiconductor layer to form an optical barrier structure.

In some embodiments, a heavily doped region is formed at a sidewall of the first semiconductor layer to continuously surround the first semiconductor layer, and the heavily doped region forms an ohmic contact with the first electrode.

Some embodiments of the present invention also provide a method of manufacturing the micro light emitting diode vertical chip structure, which includes:

providing an epitaxial structure for manufacturing an LED chip, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially stacked along a set direction;

manufacturing a first electrode and a second electrode which are matched with the epitaxial structure;

further, the step of fabricating the first electrode comprises:

etching a pattern channel in a selected area of the first semiconductor layer;

and arranging a first metal layer at least in the pattern channel, and forming a first electrode on the side wall of the first semiconductor layer by using the first metal layer.

In some embodiments, the step of fabricating the first electrode further comprises: and arranging a mask corresponding to the pattern channel on the first semiconductor layer, exposing a selected region of the first semiconductor layer from the mask, carrying out heavy doping treatment on the selected region, etching the pattern channel in the selected region, and arranging the pattern channel around the remaining heavy doping region.

In some embodiments, the step of fabricating the first electrode further comprises: after the first electrode is formed, thinning the first semiconductor layer again until the top height of the first semiconductor layer is lower than that of the first electrode, so that the first electrode is formed into an optical retaining wall structure surrounding the first semiconductor layer.

Some embodiments of the invention also provide application of the micro light-emitting diode vertical chip structure in preparation of products such as optical components.

Compared with the prior art, in the vertical chip structure of the micro light-emitting diode provided by the embodiment of the invention, by adopting the side wall electrode structure of the chip, the absorption of light emitted by the micro-LED chip due to the electrode arranged on the light-emitting surface can be avoided, the light-emitting efficiency of the micro-LED chip is increased, and the light reflection effect can be realized, so that the light extraction efficiency and the brightness of the micro light-emitting diode are further improved, the optical crosstalk among the micro-LED chips can be reduced, the color coordinate offset is avoided, the display color purity is improved, the size of the micro-LED chip can be further reduced, the integration level of the micro light-emitting diode device can be further improved, and the display resolution is improved. Meanwhile, the wafer-level array chip can be realized, the huge transfer is avoided, the process is simplified, and the cost is saved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a vertical chip structure of a micro light emitting diode in embodiment 1 of the present invention;

fig. 2a is a schematic view of an epitaxial structure of an LED chip in embodiment 1 of the present invention;

FIG. 2b is a schematic illustration of a mask disposed on the epitaxial structure shown in FIG. 2 a;

FIG. 2c is a schematic illustration of the mask of FIG. 2b being patterned;

fig. 2d is a schematic view of a p-type heavily doped region formed in the first semiconductor layer in fig. 2 c;

FIG. 2e is a schematic diagram of the formation of a patterned trench in the first semiconductor layer of FIG. 2 d;

figure 2f is a schematic illustration of a photoresist planarizing the surface of the device of figure 2 e;

FIG. 2g is a schematic illustration of the device of FIG. 2f after a photolithographic process has been performed to deposit a metal layer on its surface;

FIG. 2h is a schematic illustration of a metal strip to form a first electrode for the device of FIG. 2 g;

FIG. 2i is a schematic illustration of the formation of an insulating isolation structure in the device of FIG. 2 h;

FIG. 2j is a schematic illustration of the formation of a second electrode on the substrate in the device of FIG. 2 i;

fig. 3 is a schematic diagram of a vertical chip structure of a micro light emitting diode in embodiment 2 of the present invention;

fig. 4 is a schematic diagram of a vertical chip structure of a micro light emitting diode in embodiment 3 of the present invention;

fig. 5 is a schematic view of a vertical chip structure of a micro light emitting diode in embodiment 4 of the present invention;

fig. 6 is a schematic diagram of a vertical chip structure of a micro light emitting diode in embodiment 5 of the present invention;

fig. 7a is a schematic view of an epitaxial structure of an LED chip in embodiment 5 of the present invention;

FIG. 7b is a schematic diagram of a metal layer for making a second electrode being vapor deposited on the epitaxial structure shown in FIG. 7 a;

FIG. 7c is a schematic illustration of a mask being provided on the first semiconductor layer of the device shown in FIG. 7 b;

FIG. 7d is a schematic illustration of the mask of FIG. 7c being patterned;

fig. 7e is a schematic diagram of forming an n-type heavily doped region in the first semiconductor layer in fig. 7 d;

FIG. 7f is a schematic illustration of the formation of a patterned trench in the first semiconductor layer of FIG. 7 e;

FIG. 7g is a schematic illustration of a photoresist planarizing the surface of the device of FIG. 7 f;

FIG. 7h is a schematic diagram of the device of FIG. 7g after a photolithography process and a metal layer deposited on the surface thereof for forming a first electrode;

FIG. 7i is a schematic illustration of a metal strip forming a first electrode for the device of FIG. 7 h;

fig. 7j is a schematic illustration of the formation of an insulating isolation structure in the device of fig. 7 i;

FIG. 7k is a schematic illustration of the formation of a second electrode on the substrate in the device of FIG. 7 j;

fig. 8 is a schematic view of a vertical chip structure of a micro light emitting diode in embodiment 6 of the present invention;

fig. 9 is a schematic view of a vertical chip structure of a micro light emitting diode in embodiment 7 of the present invention.

Detailed Description

As mentioned above, due to the shortcomings of the prior art, it has been difficult for the industry to overcome the following micro-LED technology bottlenecks: the vertical structure has brightness loss caused by light absorption of the electrodes, and the brightness of the LED light source needs to be greatly improved; the light crosstalk among different pixel points seriously affects the displayed color coordinate and color purity; and, the micro-LED of the flip-chip structure cannot further improve the display resolution due to the chip size limitation.

Accordingly, the present inventors have made extensive studies and practice to propose the technical solution of the present invention, as will be explained in detail below.

One aspect of the embodiment of the invention provides a vertical chip structure of a micro light-emitting diode, which comprises an epitaxial structure, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially arranged along a set direction; the first semiconductor layer and the second semiconductor layer are respectively matched with the first electrode and the second electrode, and the first electrode is distributed around the first semiconductor layer and is electrically contacted with the side wall of the first semiconductor layer.

Furthermore, the surface of one side of the first semiconductor layer, which is far away from the active region, is set as a light-emitting surface of the micro light-emitting diode vertical chip structure.

The first electrode is arranged on the side wall of the first semiconductor layer, so that the first electrode can form good electrical contact with the first semiconductor layer, the first electrode can also prevent the first electrode from occupying a light-emitting surface, the first electrode is prevented from absorbing and blocking light emitted by the LED, and the light-emitting efficiency of the device is improved.

Wherein the predetermined direction may be a thickness direction of the epitaxial structure.

In some embodiments, the first electrode is disposed around the first semiconductor layer to form an optical barrier structure. Therefore, the lateral light emitting and reflecting of the LED can be realized, the light extraction efficiency of the micro light emitting diode is further improved, and the light crosstalk among the LED chips can be reduced.

Preferably, the inner annular surface of the optical retaining wall structure is a mirror surface structure.

In some embodiments, the first electrode forms an ohmic contact with a sidewall of the first semiconductor layer.

Furthermore, a heavily doped region which is continuously arranged in a surrounding mode is formed on the side wall of the first semiconductor layer, and the heavily doped region and the first electrode form ohmic contact.

Wherein the heavily doped region has a conductive characteristic consistent with that of the first semiconductor layer, i.e., can be p-type or n-type.

Wherein, the radial cross-sectional shape of the heavily doped region may be circular, rectangular or other regular or irregular shapes, and is not limited thereto.

In some embodiments, the micro light emitting diode vertical chip structure further comprises a light conversion structure disposed on the first semiconductor layer.

Further, the light conversion structure comprises a quantum dot light conversion material layer coated on the first semiconductor layer.

Of course, the light conversion structure may also adopt other light conversion structures known in the art, such as a thin film formed by fluorescent powder, fluorescent nanoparticles, and the like, an encapsulating adhesive layer, and the like, but is not limited thereto.

In addition, the light conversion structure may directly cover the surface of the first semiconductor layer, or a remote light conversion (such as quantum dot or phosphor) block or film may be used, without being limited thereto. The advantage is that RGB full-color display can be realized, and huge chip transfer is not needed, thereby effectively saving cost.

Further, the first semiconductor layer and the second semiconductor layer have different conductivity types. For example, one of the first semiconductor layer and the second semiconductor layer is p-type, and the other is n-type.

In some embodiments, a carrier blocking layer (e.g., an electron or hole blocking layer) is further disposed between the first semiconductor layer and the active region, and the first electrode is disposed on the carrier blocking layer.

In some embodiments, the first semiconductor layer is a p-type layer, and an Electron Blocking Layer (EBL) is further disposed between the first semiconductor layer and the active region, and the first electrode is disposed on the electron blocking layer. Further, the electron blocking layer is also p-type. Or, the first semiconductor layer is an n-type layer, a hole blocking layer is further arranged between the first semiconductor layer and the active region, and the first electrode is arranged on the hole blocking layer. Accordingly, the hole blocking layer is also n-type.

In some embodiments, the first semiconductor layer and the second semiconductor layer are a p-type layer and an n-type layer, respectively, and a conductive substrate is distributed between the second semiconductor layer and the second electrode, or the second electrode is disposed on the second semiconductor layer and forms ohmic contact with the second semiconductor layer. Further, the conductive substrate has the same conductivity type as the second semiconductor.

In some embodiments, the first semiconductor layer is an n-type layer and the first electrode is disposed on the active layer. Further, the first electrode is disposed around the first semiconductor layer.

Further, the first semiconductor layer and the second semiconductor layer are respectively an n-type layer and a p-type layer, and the second electrode is arranged on the second semiconductor layer and forms ohmic contact with the second semiconductor layer.

In some embodiments, the active region comprises a multiple quantum well active region.

In some embodiments, the vertical micro led chip structure further comprises an insulating isolation structure disposed at least around the first semiconductor layer and the active region.

Further, the insulating isolation structure may be formed of various insulating dielectric materials such as silicon dioxide, aluminum oxide, and silicon nitride, and may also be formed of air, without being limited thereto.

Preferably, the insulating isolation structure may be formed by using an opaque insulating material.

In the above embodiments of the present invention, the material of the epitaxial structure may be selected from III-V semiconductor materials or other semiconductor materials known in the art. For example, GaN, AlN, InN, AlGaN, InGaN, GaAs, AlGaAs, AlGaInP, InP, GaP, InGaAsP, etc. may be selected, but not limited thereto. Also, the epitaxial structure may be grown using an epitaxial growth technique such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), and the like, which are known in the art.

Further, the epitaxial structure may further include a nucleation layer, a buffer layer, and other structural layers known in the art.

In the above embodiments of the present invention, the first electrode and the second electrode may be formed by using various materials with good conductivity known in the art, such as ITO, Au, Ti, Al, Ag, Cu, Ni, Cr, etc., or alloys thereof, but not limited thereto. The first and second electrodes may be formed by metal sputtering (Sputter), Plasma Enhanced Chemical Vapor Deposition (PECVD), electron beam evaporation (e-beam), and the like, which are known in the art, but not limited thereto.

Another aspect of the embodiments of the present invention also provides an optical assembly including a plurality of light emitting units, wherein at least one of the light emitting units has the micro light emitting diode vertical chip structure.

In some embodiments, the radial dimension of the light emitting cells is below 5 μm. Of course, the radial dimension of the light emitting unit may also be larger than 5 μm, e.g. adjusted to tens of microns or even hundreds of microns. But it is preferably controlled to 5 μm or less.

In some embodiments, the plurality of light emitting units each have the micro light emitting diode vertical chip structure.

In some embodiments, the plurality of light emitting cells are arranged integrally, e.g. in an array.

Furthermore, the plurality of light-emitting units are formed on the same epitaxial wafer through etching processing, so that the optical assembly is a wafer-level device.

In some embodiments, the plurality of light-emitting units are discrete from one another.

Further, the optical module may be various optical modules applied to a display device or an optical communication device, and is not limited thereto.

Another aspect of the embodiments of the present invention also provides a method for manufacturing the vertical chip structure of the micro light emitting diode, including:

providing an epitaxial structure for manufacturing an LED chip, wherein the epitaxial structure comprises a first semiconductor layer, an active region and a second semiconductor layer which are sequentially stacked along a set direction; and

manufacturing a first electrode and a second electrode which are matched with the epitaxial structure;

further, the step of fabricating the first electrode comprises:

etching a pattern channel in a selected area of the first semiconductor layer;

and arranging a first metal layer at least in the pattern channel, and forming a first electrode on the side wall of the first semiconductor layer by using the first metal layer.

In some embodiments, the step of fabricating the first electrode comprises: and arranging a mask corresponding to the pattern channel on the first semiconductor layer, exposing a selected region of the first semiconductor layer from the mask, carrying out heavy doping treatment on the selected region, etching the pattern channel in the selected region, and arranging the pattern channel around the remaining heavy doping region.

The heavily doping process for the selected region may be selected from ion implantation, plasma treatment, thermal diffusion, and the like, which are known in the art, and is not limited thereto.

The heavy doping treatment can be a p-type or n-type heavy doping treatment according to the conductivity type of the first semiconductor layer. By arranging the pattern channel around the remaining heavily doped region, when the first electrode is manufactured in the pattern channel, the first electrode can form better ohmic contact with the first semiconductor layer by using the heavily doped region.

In some embodiments, the step of fabricating the first electrode further comprises: the first electrode is formed by a metal lift-off technology (metal lift-off technology) in a manner known in the art.

For example, a first electrode can be formed on the first semiconductor layer by applying a photoresist/photoresist, exposing and developing the photoresist/photoresist, forming a photoresist film having a desired pattern on the first semiconductor layer (only a region corresponding to the first electrode is exposed), depositing a desired metal with a photoresist using the photoresist film as a mask, and removing the mask and simultaneously stripping the metal on the photoresist film.

Or, a metal layer may be deposited at the pattern channel by a metal lift-off process, and then the metal layer distributed at the region corresponding to the insulating isolation structure is etched and removed during the process of manufacturing the insulating isolation structure, thereby forming the first electrode.

In some embodiments, the method of making further comprises: and etching the first semiconductor layer and the active region at the pattern channel until the groove bottom of the formed etching groove reaches or enters the second semiconductor layer, thereby forming the insulating isolation structure.

Furthermore, when the area corresponding to the etched groove on the first semiconductor layer is directly exposed, the first semiconductor layer can be directly etched, so that the etched groove is formed. And when the area of the first semiconductor layer corresponding to the etched groove is covered with the metal layer for forming the first electrode, the metal layer and the first semiconductor layer can be etched in sequence in the area, so that the etched groove is formed.

Further, according to a manner known in the art, the etching trench may be filled with an insulating medium such as silicon dioxide, silicon nitride, aluminum oxide, and the like by using a photolithography process and Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof, so as to form the insulating isolation structure.

Furthermore, if the insulating isolation structure is formed by using an opaque insulating material, optical crosstalk between the LED chips can be better avoided.

In some embodiments, the method of making further comprises: after the first electrode is formed, thinning the first semiconductor layer until the top height of the first semiconductor layer is lower than that of the first electrode, so that the first electrode is formed into an optical retaining wall structure surrounding the first semiconductor layer.

Further, the first semiconductor layer may be thinned by a method known in the art, such as photolithography and dry or wet etching, without being limited thereto.

In some embodiments, the method of making further comprises: and arranging a light conversion structure on the first semiconductor layer. The material and the arrangement of the light conversion structure are as described above.

In some embodiments, the second semiconductor layer is grown on a substrate, and the step of forming the second electrode includes:

separating the substrate from the second semiconductor layer, and then manufacturing a second electrode on the second semiconductor layer;

alternatively, a second electrode is fabricated on the substrate.

Further, if the substrate is an insulating substrate or an opaque substrate, the substrate may be separated from the second semiconductor layer, and then the second electrode is formed on the second semiconductor layer.

Further, if the substrate is a light-transmitting conductive substrate, the substrate may be thinned, and then the second electrode is formed on the substrate.

Further, the second electrode may be in full-face contact with the substrate or the second semiconductor layer to improve uniformity of current injection.

The substrate may be a sapphire substrate, a Si substrate, a GaN substrate, a SiC substrate, an AlN substrate, a gallium oxide substrate, a GaAs substrate, a GaP substrate, an InP substrate, etc. known in the art, but is not limited thereto.

The method for manufacturing the vertical chip structure of the micro light-emitting diode provided by the embodiment of the invention is compatible with the existing semiconductor device manufacturing process, can realize the wafer-level micro light-emitting diode array chip, and has the advantages of simpler and more efficient manufacturing process, lower cost and higher yield compared with the existing micro light-emitting diode, thereby having better application prospect.

The technical solutions in the embodiments of the present invention will be described in detail below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. It should be noted that, in the following examples, unless otherwise specified, various reagents and various processing and testing equipment used are known in the art and commercially available, and various processing methods used therein, such as photolithography, dry or wet etching, metal stripping processes, physical or chemical deposition processes, etc., may be implemented according to the methods known in the art.

Example 1: referring to fig. 1, the vertical chip structure of a micro light emitting diode according to the present embodiment includes an epitaxial structure formed on an n-type conductive substrate 107 (e.g., GaN, etc.), wherein the epitaxial structure includes a second semiconductor layer 105 (e.g., GaN) and an active region 103 (e.g., In) sequentially grown from bottom to top_xGa_1-xN/GaN multiple quantum well, 0<x<1) Electron blocking layer 102 (e.g., Al)_xGa_1-xN，0<x<1) And a first semiconductor layer 101 (e.g., GaN). The first semiconductor layer 101 and the electron blocking layer 102 are both p-type (e.g., doped with Mg) and the second semiconductor layer 105 is n-type (e.g., doped with Si)The active region 103 employs a multiple quantum well active region (MQW). Wherein a third semiconductor layer 104 (e.g. Al) is disposed between the electron blocking layer 102 and the active region 103_yGa_1-yN, 0 ≦ y ≦ 1), the third semiconductor layer 104 is also p-type and may be formed by one epitaxial growth with the first semiconductor layer 101 and the electron blocking layer 102. Of course, the third semiconductor layer 104 may be omitted. The first semiconductor layer 101 and the second semiconductor layer 105 are respectively matched with a first electrode 106 (for example, Ti/Al/Ni/Au is adopted) and a second electrode 110 (for example, Ti/Al/Ni/Au or/Al/Ni/Au is adopted), the first electrode is arranged around the first semiconductor layer in a surrounding mode, a p-type heavily doped region 108 is formed at the side wall of the first semiconductor layer, and the p-type heavily doped region and the first electrode form ohmic contact. The radial cross section of the first electrode and the p-type heavily doped region can be circular, rectangular or other shapes. A conductive substrate 107 may be disposed between the second electrode 110 and the second semiconductor layer 105. Wherein at least the first electrode is a metal electrode (for example, Ti/Al/Ni/Au is adopted). Further, an insulating isolation structure 109 is further arranged around the first semiconductor layer to the active region, the insulating isolation structure includes an isolation groove arranged around the first semiconductor layer to the active region, a groove bottom of the isolation groove reaches or enters the second semiconductor layer, and insulating media such as silicon oxide can be filled in the isolation groove. By utilizing the insulating isolation structure, the micro light-emitting diode vertical chip structure can be electrically isolated from other micro light-emitting diode vertical chip structures, and meanwhile, the effect of optical isolation between chips can also be achieved to a certain extent. The second electrode 110 may also be a patterned discrete electrode.

When the vertical chip structure of the micro light-emitting diode is used, light generated by the active layer can be emitted from the first semiconductor layer (as shown by arrows in the figure), and the first electrode is arranged around the first semiconductor layer, so that the light-emitting surface is not occupied, the light-emitting efficiency and the brightness of the vertical chip structure of the micro light-emitting diode are increased, the lateral propagation of the light can be blocked to a certain extent, and the optical crosstalk among the vertical chip structures of the micro light-emitting diode is reduced.

A method for manufacturing the vertical chip structure of the micro light-emitting diode comprises the following steps:

s1, sequentially epitaxially growing a second semiconductor layer 105, an active region 103, a third semiconductor layer 104, an electron blocking layer 102, a first semiconductor layer 101, and the like on the conductive substrate 107, and obtaining an LED chip epitaxial structure, as shown in fig. 2 a;

s2, as shown in FIG. 2b, a mask 111 (e.g., SiO silicon oxide) is disposed on the first semiconductor layer₂Etc., without limitation) and a desired pattern is formed in the mask using photolithography, dry or wet etching processes, etc., to expose selected regions 114 of the first semiconductor layer, as shown in fig. 2 c;

s3, as shown in fig. 2d, performing p-type heavy doping on the selected region of the first semiconductor layer by using an ion implantation method to form a p-type heavy doped region 108, so as to facilitate ohmic contact between the first electrode and the sidewall of the first semiconductor layer in the subsequent process;

s4, as shown in fig. 2e, continuing to etch the selected region of the first semiconductor layer by using photolithography, dry or wet etching, etc. to form the required pattern channel 113, but leaving a part of the p-type heavily doped region 108 in the region surrounded by the pattern channel;

s5, forming a first electrode 106 on the sidewall of the first semiconductor layer by using a metal lift-off process, specifically, as shown in fig. 2f, coating a photoresist 112 on the first semiconductor layer, planarizing, performing a patterned exposure and development on a selected area to expose the patterned trench 113, and then evaporating a metal layer 106' (as shown in fig. 2 g) on the first semiconductor layer and other areas on the chip surface to form the first electrode by lift-off (as shown in fig. 2 h);

s6, continuing to process the epitaxial structure by photolithography, dry etching, etc., so as to form an insulating isolation structure 109 (as shown in fig. 2 i) between the vertical chip structures of the micro light emitting diodes, which plays a role in isolating and passivating the side walls of the chips. The insulating dielectric material adopted in the insulating isolation structure can be silicon nitride or SiO₂And the like, and can be fabricated by ALD, PECVD, and the like, without being limited thereto;

s7, the conductive substrate 107 is thinned, and then the second electrode 110 is formed on the conductive substrate by evaporation, sputtering, or the like, as shown in fig. 2 j. Further, the second electrode 110 can be further processed into a patterned discrete electrode. Alternatively, the second electrode 110 having a patterned discrete structure may be directly formed on the conductive substrate by evaporation or sputtering.

In this embodiment, each micro light emitting diode vertical chip structure may be separated by mechanical or laser scribing, so as to form a discrete light emitting unit.

Example 2: the vertical chip structure of a micro light emitting diode provided by this embodiment is basically the same as that of embodiment 1, except that: referring to fig. 3, the top height of the first electrode 106 'is higher than the top height of the first semiconductor layer 101', so as to form an optical barrier structure surrounding the first semiconductor layer. Preferably, the inner annular surface of the optical retaining wall structure may be configured as a mirror surface structure. Therefore, the problem that the first electrode occupies the effective light emitting surface on the front surface of the micro light emitting diode can be avoided, the first electrode can be utilized to play a role in light reflection, the light extraction efficiency and the brightness of the vertical chip structure of the micro light emitting diode are further improved, forward light emission is increased, and meanwhile, the light crosstalk between the vertical chip structures of the micro light emitting diode is better reduced and even eliminated.

The manufacturing process of the vertical chip structure of the micro light emitting diode in this embodiment is also substantially the same as that in embodiment 1, except that the method further includes:

s8, continuing to process the first semiconductor layer by photolithography, dry etching or wet etching, and so on, to thin the first semiconductor layer (i.e. reduce the height of the top end of the first semiconductor layer), until the top end of the first electrode and the top end of the first semiconductor layer form a certain height difference, so that the first electrode forms the optical retaining wall structure.

Example 3: the vertical chip structure of the micro light emitting diode provided by the embodiment is basically the same as that of the embodiment 2, and is a deep ultraviolet chip, and the difference is that: referring to fig. 4, a quantum dot light conversion material layer 115 is further disposed on the first semiconductor layer. In particular, red, green and blue quantum dot light conversion material layers can be coated on the first semiconductor layer of the adjacent micro light emitting diode vertical chip structure at intervals, so that full-color display can be realized. The advantages of this embodiment are at least: compared with the red, green and blue micro light-emitting diode full-color display technology, the technology is simplified, and the cost can be saved.

Correspondingly, the manufacturing process of the vertical chip structure of the micro light emitting diode in this embodiment is also substantially the same as that of embodiment 2, except that the method further includes:

and S9, coating a red, green or blue quantum dot light conversion material layer on the first semiconductor layer by means of photoetching or ink-jet printing, spin coating and the like.

Example 4: the vertical chip structure of a micro light emitting diode provided by this embodiment is basically the same as that of embodiment 1, except that: referring to fig. 5, the second electrode 110 is directly formed on the second semiconductor layer 105.

Correspondingly, the manufacturing process of the vertical chip structure of the micro light emitting diode in this embodiment is also substantially the same as that in embodiment 1, except that:

a light absorbing substrate (e.g., Si) is used in step S1;

in step S7, the substrate and the second semiconductor layer are peeled off by a method known in the art, and then a second electrode is formed on the second semiconductor layer 105 by e-beam evaporation (e-beam), PECVD, magnetron sputtering (Sputter), or the like.

Further, the preparation process of this embodiment may further include the operations of steps S8 and S9 in embodiments 2 and 3.

Example 5: referring to fig. 6, the vertical chip structure of a micro light emitting diode provided in the present embodiment includes an epitaxial structure, and the epitaxial structure includes a first semiconductor layer 205, an active region 203, a third semiconductor layer 204, an electron blocking layer 202, and a second semiconductor layer 201, which are sequentially grown from bottom to top. The second semiconductor layer 201, the third semiconductor layer 204 and the electron blocking layer 202 are all p-type, the first semiconductor layer 205 is n-type, and the active region 203 is a multi-quantum well active region (MQW). The second semiconductor layer 201 and the first semiconductor layer 205 are respectively matched with the second electrode 206 and the first electrode 210, the first electrode is arranged around the first semiconductor layer in a surrounding mode, an n-type heavily doped region 208 is formed on the side wall of the first semiconductor layer, and the n-type heavily doped region and the first electrode form ohmic contact. The radial cross section of the first electrode and the n-type heavily doped region can be circular, rectangular or other shapes. The first electrode and the second electrode can both adopt metal electrodes. Further, an insulating isolation structure 209 is further arranged around the first semiconductor layer to the active region, the insulating isolation structure includes an isolation groove arranged around the first semiconductor layer to the active region, a groove bottom of the isolation groove reaches or enters the second semiconductor layer, and insulating media such as silicon dioxide can be filled in the isolation groove.

When the vertical chip structure of the micro light-emitting diode is used, light generated by the active layer can be emitted from the first semiconductor layer (as shown by arrows in the figure), and the first electrode is arranged around the first semiconductor layer, so that the light-emitting surface is not occupied, the light-emitting efficiency and the brightness of the vertical chip structure of the micro light-emitting diode are increased, the lateral propagation of the light can be blocked to a certain extent, and the optical crosstalk among the vertical chip structures of the micro light-emitting diode is reduced.

A method for manufacturing the vertical chip structure of the micro light-emitting diode comprises the following steps:

s1, sequentially epitaxially growing a first semiconductor layer 205, an active region 203, a third semiconductor layer 204, an electron blocking layer 202, a second semiconductor layer 201, and the like on a substrate 207, to obtain an LED chip epitaxial structure, as shown in fig. 7 a;

s2, forming a metal layer 206' for forming the second electrode 206 on the substrate 207 by electron beam evaporation (e-beam), PECVD, magnetron sputtering, etc. in a manner known in the art, as shown in fig. 7 b;

s3, flipping the epitaxial structure, peeling the substrate 207 and the first semiconductor layer 205 by a method known in the art, and then removing the first semiconductor layerA mask 211 (e.g., silicon dioxide SiO) is disposed on the first semiconductor layer₂Etc., without limitation, as shown in fig. 7 c), and forming a desired pattern in the mask using photolithography, etching processes, etc., to expose selected regions 214 of the first semiconductor layer, as shown in fig. 7 d;

s4, heavily doping the selected region 214 of the first semiconductor layer with n-type by ion implantation, etc. to form a heavily doped region 208 of n-type, as shown in fig. 7e, so as to facilitate ohmic contact between the first electrode and the sidewall of the first semiconductor layer in the subsequent process;

s5, continuing to etch the S-selected region of the first semiconductor layer by using photolithography, dry or wet etching, etc. to form the required pattern channel 213, but leaving a portion of the n-type heavily doped region 208 in the region surrounded by the pattern channel, as shown in fig. 7 f;

s6, forming a first electrode 210 on the sidewall of the first semiconductor layer by using a metal lift-off process, specifically, coating a photoresist 212 on the first semiconductor layer, planarizing, as shown in fig. 7g, performing a patterned exposure and development on the selected area to expose the patterned trench 213, and then evaporating a metal 210' on the first semiconductor layer and other areas of the chip surface, as shown in fig. 7h, to lift off and form a first electrode, as shown in fig. 7 i;

s7, processing the epitaxial structure by photolithography and etching, so as to form insulating isolation structures 209 between the vertical chip structures of the micro leds, which serve to isolate and passivate the sidewalls of the chips, as shown in fig. 7 j. The insulating medium material adopted in the insulating isolation structure can be SiO₂And the like, and can be fabricated by ALD, PECVD, and the like, without being limited thereto;

s8, patterning the metal layer 206' by photolithography and etching to form the second electrode 206, as shown in fig. 7 k. Preferably, the second electrode 206 has a light reflecting characteristic.

In this embodiment, each micro light emitting diode vertical chip structure may be separated by mechanical or laser scribing, so as to form a discrete light emitting unit.

Example 6: the vertical chip structure of a micro light emitting diode provided by this embodiment is substantially the same as that of embodiment 5, except that: referring to fig. 8, the top height of the first electrode 210 'is higher than the top height of the first semiconductor layer 205', so as to form an optical barrier structure surrounding the first semiconductor layer. Preferably, the inner annular surface of the optical retaining wall structure may be configured as a mirror surface structure. Therefore, the problem of light efficiency loss caused by the fact that the first electrode occupies the effective light emitting surface on the front surface of the miniature light emitting diode can be avoided, the first electrode can be utilized to play a role in light reflection, the light extraction efficiency and the brightness of the miniature light emitting diode vertical chip structure are further improved, forward light emitting is increased, and meanwhile light crosstalk between the miniature light emitting diode vertical chip structures is better reduced and even eliminated. When the method is applied to display, color coordinate deviation can be avoided, and display color purity is improved.

The manufacturing process of the vertical chip structure of the micro light emitting diode in this embodiment is also substantially the same as that in embodiment 5, except that the method further includes:

s9, processing the first semiconductor layer by photolithography, dry etching or wet etching, etc., to thin the first semiconductor layer (i.e., reduce the height of the top end of the first semiconductor layer), until the top end of the first electrode and the top end of the first semiconductor layer form a certain height difference, so that the first electrode forms the optical retaining wall structure.

Example 7: the vertical chip structure of a micro light emitting diode provided by this embodiment is substantially the same as that of embodiment 6, and is a deep ultraviolet chip, and the difference is that: referring to fig. 9, a quantum dot light conversion material layer 215 is further disposed on the first semiconductor layer. In particular, red, green and blue quantum dot light conversion material layers can be coated on the first semiconductor layer of the adjacent micro light emitting diode vertical chip structure at intervals, so that full-color display can be realized. The advantages of this embodiment are at least: and a huge amount of chips are not required to be transferred, and compared with a red, green and blue three-color micro light-emitting diode full-color display technology, the cost can be saved.

Correspondingly, the manufacturing process of the vertical chip structure of the micro light emitting diode in this embodiment is also substantially the same as that of embodiment 2, except that the method further includes:

and S10, coating a red, green or blue quantum dot light conversion material layer on the first semiconductor layer by means of photoetching or ink-jet printing, spin coating and the like.

The vertical chip structure of the micro light emitting diode provided in the above embodiments 1 to 7 can also be used as a light emitting unit to be assembled with a corresponding driving module to form an optical module, and the optical module can be applied to a display device, an optical communication device, and the like, but is not limited thereto. The driving module may be selected from various types of driving modules known in the art, such as a CMOS driving module, etc., without being limited thereto.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only the aforementioned elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing is directed to embodiments of the present invention, and it is understood that various modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention.