阅读说明：本技术 SiC晶片和SiC晶片的制造方法 (SiC wafer and method for producing SiC wafer ) 是由 长屋正武 神田贵裕 冈本武志 鸟见聪 野上晓 北畠真 于 2019-07-24 设计创作，主要内容包括：本发明解决的问题是提供可以提高光学式传感器的检测率的SiC晶片和SiC晶片的制造方法。其特征在于,包括：梨皮面加工步骤(S141),对SiC晶片(20)的至少背面(22)进行梨皮面加工；蚀刻步骤(S21),在所述梨皮面加工步骤(S141)之后,通过在Si蒸汽压下进行加热来对所述SiC晶片(20)的至少背面(22)进行蚀刻；以及镜面加工步骤(S31),在所述蚀刻步骤(S21)之后,对所述SiC晶片(20)的主面(21)进行镜面加工。由此,可以获得具有已镜面加工的主面(21)和已梨皮面加工的背面(22)的SiC晶片。(The present invention addresses the problem of providing a SiC wafer and a method for producing a SiC wafer, which can improve the detection rate of an optical sensor. It is characterized by comprising: a rind surface processing step (S141) for performing rind surface processing on at least the back surface (22) of the SiC wafer (20); an etching step (S21) of etching at least the back surface (22) of the SiC wafer (20) by heating under Si vapor pressure after the pearskin surface processing step (S141); and a mirror finishing step (S31) of mirror finishing the main surface (21) of the SiC wafer (20) after the etching step (S21). Thus, a SiC wafer having a mirror-finished main surface (21) and a rind-finished back surface (22) can be obtained.)

1. A SiC wafer characterized by comprising:

a mirror-finished main surface; and

the back processed by the pear peel surface.

2. The SiC wafer according to claim 1, wherein an arithmetic mean deviation Ra of the back surface is 50nm to 300 nm.

3. The SiC wafer of claim 1 or 2, wherein the maximum height Rz of the back surface is 0.5 μm to 5 μm.

4. The SiC wafer of any one of claims 1 to 3, characterized in that there is substantially no process-altered layer at the back side.

5. A SiC wafer characterized in that at least the back surface of the SiC wafer is subjected to pearskin surface processing and then heated under Si vapor pressure to be etched.

6. A SiC wafer characterized in that at least the back surface of the SiC wafer is subjected to pearskin surface processing and heated under Si vapor pressure to be etched, and the main surface of the SiC wafer is mirror-finished.

7. A SiC wafer according to claim 5 or claim 6, wherein the pearskin face machining is free abrasive machining using boron carbide abrasive grains and/or silicon carbide abrasive grains.

8. The SiC wafer according to any one of claims 1 to 7, wherein the wafer thickness is 1mm or less.

9. A method for manufacturing a SiC wafer, comprising:

a pear skin surface processing step, wherein pear skin surface processing is carried out on at least the back surface of the SiC wafer; and

an etching step of etching at least a back surface of the SiC wafer by heating under Si vapor pressure after the pearskin surface processing step.

10. The method of manufacturing an SiC wafer according to claim 9, further comprising a mirror finishing step of mirror finishing a principal surface of the SiC wafer after the etching step.

11. The method of manufacturing a SiC wafer according to claim 9 or claim 10, wherein the pearskin surface processing step is free abrasive grain processing using boron carbide abrasive grains and/or silicon carbide abrasive grains.

12. The method of manufacturing an SiC wafer according to any one of claims 9 to 11, characterized in that the etching step has: and a roughness adjusting step of adjusting the roughness of the back surface by controlling the etching amount so that the arithmetic mean deviation Ra is 50nm to 300 nm.

13. A SiC wafer characterized by being substantially free of a process-altered layer.

14. A SiC wafer characterized by comprising:

a main surface on which a semiconductor element is fabricated;

a back surface opposite the major surface;

a peripheral portion connected to outer edges of the main surface and the back surface;

a notch portion provided at a part of the outer peripheral portion; and

an imprint section provided at the main surface or the back surface,

wherein the main surface, the back surface, the outer peripheral portion, the cut portion, and the imprint portion are substantially free of a processing-altered layer.

15. A SiC wafer is characterized by being substantially free from lattice strain other than lattice strain caused by surface restructuring.

16. A SiC wafer characterized by comprising:

a main surface on which a semiconductor element is formed;

a back surface opposite the major surface; and

a bulk layer adjacent to the major surface and the back surface,

wherein the bulk layer has a lattice strain amount of 0.01% or less with respect to the base lattice.

17. The SiC wafer of any one of claims 13 to 16, characterized in that the SORI value does not change when heated in the temperature range of 1500 ℃ to 2000 ℃.

18. A method for manufacturing a SiC wafer, comprising:

a planarization step of planarizing the SiC wafer; and

an etching step of etching the main surface and the back surface of the SiC wafer by heating under Si vapor pressure after the planarization step.

19. The method of manufacturing a SiC wafer of claim 18 wherein the processing temperature of the etching step is 1500 ℃ or higher.

20. The method of manufacturing a SiC wafer according to claim 18 or claim 19, characterized by comprising: and a mirror finishing step of mirror finishing the principal surface of the SiC wafer subsequent to the etching step.

21. The method for manufacturing an SiC wafer according to any one of claims 18 to 20, characterized by further comprising, before the etching step:

an ingot shaping step of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot;

a crystal orientation forming step of forming a notch portion indicating a crystal orientation at a part of an outer periphery of the ingot;

a slicing step of slicing the ingot to obtain a thin disc-shaped SiC wafer;

an imprint forming step of selectively removing the surface of the SiC wafer to form an imprint portion; and

and a chamfering step of chamfering an outer peripheral portion of the SiC wafer.

22. A method for manufacturing a SiC wafer, comprising:

a planarization step of planarizing the SiC wafer in the presence of abrasive grains having a modified mohs hardness of less than 15; and

an etching step of etching the SiC wafer by heating under Si vapor pressure.

23. The method of producing a SiC wafer according to claim 22, characterized in that the abrasive grains are abrasive grains having a modified mohs hardness of 13 or more.

24. The method of manufacturing a SiC wafer according to claim 22 or claim 23, wherein the abrasive grains are boron carbide abrasive grains and/or silicon carbide abrasive grains.

25. The method of producing the SiC wafer of any one of claims 22 to 24, wherein the flattening step is a free abrasive grain manner.

26. The method of producing the SiC wafer according to any one of claims 22 to 25, wherein an amount of etching the SiC wafer by the etching step is 10 μm or less per surface.

27. The method for manufacturing the SiC wafer according to any one of claims 22 to 26, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed before the etching step.

28. The method for manufacturing the SiC wafer according to any one of claims 22 to 26, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed after the planarizing step.

29. A method for manufacturing a SiC wafer, comprising:

a flattening step of flattening the SiC wafer while grinding the abrasive grains in a free abrasive grain manner; and

an etching step of etching the SiC wafer by heating under Si vapor pressure.

30. The method of producing the SiC wafer according to claim 29, wherein in the flattening step, the SiC wafer is flattened while grinding the abrasive grains so that an average abrasive grain diameter at the start of processing is 20 μm or more and an average abrasive grain diameter at the end of processing is less than 20 μm.

31. A method for manufacturing a SiC wafer, comprising:

a flattening step of flattening the SiC wafer by the free abrasive method using abrasive grains having brittleness, which are crushed by the free abrasive method; and

an etching step of etching the SiC wafer by heating under Si vapor pressure.

32. The method of manufacturing a SiC wafer according to claim 31, wherein the abrasive grains satisfy the following brittleness condition:

brittle conditions: when the processing pressure is 150g/cm²When both surfaces of the surface of the SiC wafer were simultaneously planarized with the free abrasive by using abrasive grains adjusted to have an average abrasive grain size of 40 μm under the conditions (1), the average abrasive grain size became 20 μm or less after a processing time of 20 minutes.

33. The method of manufacturing a SiC wafer according to any one of claims 29 to 32, wherein the abrasive grains are boron carbide abrasive grains and/or silicon carbide abrasive grains.

34. The method of manufacturing the SiC wafer according to any one of claims 29 to 33, wherein an amount of etching the SiC wafer by the etching step is 10 μm or less per one surface.

35. The method for manufacturing the SiC wafer according to any one of claims 29 to 34, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint on a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed before the etching step.

36. The method for manufacturing the SiC wafer according to any one of claims 29 to 34, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed after the planarizing step.

37. A method for manufacturing a SiC wafer, comprising:

a slicing step of slicing the ingot to obtain a SiC wafer;

a planarization step of planarizing the SiC wafer; and

an etching step of etching the SiC wafer by heating under Si vapor pressure and removing the process-altered layer introduced in the planarization step,

wherein in the dicing step, a SiC wafer having a thickness obtained by adding a thickness of 122 μm or less to a thickness of the SiC wafer after the surface processing including the flattening step and the etching step is completed is obtained.

38. The method of manufacturing an SiC wafer according to claim 37, wherein in the dicing step, an SiC wafer is obtained in which a thickness of less than 100 μm is added to a thickness of the SiC wafer after the surface processing including the flattening step and the etching step is finished.

39. The method of manufacturing an SiC wafer according to claim 37 or claim 38, wherein in the dicing step, an SiC wafer is obtained in which a thickness of less than 87 μm is added to a thickness of the SiC wafer after the end of the surface processing including the flattening step and the etching step.

40. The method of manufacturing the SiC wafer according to any one of claims 37 to 39, wherein in the dicing step, a SiC wafer is obtained in which a thickness of 61 μm or more is added to a thickness of the SiC wafer after the surface processing including the flattening step and the etching step is finished.

41. The method of producing the SiC wafer according to any one of claims 37 to 40, wherein the thickness of the SiC wafer after the completion of the surface processing is 300 to 400 μm.

42. The method of producing the SiC wafer according to any one of claims 37 to 41, wherein in the dicing step, the SiC wafer having a thickness of 472 μm or less is obtained.

43. The method of producing the SiC wafer of any one of claims 37 to 42, wherein an etching amount in the etching step is 10 μm or less per one surface of the SiC wafer.

44. The method of manufacturing an SiC wafer according to any one of claims 37 to 43, characterized in that in the flattening step, boron carbide abrasive grains and/or silicon carbide abrasive grains are used.

45. The method of producing the SiC wafer of any one of claims 37 to 44, wherein the flattening step is a free abrasive grain manner.

46. The method for manufacturing the SiC wafer of any one of claims 37 to 45, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed before the etching step.

47. The method for manufacturing the SiC wafer of any one of claims 37 to 45, further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed after the planarizing step.

48. A method for manufacturing a SiC wafer, comprising:

a planarization step of planarizing the SiC wafer;

an etching step of etching the SiC wafer by heating under Si vapor pressure after the planarization step; and

and a chemical mechanical polishing step, wherein the surface of the SiC wafer is subjected to chemical mechanical polishing processing after the etching step.

49. The method of manufacturing an SiC wafer of claim 48 further comprising:

a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and

an imprint forming step of forming an imprint at a surface of the SiC wafer,

wherein the chamfering step and the imprint forming step are performed before the etching step.

50. The method of manufacturing an SiC wafer according to claim 49, wherein the chamfering step and the imprint forming step are performed after the planarizing step.

51. The method of producing the SiC wafer of any one of claims 48 to 50, wherein a step of newly causing a process-altered layer in the SiC wafer is not included after the etching step.

52. The method of producing the SiC wafer of any one of claims 48 to 51, comprising a chemical mechanical polishing step of performing a chemical mechanical polishing process on the surface of the SiC wafer after the etching step.

53. The method of manufacturing an SiC wafer of any one of claims 48 to 52 wherein, in the chemical mechanical polishing step, chemical mechanical polishing processing is performed only on the (0001) plane of the SiC wafer.

54. The method of producing the SiC wafer of any one of claims 48 to 53, wherein boron carbide abrasive grains and/or silicon carbide abrasive grains are used in the planarization step.

55. The method of producing the SiC wafer of any one of claims 48 to 54, wherein an amount of etching the SiC wafer by the etching step is 10 μm or less per surface.

Technical Field

The present invention relates to a SiC wafer and a method for producing the SiC wafer.

Background

In recent years, silicon carbide (SiC) semiconductor devices have attracted attention as energy-saving, high-performance semiconductor devices because they have higher breakdown voltage and higher efficiency than silicon (Si) and gallium arsenide (GaAs) semiconductor devices, and can operate at high temperatures.

Conventionally, a SiC wafer for a semiconductor device on the market is generally processed to have a mirror surface on its main surface and back surface. On the other hand, in Si wafers and the like, a pearskin surface processing is performed on the back surface of the wafer (for example, see patent document 1).

Thus, the back surface of the wafer is made into a pearskin surface, whereby the main surface and the back surface of the wafer can be easily recognized. Further, there are advantages that the friction coefficient of the back surface of the wafer is increased, slip during transportation or in the apparatus is prevented, and peeling from the sample stage of the electrostatic chuck system is easy.

Further, a silicon carbide (SiC) wafer is formed by slicing an ingot of single crystal SiC. A surface layer (hereinafter, referred to as a work-affected layer) having strain, damage, and the like of a crystal introduced at the time of slicing is present at the surface of the sliced SiC wafer. The process-altered layer needs to be removed in order not to lower the yield in the device manufacturing step.

Conventionally, the mainstream of such removal of the machining-affected layer is removal by surface machining using diamond abrasive grains. In recent years, various surface processing techniques have been proposed without using diamond abrasive grains.

For example, non-patent document 1 discloses a method using boron carbide (B)₄C) Free abrasive grain polishing processing technology of abrasive grains. This is achieved byIn addition, patent document 2 describes an etching technique in which an SiC wafer is heated under Si vapor pressure to perform etching (hereinafter, also referred to as Si vapor pressure etching).

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2004-200240

Patent document 2: japanese patent laid-open publication No. 2011-247807

Non-patent document

Non-patent document 1: 2014-year precision workshop autumn college academic lecture corpus p.605-606

Disclosure of Invention

Problems to be solved by the invention

However, unlike single crystal Si, single crystal SiC transmits visible light because of its light transmittance. Therefore, in a device manufacturing step using an optical sensor, there is a problem that it is difficult to detect a wafer.

A first problem to be solved by the present invention is to provide a SiC wafer and a method for manufacturing the same, which can improve the detection rate of an optical sensor.

Further, single crystal SiC is a hard and brittle material having hardness next to diamond or the like and a characteristic of being easily cleaved at a (0001) plane or a (1-100) plane, and is classified as a material extremely difficult to process. What is needed in the processing steps of semiconductor materials are: "high quality (high flatness, no damage)", "low loss (material loss, yield)", "low cost (high efficiency, inexpensive means/steps)", however, the more they exhibit high hard brittleness, the more they are in a trade-off relationship, and it is difficult to achieve both of them at the same time.

Among them, in order to industrially produce SiC wafers, a technique for producing high-quality SiC wafers is particularly required. In particular, SiC wafers having a work-affected layer have a problem of an increase in SORI value during high-temperature annealing in the subsequent device manufacturing steps, or a problem of occurrence of cracks (damages) or crystal strain as defects.

Therefore, it is desirable to remove the process-altered layer in the entire region of the SiC wafer. However, there is no means for removing the processing-altered layer at a portion other than the main surface and the back surface of the SiC wafer, for example, a notch portion such as an outer peripheral portion or an orientation flat, or a periphery of a scribe portion.

A second problem to be solved by the present invention is to provide a high-quality SiC wafer from which damage and lattice strain are removed, and a method for manufacturing the same.

Further, reducing the amount of removal of single crystal SiC (material loss) in surface processing contributes to reducing the cost of SiC wafers. That is, by reducing the material loss in the surface processing, the number of SiC wafers taken out from one ingot can be increased, and the unit price per wafer can be lowered.

A third problem to be solved by the present invention is to provide a method for manufacturing an SiC wafer capable of reducing material loss.

A fourth problem to be solved by the present invention is to provide a method for manufacturing a SiC wafer, which is capable of reducing material loss and manufacturing more SiC wafers from one ingot.

In addition, in order to industrially produce SiC wafers, a technique for producing high-quality SiC wafers is particularly required.

A fifth problem to be solved by the present invention is to provide a novel SiC wafer manufacturing method capable of manufacturing a high-quality SiC wafer.

Means for solving the problems

An SiC wafer according to an aspect of the present invention for solving the first problem is characterized by comprising: a mirror-finished main surface; and the back processed by the pear peel surface.

In this way, the detection rate of the optical sensor can be improved by forming the back surface of the SiC wafer as a peaked surface.

In this aspect, the arithmetic mean deviation Ra of the back surface is 50nm to 300 nm.

In this aspect, the maximum height Rz of the rear surface is 0.5 μm to 5 μm.

By adopting such roughness, it is possible to prevent the wafer from slipping, to suppress the adhesion of particles and the like, and to prevent the flatness of the wafer from deteriorating when it is held on the sample stage.

In this aspect, it is characterized in that the back surface is substantially free of a process-altered layer.

Thus, since a process-affected layer is not substantially generated at the back surface, a pearskin surface preferable for a device manufacturing step can be formed.

In addition, in another aspect of the present invention to solve the first problem, the SiC wafer is characterized in that at least the back surface of the SiC wafer is etched by heating under Si vapor pressure after the pearskin surface processing.

Thus, by heating under Si vapor pressure after the pearskin face processing, a pearskin face preferable to the device manufacturing step can be formed.

In addition, another aspect of the present invention to solve the first problem is a SiC wafer characterized in that at least a back surface of the SiC wafer is subjected to a pearskin surface processing and heated under Si vapor pressure to be etched, and a main surface of the SiC wafer is mirror-finished.

In these aspects, it is characterized in that the pearskin face machining is free abrasive machining using boron carbide abrasive grains and/or silicon carbide abrasive grains.

In these aspects, the wafer thickness is 1mm or less.

The present invention also relates to a method for producing the SiC wafer. That is, the method for producing an SiC wafer of the present invention for solving the first problem includes: a pear skin surface processing step, wherein pear skin surface processing is carried out on at least the back surface of the SiC wafer; and an etching step of etching at least the back surface of the SiC wafer by heating under Si vapor pressure after the pearskin surface processing step.

Single crystal SiC is a hard and brittle material having hardness next to diamond or the like and a characteristic of being easily cleaved at the (0001) plane or the (1-100) plane, and is classified as a material extremely difficult to process. However, according to the manufacturing method of the present invention, for such a SiC wafer that is difficult to process, a pear peel face suitable for a device manufacturing step can be formed at the back face.

In this aspect, the method further includes: and a mirror finishing step of mirror finishing the principal surface of the SiC wafer after the etching step.

In this aspect, it is characterized in that the pearskin surface processing step is free abrasive grain processing using boron carbide abrasive grains and/or silicon carbide abrasive grains.

In this aspect, the etching step is characterized by having: and a roughness adjusting step of adjusting the roughness of the back surface by controlling the etching amount so that the arithmetic mean deviation Ra is 50nm to 300 nm.

In order to solve the second problem, an SiC wafer according to an aspect of the present invention is characterized by being substantially free of a process-degraded layer.

In addition, a SiC wafer according to another aspect of the present invention to solve the second problem described above includes: a main surface on which a semiconductor element is fabricated; a back surface opposite the major surface; a peripheral portion connected to outer edges of the main surface and the back surface; a notch portion provided at a part of the outer peripheral portion; and an imprint section provided on the main surface or the rear surface, wherein the main surface, the rear surface, the outer peripheral portion, the cutout portion, and the imprint section are substantially free from a work-affected layer.

In addition, a SiC wafer according to another aspect of the present invention that solves the second problem is characterized by substantially no lattice strain other than lattice strain due to surface restructuring.

In addition, a SiC wafer according to another aspect of the present invention to solve the second problem described above includes: a main surface on which a semiconductor element is formed; a back surface opposite the major surface; and a bulk layer adjacent to the main surface and the back surface, wherein an amount of lattice strain of the bulk layer with respect to a reference lattice is 0.01% or less.

Thus, since lattice strain other than lattice strain due to surface restructuring is substantially eliminated, a high-quality SiC wafer preferable for the subsequent device manufacturing step can be obtained.

In this aspect, the bulk layer has a lattice strain amount of 0.01% or less with respect to the base lattice.

In this aspect, it is characterized in that the SORI value does not change when heated in a temperature range of 1500 ℃ to 2000 ℃.

Further, a method for manufacturing a SiC wafer according to an aspect of the present invention to solve the second problem described above includes: a planarization step of planarizing the SiC wafer; and an etching step of etching the main surface and the back surface of the SiC wafer by heating under Si vapor pressure after the planarization step.

In this aspect, the processing temperature in the etching step is 1500 ℃.

In this aspect, the method is characterized by comprising: and a mirror finishing step of mirror finishing the principal surface of the SiC wafer subsequent to the etching step.

In this aspect, before the etching step, the method further includes: an ingot shaping step of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot; a slicing step of slicing the ingot to obtain a thin disc-shaped SiC wafer; an imprint forming step of selectively removing the surface of the SiC wafer to form an imprint portion; and a chamfering step of chamfering an outer peripheral portion of the SiC wafer.

A method for manufacturing a SiC wafer according to an aspect of the present invention for solving the third problem described above includes: a planarization step of planarizing the SiC wafer in the presence of abrasive grains having a modified mohs hardness of less than 15; and an etching step of etching the SiC wafer by heating under Si vapor pressure.

By combining such a planarization step and an etching step, the amount of material loss removed in the process-altered layer removal step can be reduced.

In this aspect, the abrasive grains are abrasive grains having a modified mohs hardness of 13 or more.

By using abrasive particles of such hardness, the processing time can be reduced.

In this aspect, the abrasive grains are boron carbide abrasive grains and/or silicon carbide abrasive grains.

By using such a material for the abrasive grains, the material cost can be reduced as compared with diamond abrasive grains.

In this aspect, it is characterized in that the flattening step is a free abrasive manner.

In this aspect, it is characterized in that, by the etching step, the SiC wafer is etched by an amount of 10 μm or less per one surface.

In this aspect, the method further includes: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed before the etching step.

In this aspect, the method further includes: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed after the planarizing step.

A method for manufacturing a SiC wafer according to an aspect of the present invention for solving the third problem described above includes: a flattening step of flattening the SiC wafer while grinding the abrasive grains in a free abrasive grain manner; and an etching step of etching the SiC wafer by heating under Si vapor pressure.

By combining such a planarization step and an etching step, the amount of material loss removed in the process-altered layer removal step can be reduced.

In this aspect, the flattening step flattens the SiC wafer while grinding the abrasive grains so that an average abrasive grain diameter at the start of processing is 20 μm or more and an average abrasive grain diameter at the end of processing is less than 20 μm.

By planarizing the SiC wafer while grinding the abrasive grains under such conditions, the work-affected layer introduced into the SiC wafer in the planarization step can be formed thinner and more uniformly, whereby the material loss can be further reduced.

In addition, a method for manufacturing a SiC wafer according to another aspect of the present invention for solving the third problem described above includes: a flattening step of flattening the SiC wafer by the free abrasive method using abrasive grains having brittleness, which are crushed by the free abrasive method; and an etching step of etching the SiC wafer by heating under Si vapor pressure.

By combining the planarization step and the etching step using such abrasive grains, the amount of material loss removed in the process-altered layer removal step can be reduced.

In this aspect, the abrasive grains are characterized by satisfying the following brittleness condition:

brittle conditions: when the processing pressure is 150g/cm²When both surfaces of the surface of the SiC wafer were simultaneously planarized with the free abrasive by using abrasive grains adjusted to have an average abrasive grain size of 40 μm under the conditions (1), the average abrasive grain size became 20 μm or less after a processing time of 20 minutes.

In this aspect, the abrasive grains are boron carbide abrasive grains and/or silicon carbide abrasive grains.

By using such a material for the abrasive grains, the material cost can be reduced as compared with diamond abrasive grains.

In this aspect, it is characterized in that, by the etching step, the SiC wafer is etched by an amount of 10 μm or less per one surface.

In these aspects, the method further comprises: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed before the etching step.

In these aspects, the method further comprises: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed after the planarizing step.

A method for manufacturing a SiC wafer according to an aspect of the present invention to solve the fourth problem is characterized by including: a slicing step of slicing the ingot to obtain a SiC wafer; a planarization step of planarizing the SiC wafer; and an etching step of etching the SiC wafer by heating under Si vapor pressure and removing the process-altered layer introduced in the planarization step, wherein in the slicing step, a SiC wafer having a thickness obtained by adding a thickness of 122 μm or less to a thickness of the SiC wafer after the end of surface processing including the planarization step and the etching step is obtained.

By using an etching step in the process-altered layer removal step, material loss in this step can be reduced.

Specifically, the SiC wafer can be manufactured with little material loss as compared with the conventional method of 122 μm or less. Therefore, the SiC wafer having "a thickness obtained by adding a thickness of 122 μm or less to the thickness of the SiC wafer after the end of surface processing" may be cut out in the dicing step. Thereby, more SiC wafers can be produced from one ingot as compared with the conventional method.

In this aspect, it is characterized in that the dicing step obtains the SiC wafer having a thickness obtained by adding a thickness of less than 100 μm to the thickness of the SiC wafer after the surface processing including the planarizing step and the etching step is finished.

In this aspect, it is characterized in that the dicing step obtains the SiC wafer having a thickness obtained by adding a thickness of less than 87 μm to the thickness of the SiC wafer after the surface processing including the planarizing step and the etching step is finished.

In this aspect, the dicing step is characterized in that the SiC wafer having a thickness obtained by adding a thickness of 61 μm or more to the thickness of the SiC wafer after the surface processing including the flattening step and the etching step is completed is obtained.

In this aspect, the thickness of the SiC wafer after the surface processing is finished is 300 μm to 400 μm.

In this aspect, it is characterized in that the dicing step obtains a SiC wafer having a thickness of 472 μm or less.

In this aspect, the etching amount in the etching step is 10 μm or less per one surface of the SiC wafer.

In this aspect, it is characterized in that the planarization step uses boron carbide abrasive grains and/or silicon carbide abrasive grains.

By using such a material for the abrasive grains, the material cost can be reduced as compared with the diamond abrasive grains commonly used in the conventional method.

In this aspect, it is characterized in that the flattening step is a free abrasive manner.

In this aspect, the method further includes: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed before the etching step.

In this aspect, the method further includes a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed after the planarizing step.

A method for manufacturing a SiC wafer according to an aspect of the present invention to solve the fifth problem is characterized by including: a planarization step of planarizing the SiC wafer; an etching step of etching the SiC wafer by heating under Si vapor pressure after the planarization step; and a chemical mechanical polishing step of performing chemical mechanical polishing processing on the surface of the SiC wafer after the etching step.

Thus, by including: a planarization step of planarizing the SiC wafer; an etching step of removing the strained layer introduced into the wafer; and a chemical mechanical polishing step for making the surface mirror-like, and a high-quality SiC wafer can be produced.

In this aspect, the method further includes: a chamfering step of chamfering an outer peripheral portion of the SiC wafer; and an imprint forming step of forming an imprint at a surface of the SiC wafer, wherein the chamfering step and the imprint forming step are performed before the etching step.

By performing the etching step after the chamfering step and the imprint forming step, it is also possible to remove the processing-altered layer in the outer peripheral portion formed by the chamfering step and the imprint formed by the imprint forming step.

In this aspect, it is characterized in that the chamfering step and the imprint forming step are performed after the planarization step.

In this way, by removing the waviness of the SiC wafer by performing the planarization step first, the scribe formation in the scribe formation step and the chamfering position in the chamfering step can be determined with high accuracy, and the homogeneity of the wafer can be improved.

In this aspect, it is characterized in that a step of newly causing a process-altered layer in the SiC wafer is not included after the etching step.

By carrying out all the steps of introducing the process-altered layer into the SiC wafer before the etching step, a high-quality SiC wafer can be produced.

In this aspect, the method is characterized by comprising: a chemical mechanical polishing step of performing a chemical mechanical polishing process on the surface of the SiC wafer after the etching step.

By performing the chemical mechanical polishing step immediately after the etching step without interposing other steps, a high-quality SiC wafer can be manufactured.

In this aspect, it is characterized in that the chemical mechanical polishing step performs the chemical mechanical polishing process only on the (0001) plane of the SiC wafer.

By performing chemical mechanical polishing processing only on the (0001) surface of the SiC wafer, a high-quality SiC wafer having a mirror surface and a pearskin surface can be manufactured.

In this aspect, it is characterized in that the planarization step uses boron carbide abrasive grains and/or silicon carbide abrasive grains.

By using such a material for the abrasive grains, the material cost can be reduced as compared with diamond abrasive grains.

In these aspects, it is characterized in that, by the etching step, the SiC wafer is etched by an amount of 10 μm or less per one surface.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the disclosed technology, a SiC wafer and a SiC wafer manufacturing method that can improve the detection rate of an optical sensor can be provided.

Further, according to the disclosed technology, a high-quality SiC wafer from which damage and lattice strain are removed and a manufacturing method thereof can be provided.

Further, according to the disclosed technology, a method for manufacturing a SiC wafer capable of reducing material loss can be provided.

Further, according to the disclosed technology, it is possible to provide a new SiC wafer manufacturing method capable of reducing material loss and manufacturing more SiC wafers from one ingot.

Further, according to the disclosed technology, a high-quality SiC wafer can be manufactured.

Other problems, features, and advantages will become apparent from the following description of the manner for carrying out the invention, when taken in conjunction with the accompanying drawings and the claims.

Drawings

Fig. 1 is a schematic diagram showing a manufacturing step of a SiC wafer that solves the first problem.

Fig. 2 is an explanatory view showing steps from an ingot to a wafer among the manufacturing steps of SiC wafers solving the first to fifth problems.

Fig. 3 is an explanatory diagram showing a manufacturing step of the SiC wafer that solves the first problem and the second problem.

Fig. 4 is a schematic view showing a high-temperature vacuum furnace used in Si vapor pressure etching.

Fig. 5 is a schematic diagram showing a manufacturing step of a SiC wafer that solves the second problem.

Fig. 6 is a schematic diagram showing manufacturing steps of a SiC wafer that solves the third to fifth problems.

Fig. 7 is an explanatory diagram showing manufacturing steps of a SiC wafer that solves the third to fifth problems.

Fig. 8 is an image obtained by observing the back surface of the SiC wafer of example 1 with a white interference microscope.

Fig. 9 is an image obtained by observing the back surface of the SiC wafer of example 2 with a white interference microscope.

Fig. 10 is a graph showing the reflectance of the SiC wafer of example 1.

Fig. 11 is a graph showing the external transmittance of the SiC wafer of example 1.

Fig. 12 is an image obtained by observing a cross section of the SiC wafer of example 1 with SEM-EBSD.

Fig. 13 is an image obtained by observing a cross section of the SiC wafer of example 2 with SEM-EBSD.

Fig. 14 is an image obtained by observing a cross section of the SiC wafer of example 1 with a transmission electron microscope.

Fig. 15 is an image obtained by observing a cross section of the SiC wafer of example 2 with a transmission electron microscope.

Fig. 16 is an image obtained by observing a cross section of the SiC wafer of example 3 with a transmission electron microscope.

Fig. 17 is an image obtained by observing a cross section of the SiC wafer of example 4 with a transmission electron microscope.

Fig. 18 is an image obtained by observing a cross section of the SiC wafer of comparative example 1 with a transmission electron microscope.

Fig. 19 is an image obtained by observing a cross section of the SiC wafer of comparative example 2 with a transmission electron microscope.

Fig. 20 is an image obtained by observing a cross section of the SiC wafer of example 5 with SEM-EBSD.

Fig. 21 is an image obtained by observing a cross section of the SiC wafer of example 6 with SEM-EBSD.

Fig. 22 is a conceptual view of a surface of a SiC wafer after a general machining process is performed, as viewed in cross section.

Fig. 23 is a graph showing a relationship between the process-denatured layer depth and the warp (SORI value) of a single crystal SiC wafer.

Fig. 24 is a schematic diagram showing a manufacturing step of a conventional SiC wafer.

Fig. 25 is an explanatory diagram showing a manufacturing step of a conventional SiC wafer.

Fig. 26 is a schematic diagram showing a manufacturing step of a conventional SiC wafer.

Fig. 27 is an explanatory diagram showing a manufacturing step of a conventional SiC wafer.

Detailed Description

Hereinafter, an embodiment of the SiC wafer manufacturing method of the present invention will be described in detail.

Fig. 22 is a conceptual diagram of a surface of a wafer subjected to machining as viewed in cross section. The SiC wafer 20 is formed by slicing and flattening the ingot 10 of single crystal SiC. At this time, a work-affected layer 30 is introduced on the surface of the SiC wafer 20, and the work-affected layer 30 includes a crack layer 31 having a large number of cracks (damages) and a strain layer 32 in which lattice strain is generated. The altered layer 30 is also introduced in the surface processing for forming the embossed portion 25 by selectively removing the wafer surface by laser processing or the like.

The process-altered layer 30 needs to be removed in order not to lower the yield in the device manufacturing step. That is, it is preferable to expose the bulk layer 33 below the work-affected layer 30 where cracks or lattice strain due to surface processing is not introduced.

In addition, in general, the SiC wafer 20 having the work-affected layer 30 has warpage caused by the work-affected layer 30. One of the indices for evaluating the warp shape is the SORI value. The SORI value is a sum of normal distances from a least-squares plane calculated by a least-squares method using all data on the wafer surface to the highest point and the lowest point on the wafer surface, when measured in such a manner that the back surface of the wafer is supported without changing the original shape.

It has been newly found that the larger the diameter of the wafer, the more susceptible the SORI value is to the affected by the process-altered layer 30. Fig. 23 shows a graph of the relationship between the depth of the process-altered layer 30 of the single crystal SiC wafer and the SORI value. As shown in fig. 23, it is understood that the deeper the depth of the work-affected layer 30, the greater the value of the SORI value. Further, when a 6-inch (about 15.24cm) single crystal SiC wafer is compared with a 4-inch (about 10.16cm) single crystal SiC wafer, it is found that the 6-inch (about 15.24cm) single crystal SiC wafer is more easily affected by the work-affected layer 30, and the SORI value becomes large. Therefore, in order to reduce the warpage of the SiC wafer, it is important to remove the work-affected layer 30.

In the description of the present specification, the surface of the SiC wafer 20 on which the semiconductor element is fabricated (specifically, the surface on which the epitaxial film is deposited) is referred to as a main surface 21, and the surface opposite to the main surface 21 is referred to as a back surface 22. The principal surface 21 and the back surface 22 are collectively referred to as a front surface. Examples of the main surface 21 include a (0001) surface, a (000-1) surface, and a surface having an off angle of several degrees from these surfaces. (in addition, in the present specification, in the notation of miller index, "-" denotes a bar attached to the index immediately thereafter).

SiC wafer

< SiC wafer for solving the first problem >

The SiC wafer 20 of the present invention for solving the first problem is characterized by including: a mirror-finished main surface 21 and a rind-finished back surface 22.

Single crystal SiC has optical transparency and transmits visible light. Therefore, in the device manufacturing step, there is a problem that it is difficult to detect the wafer using the optical sensor. Since the back surface 22 of the SiC wafer 20 of the present invention is a pearskin surface, the detection rate of the optical sensor can be improved as compared with a conventional SiC wafer whose both surfaces are mirror surfaces.

Further, since the back surface of the wafer has a large friction coefficient, it is difficult to slide during transportation or in the apparatus, and it is easy to peel off from the electrostatic chuck type sample stage, which is advantageous in the device manufacturing process.

In the description of the present specification, the pear skin surface is a concept representing a surface having fine irregularities formed like the surface of a pear fruit. Examples of the pear peel surface include a surface in which irregular fine spot-like irregularities are combined disorderly without directionality, or a surface in which stripe-like irregularities extending in one direction are arranged.

In particular, the back surface 22 having the pearskin surface does not cause a variation in reflectance of visible light incident from the main surface 21 side of the mirror surface for each wavelength. On the other hand, when both surfaces are mirror surfaces, the reflectance in a specific wavelength region increases due to interference of light or the like, and the reflectance varies for each wavelength.

That is, the pearskin surface diffuses and scatters incident light, thereby suppressing interference and the like occurring in a specific wavelength region, and reducing a difference in reflectance for each wavelength. This makes it possible to improve the detection rate for various optical sensors having different wavelengths to be used. In addition, the difference in reflectance per wavelength in the visible light region is preferably 6% or less, more preferably 5% or less, and further preferably 4% or less.

In other words, it is desirable that the reflectance on the mirror surface side in the visible light is not deviated for each wavelength, and the difference in reflectance for each wavelength is 6% or less, more preferably 5% or less, and further preferably 4% or less.

In this way, the SiC wafer 20 having the peaked surface can improve the detection rate for optical sensors of various wavelengths by reducing the difference in reflectance for each wavelength. That is, the pearskin surface diffuses and scatters incident light, thereby suppressing interference and the like occurring in a specific wavelength region, and reducing a difference in reflectance for each wavelength.

The reflectance of the main surface 21 incident on the mirror surface is preferably 10% or more, and more preferably 15% or more in the wavelength region of visible light. On the other hand, the reflectance of visible light incident on the back surface 22 of the pearskin surface is preferably 5% or less, more preferably 3% or less, and still more preferably 2% or less.

The SiC wafer 20 provided with the peaked surface having such a reflectance has a high detection rate of the optical sensor used in the device manufacturing step. That is, since such a pearskin surface has low reflectance and high visibility, the wafer can be easily inspected. Further, since the mirror surface (main surface 21) can be easily recognized, the back surface 22 is not erroneously focused when focusing on the main surface 21 is intended even in an inspection step of a wafer or a component, and inspection and diagnosis can be appropriately performed.

Further, although it cannot be expressed by numerical values, as the surface shape of the pearskin surface, it is preferable that a plurality of gentle convex portions different in diameter are in a structure in which they are arranged in scale. By configuring the pear skin surface in such a shape, the advantage in the device manufacturing step can be further improved.

In the description of the present specification, the term "reflectance" as used herein means a ratio of reflection of an electromagnetic wave having a wavelength of 300nm to 1500nm at a surface of an SiC wafer when the surface is irradiated with the irradiated electromagnetic wave. In the description of the present specification, the term "visible light" refers to an electromagnetic wave having a wavelength of 360nm to 830 nm.

Desirably, the external transmittance of visible light including the interface of the SiC wafer 20 is preferably 25% or less. The optical sensor of the SiC wafer 20 having such an external transmittance has a high detection rate, and detection errors in the device manufacturing steps can be suppressed.

In the description of the present specification, when referring to the external transmittance, it means a ratio of transmitting inside the SiC wafer 20 when electromagnetic waves having a wavelength of 300nm to 1500nm are irradiated to the main surface 21 or the back surface 22 of the SiC wafer.

The thickness of the SiC wafer 20 (wafer thickness) is preferably 1mm or less, more preferably 500 μm or less, and still more preferably 50 μm to 350 μm.

Even if the SiC wafer 20 is set to such a thin thickness, the rear surface 22 is processed into a pearskin surface, and therefore, the detection rate of the optical sensor can be improved.

The arithmetic average roughness Ra of the pearskin surface is preferably 50nm to 300nm, more preferably 75nm to 200 nm.

The maximum height Rz of the pear skin surface is preferably 0.5 to 5 μm, more preferably 0.75 to 2.5 μm.

By forming the roughness of the pearskin surface at such a value, the following advantages can be more strongly exerted: the recognition of the main surface and the back surface of the SiC wafer 20 becomes easy; the friction coefficient of the back surface of the wafer is increased, and the wafer is prevented from sliding during transportation or in the device; the sample was easily peeled off from the electrostatic chuck type sample table.

Further, it is possible to more strongly suppress troubles such as easy adhesion of particles and deterioration of flatness of the wafer when the wafer is held on the sample stage.

In addition, in the description in the present specification, when referring to the arithmetic average roughness Ra and the maximum height Rz, it means the arithmetic average roughness and the maximum height according to Japanese Industrial Standard (JIS) B0601-2001.

Although not shown by numerical values, the SiC wafer 20 of the present invention preferably has a convex surface with a smooth edge from which fine burrs are removed, as the surface shape of the pericarp surface.

On the other hand, the arithmetic average roughness Ra of the mirror surface is preferably 0.05nm to 0.3nm, more preferably 0.05nm to 0.1 nm.

The maximum height Rz of the mirror surface is 0.2 μm to 1.2 μm, and more preferably 0.2 μm to 0.4 μm.

By forming the mirror surface in this manner, the principal surface and the back surface of the wafer can be easily recognized.

SiC wafer 20 may have an orientation flat 24 and an imprint 25. Further, the shape of the SiC wafer 20 is not particularly limited, and is typically a thin disk shape.

< SiC wafer for solving the second problem >

The SiC wafer 20 of the present invention that solves the second problem is characterized by substantially not having the affected layer 30. That is, the main surface 21, the back surface 22 facing the main surface 21, the outer peripheral portion 23, the orientation flat 24, the notch such as the notch, and the scribe portion 25 of the semiconductor element are substantially free from the work-affected layer 30. In other words, it is desirable that there is substantially no lattice strain other than that caused by surface reconstruction. In other words, bulk layer 33 adjacent to main surface 21 and back surface 22 is substantially free from lattice strain other than lattice strain due to surface restructuring.

Further, it is desirable that lattice strain does not occur in the lattice under the surface (main surface 21 and back surface 22) of the SiC wafer 20. In other words, it is desirable to have: a main surface 21, a bulk layer 33 provided directly below the main surface 21, and a back surface 22 provided directly below the bulk layer 33.

Here, "substantially no processing-deteriorated layer" means that there is no processing-deteriorated layer to such an extent that it affects the device manufacturing steps. For example, it means that there is no work-affected layer having a lattice strain amount exceeding 0.01% as described later.

Further, "substantially free of lattice strain other than lattice strain due to surface restructuring" means that there is no lattice strain to such an extent that it affects the device manufacturing steps. For example, the lattice strain amount of the single crystal SiC constituting the SiC wafer 20 other than the surface is 0.01% or less.

In this way, by not causing lattice strain in the entire region within the SiC wafer 20, the SiC wafer 20 preferable for the device manufacturing step can be provided.

In addition, in the description in the present specification, when lattice strain is referred to, lattice strain other than lattice strain caused by surface reconstruction is meant.

In the description of the present specification, the term "lattice strain amount" as used herein means a deviation amount generated when the crystal lattice of the bulk layer 33 in fig. 22 is compared with the crystal lattice of the strained layer, and is simply a numerical value representing a ratio, and is expressed as "%".

The lattice strain below the surface of the SiC wafer 20 can be determined by comparing it with a reference lattice serving as a reference. As a means for measuring the lattice strain, for example, SEM-EBSD method can be used. The SEM-EBSD method is a method capable of performing strain measurement of minute regions based on a Kikuchi-line Diffraction pattern obtained by Electron beam backscattering in a Scanning Electron Microscope (SEM) (Electron Back Scattering Diffraction: EBSD). In this method, the amount of lattice strain can be determined by comparing the diffraction pattern of the reference lattice with the diffraction pattern of the measured lattice.

As the reference lattice, for example, a reference point R is set in a region where lattice strain is not considered to occur. That is, it is desirable that the reference point R is arranged in the region of the bulk layer 33 in fig. 22. Generally, the depth of the affected layer 30 is determined to be about 10 μm. Therefore, the reference point R may be set at a position where the depth is considered to be sufficiently deeper than the affected layer 30, and is about 20 μm to 30 μm.

Next, the diffraction pattern of the crystal lattice at the reference point R is compared with the diffraction pattern of the crystal lattice of each measurement region measured at a pitch of the order of nanometers. Thereby, the lattice strain amount of each measurement region with respect to the reference point R can be calculated.

Although the reference point R, which is considered not to cause lattice strain, is set as the reference lattice, it is needless to say that the reference point R may be based on an ideal lattice of single crystal SiC or a lattice occupying most (for example, more than half) of the lattice in the measurement region plane.

As a method for determining the amount of lattice strain below the surface of the SiC wafer 20, a general stress measurement method can be used, and examples thereof include raman spectroscopy, X-ray diffraction, and electron beam diffraction.

The amount of lattice strain of the crystal lattice under the surface of the SiC wafer 20 of the present invention with respect to the reference crystal lattice is preferably 0.01% or less, more preferably 0.005% or less, and still more preferably 0.001% or less.

In this way, since the lattice strain amount is 0.01% or less, it is possible to suppress occurrence of defects due to lattice strain in the subsequent device manufacturing steps, and it is possible to provide a higher quality SiC wafer 20.

Further, since the lattice strain amount is 0.01% or less, it is found that stress hardly occurs in the SiC wafer 20 and even a strained layer which is difficult to remove in the work-affected layer is removed.

The thickness of the SiC wafer 20 (wafer thickness) is preferably 1mm or less, more preferably 500 μm or less, and still more preferably 50 μm to 350 μm.

Even if the SiC wafer 20 is set to such a thin thickness, the rear surface 22 is processed into a pearskin surface, and therefore, the detection rate of the optical sensor can be improved.

Desirably, the external transmittance of visible light including the interface of the SiC wafer 20 is preferably 25% or less. The optical sensor of the SiC wafer 20 having such an external transmittance has a high detection rate, and detection errors in the device manufacturing steps can be suppressed.

In the description of the present specification, when referring to the external transmittance, it means a ratio of transmitting inside the SiC wafer 20 when electromagnetic waves having a wavelength of 300nm to 1500nm are irradiated to the main surface 21 or the back surface 22 of the SiC wafer.

Further, the SORI of the SiC wafer according to the present invention does not change when heated in a temperature range of 1500 ℃ to 2000 ℃. That is, since the work-affected layer 30 is removed in the entire region of the SiC wafer 20, warpage due to the work-affected layer 30 does not occur at the time of subsequent device manufacturing steps.

Note that "SORI value does not change" in the present specification means that there is no change in the SORI value due to the work-affected layer 30. For example, the variation in the value of SORI caused by lattice strain or damage or the like introduced in device manufacturing steps after an epitaxial growth step or an ion implantation step or the like is not included.

In addition, the SiC wafer 20 according to the present invention removes the work-affected layer 30 not only on the principal surface 21 and the back surface 22 but also in the outer peripheral portion 23, the orientation flat 24, the notch portion such as the notch, and the imprint portion 25, which are difficult to machine. Therefore, defects and the like generated by processing the altered layer 30 in the subsequent device manufacturing step can be suppressed.

Further, the SiC wafer 20 according to the present invention can also solve the first problem and the second problem described above at the same time.

The method for producing the SiC wafer 20 of the present invention is not particularly limited, and it is preferably produced by the production method of the present invention described later. The production method of the present invention will be explained below.

Method for producing SiC wafer

Hereinafter, a method for producing a SiC wafer according to the present invention will be described in more detail with reference to fig. 1 to 7. The drawings illustrate preferred embodiments. However, it can be implemented in many different ways and is not limited to the embodiments described in this specification.

In addition, it is considered useful in understanding the present invention as compared with the conventional manufacturing steps of SiC wafers. Accordingly, with reference to fig. 24 to 27 as appropriate, the respective steps in the method for producing an SiC wafer of the present invention will be described while being compared with the respective steps in the conventional method for producing an SiC wafer.

The following describes a method for producing an SiC wafer according to the present invention, which solves the first to fifth problems, in accordance with the procedure shown in fig. 1 to 7.

< method for producing SiC wafer to solve the first problem >

Fig. 1 to 3 are manufacturing steps of a SiC wafer solving the first problem.

The method for manufacturing a SiC wafer of the present invention for solving the first problem includes: an ingot shaping step (step S11) of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot 10; a crystal orientation forming step (step S12) of forming a cutout portion at a part of the outer periphery to be a mark indicating the crystal orientation of the ingot 10; a slicing step (step S13) of slicing and processing the ingot 10 into a thin disc-shaped SiC wafer 20; a pearskin-surface processing step (step S141) of forming at least the back surface 22 of the SiC wafer 20 into a pearskin surface; an imprint forming step (step S15) of forming an imprint section 25; a chamfering step (step S16) of chamfering the outer peripheral portion 23; an etching step (step S21) of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure; and a mirror finishing step (step S31) of forming a mirror surface on the main surface 21 of the SiC wafer 20.

In addition, the ingot shaping step S11 to the chamfering step S16 are wafer shape forming steps S10, the etching step S21 is a work-altered layer removing step S20, and the mirror-finishing step S31 is a mirror-polishing step S30.

Hereinafter, each step will be described.

(1) Ingot shaping step

Ingot shaping step 11 is a step of processing a block of single crystal SiC grown by crystal into ingot 10 of cylindrical shape. The ingot 10 is generally processed such that the length direction of the cylinder is the <0001> direction.

In the manufacturing method of the SiC wafer of the present invention, the work-affected layer 30 introduced in the ingot shaping step S11 can be removed by combining with the etching step S21 as a subsequent step.

(2) Crystal orientation shaping step

The crystal orientation shaping step S12 is a step of forming a notched portion at a part of the outer periphery of the ingot to be a mark indicating the crystal orientation of the ingot 10 formed in the ingot shaping step S11. The notch may be a plane (orientation flat)24 parallel to the <11-20> direction, a groove (notch) provided at both ends of the <11-20> direction, or the like, and may be formed so as to specify the crystal orientation of the single crystal SiC.

In the method for manufacturing a SiC wafer of the present invention, the work-affected layer 30 introduced in this crystal orientation forming step S12 can be removed by combining with the etching step S21 as a subsequent step.

(3) Slicing step

The slicing step S13 is a step of slicing the ingot 10 to obtain a thin disc-shaped SiC wafer 20.

As the slicing means of the slicing step S13, the following and the like can be exemplified: multi-wire saw slicing of slicing the ingot 10 at predetermined intervals by reciprocating a plurality of wires; an electric discharge machining method for intermittently generating plasma discharge to cut off the workpiece; cutting with laser light is performed by irradiating and condensing laser light on the ingot 10 to form a layer serving as a base point of cutting.

In the method for manufacturing a SiC wafer of the present invention, the work-affected layer 30 introduced in this slicing step S13 can be removed by combining with the etching step S21 as a subsequent step. In particular, the work-affected layer 30 introduced into the surface as the device-generated surface becomes a cause of lowering the yield in the device manufacturing step, and thus complete removal is desirable.

(4) Processing step of pear peel noodles

The peaked surface processing step S141 is a step of forming a peaked surface at least at the back surface 22 of the SiC wafer 20. As the pear peel noodle processing means in the pear peel noodle processing step S141, conventional means capable of forming pear peel noodles can be used, and examples thereof include: a sand blast process of spraying a fine granular grinding material to a surface of a wafer using air compressed by a compressor; fixed abrasive grain processing (grinding and the like) in which processing is performed using a grinding stone in which abrasive grains are embedded in a binder; free abrasive machining (grinding and polishing, etc.) in which machining is performed while fine abrasive grains are driven to a surface plate. More preferably, fixed abrasive grain processing and free abrasive grain processing are preferably used, which can simultaneously perform planarization, i.e., removal of "waviness" introduced into the SiC wafer 20 in the slicing step S13.

The processing method and processing conditions in the processing step S141 for the jacket surface, which are preferable in the method for producing a SiC wafer according to the present invention, and the properties of abrasive grains will be described below.

(4-1) processing method

As a preferable processing method in the pear skin surface processing step S141, free abrasive grain processing (grinding and polishing or the like) in which fine abrasive grains are processed while being driven to a surface plate is preferably used. Further, it is desirable to drop the abrasive grains as a mixed liquid (slurry) mixed with water or a dispersant. As the processing apparatus used in this step, a general-purpose processing apparatus used in conventional free abrasive processing can be used. The processing may be performed on both sides simultaneously or may be performed on one side.

In the pear skin surface processing step S141, it is preferable that the SiC wafer 20 is processed while grinding abrasive grains. That is, when the average abrasive grain diameter before the processing in the pear skin surface processing step S141 and the average abrasive grain diameter after the processing are compared, it is desirable that the abrasive grain diameter is reduced after the processing.

Here, the average abrasive grain diameter of the abrasive grains used in the pear skin surface processing step S141 affects the processing speed. More specifically, the following relationship exists: in the case of using large abrasive grains, a large machining speed can be achieved, and in the case of using small abrasive grains, the machining speed becomes small.

Therefore, if the peaked skin surface processing step S141 is executed while grinding abrasive grains, the surface of the SiC wafer 20 can be quickly processed at a large processing speed at the start stage of the peaked skin surface processing step S141. On the other hand, as the machining proceeds and the abrasive grains become smaller, the machining speed gradually becomes smaller, fine machining of the surface of the SiC wafer 20 can be achieved at the final stage of the step, and the roughness of the pearskin surface introduced into the surface of the SiC wafer is suppressed from becoming excessively large.

By performing the etching step S21 on the thus formed peaked surface, the SiC wafer 20 having a peaked surface suitable for the device manufacturing step can be manufactured.

In addition, by using the abrasive grains having brittleness, which will be described later, the invention of the aspect of executing the pear skin surface processing step S141 while grinding the abrasive grains can be implemented.

The invention of the aspect of executing the pear peel finish processing step S141 while grinding abrasive grains can be implemented under the processing conditions in the pear peel finish processing step S141 to be described later.

In the embodiment in which the pear skin surface processing step S141 is performed while grinding abrasive grains, the average abrasive grain diameter of the abrasive grains before processing is preferably 20 μm or more, and more preferably 40 μm or more.

By using abrasive grains having an average abrasive grain diameter in the above range in a state before processing, rapid processing can be performed at the start stage of the pear skin surface processing step S141.

In the method for producing a SiC wafer according to the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less are used at least at the beginning of the pear front surface processing step S141.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used to the above range at the beginning of the jacket surface processing step S141, the depth of the process-altered layer 30 introduced into the SiC wafer 20 by the jacket surface processing step S141 can be reduced.

On the other hand, it is preferable that the pear skin surface processing step S141 is performed while grinding abrasive grains so that the average abrasive grain diameter after processing is preferably less than 20 μm, more preferably 10 μm or less.

By performing the pyricularia surface processing step S141 while grinding the abrasive grains so that the average abrasive grain diameter after processing is within the above range, the roughness of the pyricularia surface introduced into the SiC wafer 20 can be reduced, and a surface state suitable for the SiC wafer 20 provided to the etching step S21 described later can be achieved.

In the method for producing a SiC wafer of the present invention, it is preferable to use abrasive grains having an average abrasive grain diameter of preferably 0.5 μm or more, more preferably 1 μm or more, at least in the final stage of the pear skin surface processing step S141.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the pear peel surface processing step S141 within the above range, the surface of the SiC wafer 20 can be efficiently processed.

A specific example of the case where the pear skin surface processing step S141 is performed while grinding abrasive grains will be described below.

B having an average abrasive grain size of 40 μm was used₄C abrasive grain, under a working pressure of 150g/cm²The rind surface processing step S141 was performed for a processing time of 20 minutes, and the rind surface equivalent to that of a conventional Si wafer was formed by performing the etching step S21 described later. In this case, the average abrasive grain size after the processing in the pear skin surface processing step S141 is 10 μm or less. The average processing speed obtained by dividing the processing depth 20 μm of the SiC wafer 20 in this step by the processing time was 1 μm/min.

(4-2) Properties of abrasive grains

In the method for manufacturing a SiC wafer of the present invention, it is desirable that the processing be performed while grinding the abrasive grains in the processing step S141 for the jacket surface in the free abrasive grain method. That is, the abrasive grains used in the present invention are preferably brittle enough to be easily crushed as free abrasive grains.

More specifically, it is preferable to use abrasive grains composed of a material satisfying the following brittleness condition.

(brittle condition) when the working pressure is 150g/cm²In the case of using abrasive grains adjusted to have an average abrasive grain size of 40 μm, in the case of performing simultaneous pear skin surface processing on both surfaces of the surface of the SiC wafer with free abrasive grains, the average abrasive grain size becomes 20 μm or less after a processing time of 20 minutes.

In the pear skin surface processing step S141, abrasive grains having a modified mohs hardness of less than 15 are preferably used.

In the description of the present specification, the modified mohs hardness is a value representing a measure of the hardness of a substance with talc of 1 and diamond of 15. That is, in this step, abrasive grains having a hardness smaller than that of diamond are used. As a specific abrasive grain material, boron carbide (B) can be exemplified₄C) Silicon carbide (SiC), aluminum oxide (Al)₂O₃) And the like. In addition, as long as the abrasive grains have a modified hardness of less than 15 on the mohs scale, it is needless to say that the abrasive grains can be used.

Thus, by using abrasive grains having a hardness smaller than that of diamond, roughness of the pearskin surface can be suppressed. That is, since the diamond abrasive grains have a hardness higher than that of the SiC wafer 20 to be processed, it is difficult to crush the grains into small diameters in the step of processing the pear front surface S141, and the damage or the like is introduced to a deep position on the surface of the SiC wafer 20, thereby roughening the pear front surface.

Further, it is desirable that the abrasive grains used in this step are abrasive grains having a modified mohs hardness of 13 or more. As a specific abrasive grain material, boron carbide (B) can be exemplified₄C) Silicon carbide (SiC).

By using the abrasive grains having a modified mohs hardness of 13 or more in this way, the SiC wafer 20 can be efficiently processed. That is, by using the same or higher hardness as or than that of the SiC wafer 20 to be processed, the processing can be efficiently performed.

Among them, in view of the cost and processing speed of abrasive grains, it is desirable to use boron carbide (B)₄C) And (4) abrasive particles. I.e. boron carbide (B)₄C) The abrasive grains are inexpensive and can be processed at a higher speed and with higher efficiency than silicon carbide abrasive grains.

In addition, in the description in the present specification, when referring to the average abrasive grain diameter, it means the average grain diameter according to Japanese Industrial Standard (JIS) R6001-2: 2017.

(4-3) processing conditions

The processing pressure in the free abrasive grain processing in the pearskin surface processing step S141 is 100g/cm²～300g/cm²More preferably 150g/cm²～200g/cm²。

The number of revolutions of the surface plate in this processing is 5 to 20rpm, more preferably 10 to 15 rpm.

The processing time in this processing is 5 to 30 minutes, and more preferably 5 to 15 minutes.

Further, the waviness introduced into the SiC wafer 20 in the dicing step S13 is generally 30 μm to 50 μm on each side. In this step S141, in addition to the peeling surface processing, the SiC wafer 20 may be simultaneously flattened and processed to a depth of 30 μm to 50 μm from the main surface 21 and the back surface 22 of the SiC wafer 20 in order to remove waviness.

In addition, as a preferable embodiment of the pear skin surface processing step S141, a case of using abrasive grains having a hardness smaller than that of diamond is shown, but diamond abrasive grains may be used.

Although the free abrasive grain processing has been described as a preferred embodiment of the pear skin surface processing step S141, fixed abrasive grain processing may be employed. As the processing conditions, the following conditions can be exemplified: diamond abrasive grains having an average abrasive grain diameter of 3 to 30 μm are used, the grindstone rotation speed is 1000 to 1500rpm, the cutting pitch is 1 to 3 μm, the front-rear feed is 150 to 250 m/min, the left-right feed is 15 to 25 m/min, and the machining speed is 50 to 150 μm/hr.

In addition, as the machining device, a general-purpose machining device used in conventional fixed abrasive machining can be used.

Further, as the peaked skin surface processing step S141, a flattening step S17 (see fig. 24) of a conventional method which is conventionally performed can also be adopted.

In the present invention, the method of surface processing the main surface 21 is not limited.

After the slicing step S13, the main surface 21 may not be subjected to surface processing. After the dicing step S13, the wafer may be subjected to the subsequent etching step S21 without being flattened.

In a preferred embodiment of the present invention, the main surface 21 is subjected to a flattening step after the dicing step S13. As a processing method in the flattening step, a fixed abrasive grain method may be employed in addition to the free abrasive grain method. Among the processing methods in the flattening step, the free abrasive grain method is particularly preferable.

As for the embodiment in which the main surface 21 is subjected to surface processing by the free abrasive grain method, the description of the free abrasive grain processing method described as the preferred embodiment of the pear peel surface processing step S141 can be applied as it is.

In the case where the split-abrasive-type pear skin surface processing is performed on the back surface 22 in the pear skin surface processing step S141, the main surface 21 may be flattened by the split-abrasive-type method under the same conditions as the above, or the main surface 21 may be flattened by a different processing method from that of the back surface 22.

In a preferred embodiment of the method for manufacturing a SiC wafer of the present invention, the method includes an imprint forming step S15 and a chamfering step S16 (see fig. 1 and 3).

(5) Imprint forming step

The imprint forming step S15 is a step of irradiating the back surface 22 (or the main surface 21) of the SiC wafer 20 with laser light, converging the laser light, and selectively removing the surface of the SiC wafer 20 to form the imprinted portion 25. As the imprint forming means in the imprint forming step S15, laser processing or the like can be exemplified. The imprint section 25 includes information (specifically, characters, symbols, bar codes, and the like) for identifying the SiC wafer 20.

(6) Chamfering step

The chamfering step S16 is a step of chamfering the outer peripheral portion 23 of the SiC wafer 20 by machining or the like. Examples of the chamfering means in the chamfering step S16 include grinding and tape polishing. The chamfer may be a circular chamfer forming a predetermined circular arc at the outer peripheral portion 23, or a chamfer obliquely cut at a predetermined angle.

The order of the pear skin surface processing step S141, the score forming step S15, and the chamfering step S16 is not limited to the order shown in fig. 1 and 3, and it is preferable that the pear skin surface processing step S141 is performed before the score forming step S15 and the chamfering step S16.

By thus performing the peeling process S141 to remove the waviness of the wafer, the formation of the embossed portion 25 in the embossing step S15 or the determination of the chamfering position in the chamfering step S16 can be performed with high accuracy, and the homogeneity of the wafer can be improved.

Further, the order of the imprint forming step S15 and the chamfering step S16 is not particularly limited, and as shown in fig. 1 and 3, the chamfering step S16 may be performed after the imprint forming step S15. In this way, by performing the imprint forming step S15 before the chamfering step S16, the main surface 21 and the back surface 22 can be managed at an early stage, and a problem in product management is not likely to occur.

Note that the imprint forming step S15 may be performed after the chamfering step S16. In this case, variations in wafer diameter can be suppressed, and the formation position of the imprint portion 25 can be determined with high accuracy.

(7) Etching step

The etching step S21 is a step of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure. More specifically, this step is a step of bringing the pear peel face introduced into the SiC wafer 20 in the previous step into a state (including waviness, irregularities, roughness, and the like) preferable for the device manufacturing step by heating and etching under Si vapor pressure.

The method for manufacturing a SiC wafer of the present invention has a significant effect that by combining the divot surface processing step S141 and the etching step S21, a divot surface preferable for the device manufacturing step can be formed at least at the back surface 22 of the SiC wafer 20 as a difficult-to-process material.

In addition, the etching step S21 of heating and etching under Si vapor pressure can remove the work-affected layer 30 introduced into the SiC wafer 20 in the previous step. Therefore, it is preferable that the etching step S21 is performed after the wafer shape forming step including the pearskin surface processing step S141, the imprint forming step S15, and the chamfering step S16, as shown in fig. 1 and 3. This can remove the work-affected layer 30 drawn into the periphery 23, the orientation flat 24, and the periphery of the scribe portion 25 in addition to the main surface 21 and the back surface 22, and can contribute to the improvement of the quality of the SiC wafer 20.

On the other hand, as shown in fig. 24 and 25, in the rough grinding step S22 and the finish grinding step S23 performed by the conventional SiC wafer manufacturing method, the work-affected layer 30 introduced to the periphery of the outer peripheral portion 23, the orientation flat 24, and the engraved portion 25 cannot be removed, thereby becoming a cause of deterioration in the quality of the SiC wafer 20.

The method for producing an SiC wafer of the present invention has a significant effect that by performing the etching step S21 after the ingot shaping step S11 to the imprint forming step S15, the work-affected layer 30, which has been introduced to the periphery of the outer peripheral portion 23, the orientation flat 24, and the imprint portion 25 and has been unable to be processed so far, can be removed in addition to the main surface 21 and the back surface 22, and can contribute to the high quality of the SiC wafer 20.

In the etching step S21 employed in the method for producing an SiC wafer of the present invention, both surfaces can be etched simultaneously, and thus the wafer is not warped by the tayman (Twyman) effect.

In the etching step S21, it is desirable that each surface of the SiC wafer 20 is etched, and the etching is preferably 0.5 μm or more, more preferably 1 μm or more.

By setting the etching amount within the above range, burrs and the like generated in the pearskin surface processing step S141 are removed, whereby a more preferable pearskin surface can be formed.

In the etching step S21, the arithmetic mean roughness Ra and the maximum height Rz of the pearskin surface can be reduced as the etching is performed (as the etching amount is increased). That is, the etching step S21 includes a roughness adjusting step of adjusting the roughness of the pearskin surface by controlling the etching amount.

This has a significant effect that a peaked surface having a desired roughness can be formed on at least the back surface 22 of the SiC wafer 20 as a material difficult to process.

Specifically, each surface of the SiC wafer 20 may be etched in the etching step S21, and the etching is preferably 3 μm or more, more preferably 6 μm or more, further preferably 9 μm or more, further preferably 10 μm or more, and further preferably 12 μm or more.

By setting the etching amount within the above range, the arithmetic average roughness Ra and the maximum height Rz of the pearskin surface can be set within the preferable ranges.

The upper limit of the etching amount in the etching step S21 is not particularly limited, and the target may be preferably 100 μm or less, more preferably 80 μm or less, for each surface of the SiC wafer 20.

Further, it is desirable that the etching amount in the etching step S21 is preferably 10 μm or less, more preferably 6 μm or less, and further preferably 3 μm or less, from the viewpoint of reducing the material loss.

The etching step S21 will be described in more detail below.

First, an example of the apparatus configuration used for the Si vapor pressure etching will be described with reference to fig. 4. Next, an etching mechanism and etching conditions for the Si vapor pressure etching will be described.

(7-1) device Structure

In this step, as shown in fig. 4, it is preferable to use an apparatus having: a crucible 40 for accommodating the SiC wafer 20; and a high temperature vacuum furnace 50 capable of heating the crucible 40.

The crucible 40 has: an upper container 41; a lower container 42 fittable with the upper container 41; and a support table 43 that supports the SiC wafer 20. The wall surface (upper surface, side surface) of the upper container 41 and the wall surface (side surface, bottom surface) of the lower container 42 are formed of a plurality of layers, and have a tantalum layer (Ta) and a tantalum carbide layer (TaC and Ta) in this order from the outer side toward the inner space side₂C) And a tantalum silicide layer (TaSi)₂Or Ta₅Si₃Etc.).

The tantalum silicide layer is heated to supply Si into the internal space. Further, since the crucible 40 includes the tantalum layer and the tantalum carbide layer, the ambient C vapor can be taken in. This makes it possible to generate a high-purity Si atmosphere in the internal space during heating. Instead of providing the tantalum silicide layer, solid Si or the like may be disposed in the internal space. In this case, solid Si sublimates during heating, and a high-purity Si atmosphere can be generated in the internal space.

The support table 43 can support so that both the main surface 21 and the back surface 22 of the SiC wafer 20 are exposed.

The high-temperature vacuum furnace 50 has: a main heating chamber 51, a preheating chamber 52, and a moving table 53 capable of moving the crucible 40 from the preheating chamber 52 to the main heating chamber 51. The main heating chamber 51 can heat the SiC wafer 20 to a temperature of 1000 ℃ or higher and 2300 ℃ or lower. The preheating chamber 52 is a space for preheating the SiC wafer 20 before heating it in the main heating chamber 51.

A valve 54 for forming a vacuum, a valve 55 for injecting an inert gas, and a vacuum gauge 56 are connected to the main heating chamber 51. The vacuum forming valve 54 can adjust the degree of vacuum in the main heating chamber 51. The inert gas injection valve 55 can adjust the pressure by introducing an inert gas (for example, Ar gas) into the main heating chamber 51. The vacuum gauge 56 may measure the degree of vacuum within the main heating chamber 51.

A heater 57 is provided inside the main heating chamber 51. A heat reflecting metal plate (not shown) is fixed to the side wall and the ceiling of the main heating chamber 51, and the heat of the heater 57 is reflected toward the substantially central portion of the main heating chamber 51.

This makes it possible to heat the SiC wafer 20 strongly and uniformly and to raise the temperature to a temperature of 1000 ℃ to 2300 ℃. The heater 57 may be, for example, a resistance heating type heater or a high-frequency induction heating type heater.

(7-2) etching mechanism

The SiC wafer 20 is stored in a crucible 40, and heated in a high-temperature vacuum furnace 50 at a high purity Si vapor pressure in a temperature range of 1500 ℃ to 2200 ℃. By heating the SiC wafer 20 under this condition, the surface is etched. The outline of this etching is shown in the following 1) to 4).

1)SiC(s)→Si(v)I+C(s)

2)Ta_xSi_y→Si(v)II+Ta_x’Si_y’

3)2C(s)+Si(v)I+II→SiC₂(v)

4)C(s)+2Si(v)I+II→Si₂C(v)

1) Description of (1): the SiC wafer 20(SiC (s)) is heated under SiC vapor pressure, whereby Si atoms (Si (v) I) are detached from SiC by thermal decomposition.

2) Description of (1): from a tantalum silicide layer (Ta)_xSi_y) Si vapor (Si (v) II) is provided.

3) And 4) description of: the C (s)) remaining after the Si atoms (Si (v) I) are desorbed by thermal decomposition are reacted with Si vapor (Si (v) I and Si (v) II) to form Si₂C or SiC₂Etc. and sublimed.

The reaction of 1) to 4) is continued, and as a result, etching is performed.

(7-3) etching conditions

The heating temperature in the Si vapor pressure etching is 1500 to 2200 ℃, more preferably 1800 to 2000 ℃.

The processing rate (etching rate) in this processing is 0.1 μm/min to 10 μm/min.

The degree of vacuum of the main heating chamber 51 in this processing is 10^-5Pa to 10Pa, more preferably 10Pa^-3Pa～1Pa。

The inert gas used in this process is Ar, and the degree of vacuum is adjusted by introducing the inert gas.

The processing time in this processing is not particularly limited, and any time can be adopted that matches the desired etching amount. For example, when the etching amount is set to 3 μm at a processing speed of 1 μm/min, the processing time is 3 minutes.

In addition, a finish grinding step S23 and a finish polishing step may be included before the etching step S21. In this way, by performing the finish grinding step S23 and the finish polishing step before the etching step S21, the flatness of the SiC wafer 20 after etching can be improved.

(8) Mirror finishing step

As the mirror finishing step S31, a Chemical Mechanical Polishing (CMP) process in which the mechanical action of the polishing pad and the chemical action of the slurry are used together for polishing can be exemplified. This chemical mechanical polishing is a step of processing the main surface 21 of the SiC wafer 20 into a mirror surface having a surface state preferable for the device manufacturing step (the two-dot chain line portion in fig. 3).

In addition, in the conventional SiC wafer manufacturing method, Chemical Mechanical Polishing (CMP) is performed on the main surface 21 and the rear surface 22, and the mirror surface is formed (the two-dot chain line portion of fig. 25).

The present process may employ a general-purpose type processing apparatus used in a conventional chemical mechanical polishing process, and the processing conditions may be set within a range generally performed by those skilled in the art.

< method for producing SiC wafer to solve the second problem >

Next, the steps of manufacturing the SiC wafer of the present invention for solving the second problem will be described in detail with reference to fig. 2, 3, and 5. In the manufacturing process of the SiC wafer of the present invention for solving the second problem, the same reference numerals are given to the same components as those in the manufacturing process of the SiC wafer of the present invention for solving the first problem, and the description thereof is simplified.

The method for manufacturing a SiC wafer of the present invention for solving the second problem includes: an ingot shaping step (step S11) of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot 10; a crystal orientation shaping step (step S12) of forming a notch at a part of the outer periphery to be a mark indicating the crystal orientation of the ingot 10; a slicing step (step S13) of slicing and processing the ingot 10 into a thin disc-shaped SiC wafer 20; a planarization step (step S142) of planarizing the SiC wafer 20; an imprint forming step (step S15) of forming an imprint section 25; a chamfering step (step S16) of chamfering the outer peripheral portion 23; an etching step (step S21) of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure; and a mirror finishing step (step S31) of forming a mirror surface on the main surface 21 of the SiC wafer 20.

In addition, the ingot shaping step S11 to the chamfering step S16 are wafer shape forming steps S10, the etching step S21 is a work-altered layer removing step S20, and the mirror-finishing step S31 is a mirror-polishing step S30.

(9) Planarization step

The flattening step S142 is a step of removing the waviness introduced into the SiC wafer 20 in the slicing step S13. The processing method and processing conditions used in the flattening step S142, and the properties of the abrasive grains will be described below.

(9-1) processing method

As a preferable processing method for the planarization step S142, it is preferable to use: fixed abrasive grain processing (grinding, etc.) in which abrasive grains are embedded in a binder and processed by a grinding stone, or free abrasive grain processing (grinding, etc.) in which fine abrasive grains are driven and processed on a surface plate. Further, it is desirable to drop the abrasive grains as a mixed liquid (slurry) mixed with water or a dispersant. As the processing apparatus used in this step, a general-purpose processing apparatus used in conventional fixed abrasive grain processing and free abrasive grain processing can be used. The processing may be performed on both sides simultaneously or may be performed on one side.

In the flattening step S142, the cladding surface formation may be performed simultaneously with the formation of the cladding surface on at least the back surface 22 of the SiC wafer 20.

In the flattening step S142, it is preferable that the SiC wafer 20 is processed while grinding abrasive grains. That is, it is desirable that when the average abrasive particle diameter before processing and the average abrasive particle diameter after processing in the flattening step S142 are compared, the abrasive particles are crushed after processing, and the abrasive particle diameter is thinned.

Here, the average abrasive grain diameter of the abrasive grains used in the flattening step S142 affects the machining speed. More specifically, the following relationship exists: in the case of using large abrasive grains, a large machining speed can be achieved, and in the case of using small abrasive grains, the machining speed becomes small.

Therefore, if the flattening step S142 is performed while grinding abrasive grains, the surface of the SiC wafer 20 can be quickly machined at a large machining speed at the start stage of the flattening step S142. On the other hand, as the machining progresses and the abrasive grains become smaller, the machining speed gradually becomes smaller, and at the final stage of the step, it is possible to achieve fine machining of the surface of the SiC wafer 20 and to suppress the roughness of the pearskin surface introduced into the surface of the SiC wafer from becoming excessively large.

By performing the etching step S21 on the thus formed peaked surface, the SiC wafer 20 having a peaked surface suitable for the device manufacturing step can be manufactured.

In addition, by using the abrasive grains having brittleness, which will be described later, the invention of the embodiment in which the flattening step S142 is performed while grinding the abrasive grains can be performed.

The invention of the embodiment in which the flattening step S142 is performed while grinding abrasive grains can be performed under the processing conditions in the flattening step S142 described later.

In the embodiment in which the flattening step S142 is performed while grinding the abrasive grains, the average abrasive grain diameter of the abrasive grains before processing is preferably 20 μm or more, and more preferably 40 μm or more.

By using abrasive grains having an average abrasive grain diameter in the above range in a state before machining, rapid machining can be performed at the start stage of the flattening step S142.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less are used at least in the initial stage of the flattening step S142.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the initial stage of the flattening step S142 within the above range, the depth of the work-affected layer 30 introduced into the SiC wafer 20 by the flattening step S142 can be reduced.

On the other hand, it is preferable that the flattening step S142 is performed while grinding abrasive grains so that the average abrasive grain diameter after processing is preferably less than 20 μm, more preferably 10 μm or less.

By performing the flattening step S142 while grinding abrasive grains so that the average abrasive grain diameter after processing is within the above range, the roughness of the pear peel surface introduced into the SiC wafer 20 can be reduced, and a surface state suitable for the SiC wafer 20 provided to the etching step S21 described later can be achieved.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 0.5 μm or more, more preferably 1 μm or more are used at least in the final stage of the flattening step S142.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the flattening step S142 within the above range, the surface of the SiC wafer 20 can be efficiently machined.

A specific example of the case where the flattening step S142 is performed while grinding abrasive grains will be described below.

B having an average abrasive grain size of 40 μm was used₄C abrasive grain, under a working pressure of 150g/cm²The planarization step S142 is performed for a processing time of 20 minutes, and the etching step S21 described later is performed, thereby forming a peaked surface equivalent to a conventional Si wafer. In this case, the average abrasive grain diameter after the processing in the flattening step S142 is 10 μm or less. The average processing speed obtained by dividing the processing depth 20 μm of the SiC wafer 20 in this step by the processing time was 1 μm/min.

(9-2) Properties of abrasive grains

In the method for manufacturing a SiC wafer of the present invention, it is desirable that the flattening step S142 in the free abrasive grain method performs processing while grinding abrasive grains. That is, the abrasive grains used in the present invention are preferably brittle enough to be easily crushed as free abrasive grains.

More specifically, it is preferable to use abrasive grains composed of a material satisfying the following brittleness condition.

(brittle condition) when the working pressure is 150g/cm²In the case of using abrasive grains adjusted to have an average abrasive grain size of 40 μm, when both surfaces of the surface of the SiC wafer are simultaneously flattened as free abrasive grains, the average abrasive grain size becomes 20 μm or less after a lapse of 20 minutes from the machining time.

In the flattening step S142, abrasive grains having a modified mohs hardness of less than 15 are preferably used.

Thus, by using abrasive grains having a hardness smaller than that of diamond, the roughness of the pearskin surface can be suppressed. That is, since the diamond abrasive grains have extremely high hardness as compared with the SiC wafer 20 to be processed, it is difficult to crush into small diameters in the process of the flattening step S142, and the damage or the like is introduced to a deep position on the surface of the SiC wafer 20, thereby roughening the pear front surface.

Further, it is desirable that the abrasive grains used in this step are abrasive grains having a modified mohs hardness of 13 or more. As a specific abrasive grain material, boron carbide (B) can be exemplified₄C) Silicon carbide (SiC).

By using the abrasive grains having a modified mohs hardness of 13 or more in this way, the SiC wafer 20 can be efficiently processed. That is, by using the same or higher hardness as or than that of the SiC wafer 20 to be processed, the processing can be efficiently performed.

Among them, in view of the cost and processing speed of abrasive grains, it is desirable to use boron carbide (B)₄C) And (4) abrasive particles. I.e. boron carbide (B)₄C) The abrasive grains are available at low cost, and can be processed at a higher speed and with higher efficiency than silicon carbide abrasive grains.

(9-3) processing conditions

The processing pressure in the free abrasive grain processing in the flattening step S142 is 100g/cm²～300g/cm²More preferably 150g/cm²～200g/cm²。

The number of revolutions of the surface plate in this processing is 5 to 20rpm, more preferably 10 to 15 rpm.

The processing time in this processing is 5 to 30 minutes, and more preferably 5 to 15 minutes.

Further, the waviness introduced into the SiC wafer 20 in the slicing step S13 is generally 30 μm to 50 μm on each side. In the flattening step S142, the SiC wafer 20 may be flattened at the same time, and the main surface 21 and the back surface 22 of the SiC wafer 20 may be processed to a depth of 30 μm to 50 μm in order to remove waviness.

In addition, as a preferable embodiment of the flattening step S142, a case of using abrasive grains having a hardness smaller than that of diamond is shown, but diamond abrasive grains may be used.

Although the free abrasive grain processing has been described as a preferred embodiment of the flattening step S142, fixed abrasive grain processing may be employed. As the processing conditions, the following conditions can be exemplified: diamond abrasive grains having an average abrasive grain diameter of 3 to 30 μm are used, the grindstone rotation speed is 1000 to 1500rpm, the cutting pitch is 1 to 3 μm, the front-rear feed is 150 to 250 m/min, the left-right feed is 15 to 25 m/min, and the machining speed is 50 to 150 μm/hr.

In addition, as the machining device, a general-purpose machining device used in conventional fixed abrasive machining can be used.

In a preferred embodiment of the method for manufacturing a SiC wafer of the present invention, the method includes an imprint forming step S15 and a chamfering step S16 (see fig. 3 and 5).

(7) Etching step

The etching step S21 is a step of removing the process-altered layer 30 introduced into the SiC wafer 20 in the previous step by etching the surface of the SiC wafer 20 by heating under Si vapor pressure, as in the previous manufacturing step of the SiC wafer of the present invention to solve the first problem.

That is, it is preferable that the etching step S21 is performed after: an ingot shaping step S11 of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot 10; a crystal orientation forming step S12 of forming a notched portion indicating the crystal orientation at a part of the outer periphery of the ingot 10; a slicing step S13 of slicing the ingot 10 to obtain a thin disc-shaped SiC wafer 20; an imprint forming step S15 of selectively removing the surface of the SiC wafer 20 to form an imprint portion 25; and a chamfering step S16 of chamfering the outer peripheral portion 23 of the SiC wafer 20. This can remove the work-affected layer 30 drawn into the periphery 23, the orientation flat 24, and the periphery of the scribe portion 25 in addition to the main surface 21 and the back surface 22, and can contribute to the improvement of the quality of the SiC wafer 20.

On the other hand, as shown in fig. 24 and 25, in the rough grinding step S22 and the finish grinding step S23 performed by the conventional SiC wafer manufacturing method, the work-affected layer 30 introduced to the periphery of the outer peripheral portion 23, the orientation flat 24, and the engraved portion 25 cannot be removed, thereby becoming a main cause of deterioration in the quality of the SiC wafer 20.

The method for producing an SiC wafer of the present invention has a significant effect that by performing the etching step S21 after the ingot shaping step S11 to the chamfering step S16, the work-affected layer 30 introduced into the periphery of the heretofore unmachined outer peripheral portion 23, the orientation flat 24, and the imprint portion 25 can be removed in addition to the main surface 21 and the back surface 22, and can contribute to the high quality of the SiC wafer 20.

In the etching step S21 employed in the method for producing an SiC wafer of the present invention, both surfaces can be etched simultaneously, and thus the wafer is not warped by the tayman (Twyman) effect.

The etching step S21 is a step of heating and etching the rind surface introduced into the SiC wafer 20 in the flattening step S142 under Si vapor pressure to obtain a state (including waviness, uneven shape, roughness, and the like) preferable for the device manufacturing step.

The method for producing a SiC wafer of the present invention has a significant effect that a pear skin surface preferable for a device production step, which does not have the work-affected layer 30, can be formed at the SiC wafer 20 as a material difficult to machine by combining the flattening step S142 and the etching step S21.

In the etching step S21, it is desirable that each surface of the SiC wafer 20 is etched, and the etching is preferably 0.5 μm or more, more preferably 1 μm or more.

By setting the etching amount within the above range, burrs and the like generated in the flattening step S142 are removed, whereby a more preferable pear skin surface can be formed.

In the etching step S21, the arithmetic mean roughness Ra and the maximum height Rz of the pearskin surface can be reduced as the etching is performed (as the etching amount is increased). That is, the etching step S21 includes: and a roughness adjusting step of adjusting the roughness of the pearskin surface by controlling the etching amount. This has a significant effect that a peaked surface having a desired roughness can be formed on at least the back surface 22 of the SiC wafer 20 as a material difficult to process.

Specifically, in the etching step S21, each surface of the SiC wafer 20 may be etched, and the etching is preferably 3 μm or more, more preferably 6 μm or more, further preferably 9 μm or more, further preferably 10 μm or more, and further preferably 12 μm or more.

By setting the etching amount within the above range, the arithmetic average roughness Ra and the maximum height Rz of the pearskin surface can be set within the preferable ranges.

< methods for producing SiC wafers to solve the third to fifth problems >

Hereinafter, the steps of manufacturing the SiC wafer of the present invention for solving the third to fifth problems will be described in detail with reference to fig. 2, 6, and 7. In the steps of manufacturing the SiC wafer of the present invention to solve the third to fifth problems, the same reference numerals are given to the same components as those in the conventional steps of manufacturing the SiC wafer of the present invention to solve the first and second problems, and the description thereof is simplified.

In general, SiC wafer 20 having thickness D is manufactured by subjecting SiC wafer 20 to the following steps (fig. 26 and 27), namely: a wafer shape forming step (step S10) for adjusting the wafer shape; a process-altered layer removal step (step S20) of reducing the process-altered layer 30 introduced into the wafer surface in the wafer shape forming step S10; and a mirror polishing step (step S30) of mirroring the wafer surface.

In the method for manufacturing a SiC wafer of the present invention, as shown in fig. 2, 6, and 7, it is preferable to adopt a mode including a wafer shape forming step S10, a work-affected layer removing step S20, and a mirror polishing step S30.

The method for producing an SiC wafer according to the present invention will be described below in accordance with the procedure of one embodiment shown in fig. 2, 6, and 7.

<1> wafer shape Forming step

In one embodiment of the present invention to solve the third to fifth problems, the wafer shape forming step S10 includes: an ingot shaping step S11 of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot 10; a crystal orientation shaping step S12 of forming a notch at a part of the outer periphery to be a mark indicating the crystal orientation of the ingot 10; a slicing step S13 of slicing and processing the ingot 10 of single crystal SiC into a thin disc-shaped SiC wafer 20; a planarization step S142 of planarizing the SiC wafer 20 using abrasive grains having a modified mohs hardness of less than 15; an imprint forming step S15 of forming an imprint portion 25; and a chamfering step S16 of chamfering the outer peripheral portion 23.

Hereinafter, each step will be described.

(1) Ingot shaping step

Ingot shaping step 11 is a step of processing a block of single crystal SiC that has been crystal-grown into a columnar ingot 10, as in the previous manufacturing step of the SiC wafer of the present invention that solves the first and second problems. The ingot 10 is generally processed such that the length direction of the cylinder is the <0001> direction.

In the manufacturing method of the SiC wafer of the present invention, strain and damage of the SiC wafer introduced in the ingot shaping step S11 can be eliminated by a combination of the flattening step S142 and the etching step S21 as subsequent steps.

(2) Crystal orientation shaping step

Crystal orientation shaping step S12 is a step of forming a notch at a part of the outer periphery to be a mark indicating the crystal orientation of ingot 10 formed in ingot shaping step S11, as in the previous manufacturing step of the SiC wafer of the present invention to solve the first and second problems. The notch may be a plane (orientation flat)24 parallel to the <11-20> direction, a groove (notch) provided at both ends of the <11-20> direction, or the like, and may be formed so as to specify the crystal orientation of the single crystal SiC.

In the method for manufacturing a SiC wafer of the present invention, strain and damage of the SiC wafer introduced in this crystal orientation shaping step S12 can be eliminated by a combination of the planarization step S142 and the etching step S21 as subsequent steps.

(3) Slicing step

As the slicing means in the slicing step S13, the following steps can be exemplified as the manufacturing steps of the SiC wafer of the present invention to solve the first and second problems described above: multi-wire saw slicing of slicing the ingot 10 at predetermined intervals by reciprocating a plurality of wires; an electric discharge machining method for intermittently generating plasma discharge to cut off the workpiece; cutting with laser light is performed by irradiating and condensing laser light on the ingot 10 to form a layer serving as a base point of cutting.

The thickness D1 of the SiC wafer 20 before processing is determined by the interval of dicing in the dicing step S13. The thickness D1 before processing is set to a thickness that takes into account the single crystal SiC (material loss) to be removed in a later step. In this way, since the pre-processing thickness D1 is set in consideration of the amount of material loss after passing through all the processing steps, specific numerical values thereof will be described after the description of all the processing steps.

(9) Planarization step

The flattening step S142 is a step of removing the waviness introduced into the SiC wafer 20 in the slicing step S13 to flatten the SiC wafer 20, as in the previous manufacturing step of the SiC wafer of the present invention to solve the second problem. The properties, processing method, and processing conditions of the abrasive grains used in the flattening step S142 will be described below.

Further, with respect to the properties of the abrasive grains, the properties of the abrasive grains corresponding to each problem will be described.

(9-1-1) Properties of abrasive grains

As shown in fig. 26, in the conventional method, diamond abrasive grains having a modified mohs hardness of 15 were used in the planarization step S17 of the conventional method.

On the other hand, a method for manufacturing a SiC wafer of the present invention for solving the third problem is characterized by comprising: a planarization step S142 (hereinafter, also referred to as diamond-free polishing) planarizes the SiC wafer 20 in the presence of abrasive grains having a modified mohs hardness of less than 15.

By using abrasive grains having a hardness of modified mohs hardness of less than 15 in this way, the work-affected layer 30 removed in the etching step S21(Si vapor pressure etching) described later can be formed thin. That is, by reducing the difference in hardness from the SiC wafer 20 as the processing object, it is possible to suppress the introduction of the damage to the deep surface of the SiC wafer 20, and to form a surface suitable for performing the Si vapor pressure etching.

Further, it is desirable that the abrasive grains used in this step are abrasive grains having a modified mohs hardness of 13 or more. As a specific abrasive grain material, boron carbide (B) can be exemplified₄C) Silicon carbide (SiC).

By using the abrasive grains having a modified mohs hardness of 13 or more in this way, the SiC wafer 20 can be efficiently cut. That is, by using the same or higher hardness as or than that of the SiC wafer 20 to be processed, the processing can be efficiently performed.

Among them, in view of the cost and processing speed of abrasive grains, it is desirable to use boron carbide (B)₄C) And (4) abrasive particles. I.e. boron carbide (B)₄C) The abrasive grains are available at low cost, and can be processed at a higher speed and with higher efficiency than silicon carbide abrasive grains.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 20 μm or more, more preferably 40 μm or more are used at least in the initial stage of the flattening step S142.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the flattening step S142 within the above range, the surface of the SiC wafer 20 can be quickly machined at a large machining speed.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less are used at least in the initial stage of the flattening step S142.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the initial stage of the flattening step S142 within the above range, the depth of the work-affected layer introduced into the SiC wafer 20 by the flattening step S142 can be reduced.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably less than 20 μm, more preferably 10 μm or less are used at least in the final stage of the flattening step S142, that is, immediately before and after the end.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the last stage of the flattening step S142 within the above range, the depth of the work-affected layer introduced into the SiC wafer 20 by the flattening step S142 can be reduced.

In the method for producing a SiC wafer of the present invention, it is preferable that abrasive grains having an average abrasive grain diameter of preferably 0.5 μm or more, more preferably 1 μm or more are used at least in the final stage of the flattening step S142.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the flattening step S142 within the above range, the surface of the SiC wafer 20 can be efficiently machined.

In the present invention, it is preferable to use abrasive grains that are brittle to the extent that they are crushed in the flattening step S142. More specifically, it is preferable to use abrasive grains composed of a material satisfying the following brittleness condition.

(brittle condition) when the working pressure is 150g/cm²When both surfaces of the surface of the SiC wafer were simultaneously planarized with the free abrasive by using abrasive grains adjusted to have an average abrasive grain size of 40 μm under the conditions (1), the average abrasive grain size became 20 μm or less after a processing time of 20 minutes.

The abrasive grains satisfying such a brittleness condition are crushed in the flattening step S142, and exhibit a property of reducing the average abrasive grain diameter.

Here, the average abrasive grain diameter of the abrasive grains used in the flattening step S142 affects the machining speed. More specifically, the following relationship exists: in the case of using large abrasive grains, a large machining speed can be achieved, whereas in the case of using small abrasive grains, the machining speed becomes smaller.

Therefore, by using abrasive grains satisfying the above-described brittleness condition, the surface of the SiC wafer 20 can be quickly processed at a large processing speed in the starting stage of the flattening step S142. On the other hand, when the machining is performed, the abrasive grains are crushed, the machining speed is gradually reduced, and in the final stage of the step, the fine machining of the surface of the SiC wafer 20 can be realized and the depth of the machining-damaged layer 30 is suppressed to the minimum.

This can shorten the time of the planarization step S142 and achieve a surface state suitable for the SiC wafer 20 to be provided to the etching step S21 described later.

As the abrasive grains satisfying such brittleness condition, the above-mentioned abrasive grains having a modified mohs hardness of less than 15 can be exemplified.

(9-1-2) Properties of abrasive grains

As shown in fig. 26, in the conventional method, diamond abrasive grains having a modified mohs hardness of 15 were used in the planarization step S17 of the conventional method. Since the diamond abrasive grains have a higher hardness than the SiC wafer 20 as the object of processing, it is difficult to crush into a small diameter during the flattening step S17 of the conventional method, resulting in introducing the work-affected layer 30 to a deep position on the surface of the SiC wafer 20.

On the other hand, in the method for manufacturing a SiC wafer of the present invention for solving the third problem, in the flattening step S142 in the free abrasive grain method, the processing is performed while grinding the abrasive grains. That is, the abrasive grains used in the present invention need to have a brittleness such that they can be easily crushed as free abrasive grains.

More specifically, it is preferable to use abrasive grains composed of a material satisfying the following brittleness condition.

(brittle condition) when the working pressure is 150g/cm²When both surfaces of the surface of the SiC wafer were simultaneously planarized with the free abrasive by using abrasive grains adjusted to have an average abrasive grain size of 40 μm under the conditions (1), the average abrasive grain size became 20 μm or less after a processing time of 20 minutes.

In the flattening step S142, abrasive grains having a modified mohs hardness of less than 15 are preferably used.

By using abrasive grains having a hardness of modified mohs hardness of less than 15 in this way, the work-affected layer 30 removed in the etching step S21(Si vapor pressure etching) described later can be formed thin. That is, by reducing the difference in hardness from the SiC wafer 20 to be processed, the introduction of the damage (i.e., the work-affected layer 30) into the deep surface of the SiC wafer 20 can be suppressed, and a surface suitable for performing the Si vapor pressure etching can be formed.

Further, it is desirable that the abrasive grains used in this step are abrasive grains having a modified mohs hardness of 13 or more. As a specific abrasive grain material, boron carbide (B) can be exemplified₄C) Silicon carbide (SiC).

By using the abrasive grains having a modified mohs hardness of 13 or more in this way, the SiC wafer 20 can be efficiently cut. That is, by using the same or higher hardness as or than that of the SiC wafer 20 to be processed, the processing can be efficiently performed.

Among them, in view of the cost and processing speed of abrasive grains, it is desirable to use boron carbide (B)₄C) And (4) abrasive particles. I.e. boron carbide (B)₄C) The abrasive grains are available at low cost, and can be processed at a higher speed and with higher efficiency than silicon carbide abrasive grains.

(9-1-3) Properties of abrasive grains

There is no limitation on the kind of abrasive grains used in the planarization step S142 of the present invention to solve the fourth and fifth problems of the present invention. It is preferable to use abrasive grains having a modified mohs hardness of less than 15 used in one embodiment of the present invention shown in fig. 6, or abrasive grains having a brittleness to the extent of being crushed in the flattening step S142, but abrasive grains having a modified mohs hardness of 15 such as diamond abrasive grains used in the flattening step S17 of the conventional method shown in fig. 26 may also be used.

In a preferred embodiment of the present invention, as shown in fig. 6, in the planarization step S142, it is preferable to use abrasive grains having a modified mohs hardness of less than 15.

By using abrasive grains having a hardness of modified mohs hardness of less than 15 in this way, the work-affected layer 30 removed in the etching step S21(Si vapor pressure etching) described later can be formed to a depth of 3 μm or less. That is, by reducing the difference in hardness from the SiC wafer 20 to be processed, the introduction of damage to the deep surface of the SiC wafer 20 can be suppressed, and a surface suitable for performing Si vapor pressure etching can be formed.

In the case of using abrasive grains having a hardness of modified mohs hardness of less than 15, it is preferable to use abrasive grains having an average abrasive grain diameter of preferably 20 μm or more, more preferably 40 μm or more, at least in the initial stage of the flattening step S142.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the flattening step S142 within the above range, the surface of the SiC wafer 20 can be quickly machined at a large machining speed.

In addition, in the case of using abrasive grains having a hardness of modified mohs hardness of less than 15, it is preferable to use abrasive grains having an average abrasive grain diameter of preferably 100 μm or less, more preferably 80 μm or less, and further preferably 60 μm or less at least in the initial stage of the flattening step S142.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the initial stage of the flattening step S142 within the above range, the depth of the work-affected layer introduced into the SiC wafer 20 by the flattening step S142 can be reduced.

Further, in the case of using abrasive grains having a hardness of modified mohs hardness of less than 15, it is preferable to use abrasive grains having an average abrasive grain diameter of preferably less than 20 μm, more preferably 10 μm or less at least at the final stage of the flattening step S142, i.e., from immediately before to the end.

By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the last stage of the flattening step S142 within the above range, the depth of the work-affected layer in the SiC wafer 20 caused by the flattening step S142 can be reduced.

Further, in the case of using abrasive grains having a hardness of modified mohs hardness of less than 15, it is preferable to use abrasive grains having an average abrasive grain diameter of preferably 0.5 μm or more, more preferably 1 μm or more, at least in the final stage of the flattening step S142.

By setting the lower limit of the average abrasive grain diameter of the abrasive grains used in the beginning of the flattening step S142 within the above range, the surface of the SiC wafer 20 can be efficiently machined.

Further, the abrasive grains used in the present invention preferably have a brittleness to the extent that they are crushed as free abrasive grains.

More specifically, it is preferable to use abrasive grains composed of a material satisfying the following brittleness condition.

(brittle condition) when the working pressure is 150g/cm²When both surfaces of the surface of the SiC wafer were simultaneously planarized with the free abrasive by using abrasive grains adjusted to have an average abrasive grain size of 40 μm under the conditions (1), the average abrasive grain size became 20 μm or less after a processing time of 20 minutes.

By performing the flattening step S142 in a free abrasive manner using abrasive grains satisfying such a brittleness condition, the depth of the introduced work-affected layer 30 can be set to 3 μm or less.

Further, in the flattening step S142, diamond abrasive grains may also be used.

In the case where diamond abrasive grains are used in the flattening step S142, it is considered that the work-affected layer 30 is introduced to a depth approximately equal to the grain diameter thereof. Therefore, in view of the removal in the subsequent work-affected layer removing step S20, it is preferable to use diamond abrasive grains having an average abrasive grain diameter of preferably 10 μm or less, more preferably 5 μm or less, and still more preferably 3 μm or less.

In this case, in the flattening step S142, a work-affected layer having a preferable form of 10 μm or less, more preferably 5 μm or less, and still more preferably 3 μm or less is introduced into the SiC wafer 20.

(9-2) processing method

As a method applicable to the flattening step S142, there are a free abrasive grain method (grinding and polishing or the like) in which fine abrasive grains are driven and processed on a surface plate, and a fixed abrasive grain method (grinding and polishing or the like) in which processing is performed using a grinding stone in which abrasive grains are embedded in a binder. More preferably, free abrasive grain means is preferably used. Further, it is desirable to drop the abrasive grains as a mixed liquid (slurry) mixed with water or a dispersant.

As the processing apparatus used in this step, a general-purpose processing apparatus used in a conventional fixed abrasive grain system and a free abrasive grain system can be used. The processing may be performed on both sides simultaneously or may be performed on one side.

In the flattening step S142, it is desirable to process the SiC wafer 20 while grinding abrasive grains. That is, it is desirable that the average abrasive grain diameter before processing and the average abrasive grain diameter after processing are compared and pulverized after processing, so that the abrasive grain diameter becomes finer.

Further, in the method for producing an SiC wafer of the present invention, the SiC wafer 20 is planarized such that the work-affected layer 30 introduced into the SiC wafer 20 in the planarization step S142 is preferably 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less.

Such a thin process-altered layer 30 may be removed by the etching step S21 as a subsequent step without additional material loss.

Therefore, by suppressing the depth of the work-affected layer 30 in the flattening step S142 to be within the above numerical range and then performing the etching step S21, the material loss can be reduced, whereby more SiC wafers 20 can be produced from one ingot 10.

In addition, as a specific means for adjusting the depth of the affected layer within the above range, the matters described in the above "properties of abrasive grains" can be applied.

In the flattening step S142, it is preferable that the SiC wafer 20 is processed while grinding abrasive grains. That is, when the average abrasive grain diameter before processing and the average abrasive grain diameter after processing in the flattening step S142 are compared, it is desirable that the abrasive grain diameter is reduced by grinding after processing.

As described above, the average abrasive grain diameter of the abrasive grains used in the flattening step S142 affects the machining speed.

Therefore, if an embodiment is employed in which the flattening step S142 is performed while grinding abrasive grains, the surface of the SiC wafer 20 can be quickly machined at a large machining speed in the initial stage of the flattening step S142. On the other hand, as the machining progresses and the abrasive grains become smaller, the machining speed gradually becomes smaller, and in the final stage of the step, the fine machining of the surface of the SiC wafer 20 can be realized, and the depth of the machining-damaged layer 30 can be suppressed to the minimum.

This can shorten the time of the planarization step S142 and achieve a surface state suitable for the SiC wafer 20 to be provided to the etching step S21 described later.

In other words, the average abrasive grain diameter of the abrasive grains used in the flattening step S142 affects the machining speed. More specifically, the following relationship exists: in the case of using large abrasive grains, a large machining speed can be achieved, and in the case of using small abrasive grains, the machining speed becomes small.

Therefore, if the flattening step S142 is performed while grinding abrasive grains, the surface of the SiC wafer 20 can be quickly machined at a large machining speed in the initial stage of the flattening step S142. On the other hand, as the machining proceeds and the abrasive grains become smaller, the machining speed gradually becomes smaller, and in the final stage of the step, fine machining of the surface of the SiC wafer 20 can be achieved, and the machining-affected layer 30 introduced into the surface of the SiC wafer is formed thin and uniform.

By performing the etching step S21 on such a thin and uniform process-altered layer 30, a high-quality SiC wafer 20 can be manufactured with less material loss.

In the flattening step S17 of the conventional method using diamond abrasive grains, the work-affected layer 30 is locally introduced deep into the surface, and does not become a work-affected layer 30 of uniform depth. Therefore, in order to remove all the work-affected layer 30 of the SiC wafer 20 in the subsequent work-affected layer removal step S20, the work-affected layer 30 is not formed, and thus the material loss amount is large.

The method for producing a SiC wafer of the present invention is advantageous in that the material loss amount is small as compared with conventional methods.

Further, in the planarization step S17 of the conventional method using diamond abrasive grains, since deep scratches are randomly generated, there is a problem in quality management.

On the other hand, in the flattening step S142 in the present invention, such scratches are difficult to generate, and thus are very advantageous in terms of quality management.

Further, by performing the flattening step S142 while grinding abrasive grains, rapid surface processing in the initial stage of the flattening step S142 and fine processing in the final stage of the step can be achieved, and thus the depth of the processing-altered layer 30 can be suppressed to the minimum.

This can shorten the time of the planarization step S142 and realize a surface state suitable for the surface of the SiC wafer 20 to be provided to the etching step S21 described later.

In addition, by using the abrasive grains having the modified mohs hardness of less than 15 described above, the invention of the aspect in which the flattening step S142 is performed while grinding the abrasive grains can be implemented.

The invention of the embodiment in which the flattening step S142 is performed while grinding abrasive grains can be performed under the processing conditions in the flattening step S142 described later.

Further, by using the aforementioned abrasive grains having brittleness, the invention of the embodiment of performing the flattening step S142 while grinding the abrasive grains can be carried out.

That is, the invention of the aspect in which the flattening step S142 is performed while grinding the abrasive grains can be implemented by using the abrasive grains having the modified mohs hardness of less than 15 or the abrasive grains having brittleness.

In the embodiment in which the flattening step S142 is performed while grinding the abrasive grains, the average abrasive grain diameter of the abrasive grains before processing is preferably 20 μm or more, and more preferably 40 μm or more.

By using abrasive grains having an average abrasive grain diameter in the above range in a state before machining, rapid machining can be performed in the initial stage of the flattening step S142.

On the other hand, it is preferable that the flattening step S142 is performed while grinding abrasive grains so that the average abrasive grain diameter after processing is preferably less than 20 μm, more preferably 10 μm or less.

By performing the flattening step S142 while grinding the abrasive grains so that the average abrasive grain diameter after machining is within the above range, the depth of the machining-affected layer 30 introduced into the SiC wafer 20 can be reduced. This makes it possible to realize a surface state suitable for the SiC wafer 20 to be supplied to the etching step S21 described later.

A specific example of the case where the flattening step S142 is performed while grinding abrasive grains will be described below.

B having an average abrasive grain size of 40 μm was used₄C abrasive grain, under a working pressure of 150g/cm²The planarization step S142 is performed under the condition that the processing time is 20 minutes, and the depth of the process-altered layer 30 of the SiC wafer 20 is about 3 μm. In this case, the average grain size after processing is 10 μm or less. The average processing speed obtained by dividing the processing depth 20 μm of the SiC wafer 20 in this step by the processing time was 1 μm/min.

(9-3) processing conditions

In the case of the free abrasive grain method in the flattening step S142, the processing pressure is 100g/cm²～300g/cm²More preferably 150g/cm²～200g/cm²。

In the case of the free abrasive grain method, the number of revolutions of the surface plate in the present processing is 5 to 20rpm, more preferably 10 to 15 rpm.

On the other hand, in the case of the fixed abrasive grain manner, the flattening step S142 may be performed under the same processing conditions as the rough grinding step S22 and the finish grinding step S23 in the conventional method. Specifically, the following conditions may be exemplified: the rotation speed of the grinding stone is 1000 rpm-1500 rpm, the cutting pitch is 1 μm-3 μm, the front and back feeding is 150 m/min-250 m/min, the left and right feeding is 15 m/min-25 m/min, and the processing speed is 50 μm/h-150 μm/h.

Typically, the waviness introduced into the SiC wafer 20 in the slicing step S13 is 30 μm to 50 μm on each side. Therefore, in the flattening step S142, the depth of the SiC wafer 20 is processed to 30 μm to 50 μm from the main surface 21 and the back surface 22 in order to remove the waviness. Therefore, the amount of material lost per wafer in the planarization step S142 is 60 μm to 100 μm on both surfaces.

In addition, in order to reduce the amount of material loss in the flattening step S142, it is preferable to perform the slicing step S13 so that the waviness introduced into the SiC wafer 20 is 30 μm or less.

The processing time in the flattening step S142 using the abrasive grains having a modified mohs hardness of less than 15 is preferably 5 to 30 minutes, and more preferably 5 to 15 minutes, when single-side processing is performed as free abrasive grains. When both surfaces are processed with free abrasive grains, the processing time is preferably 30 to 50 minutes, and more preferably 15 to 25 minutes.

On the other hand, the processing time in the flattening step S17 in the conventional method using the abrasive grain having a modified mohs hardness of 15 is generally 30 to 50 minutes in the case of performing single-side processing as free abrasive grains, and 60 to 100 minutes in the case of performing double-side processing.

That is, from the viewpoint of shortening the processing time, it is preferable to adopt the flattening step S142 using the abrasive grains having a modified mohs hardness of less than 15. Alternatively, it is preferable that the flattening is performed while grinding the abrasive grains as free abrasive grains.

The work-affected layer up to the previous step is removed by the planarization step S142, and on the other hand, the work-affected layer 30 is newly introduced into the surface of the SiC wafer 20. The depth of the work-affected layer 30 introduced through the planarization step S142 is smaller than the depth of the work-affected layer 30 introduced through the planarization step S17 of the conventional method. Hereinafter, the description will be specifically made.

In the conventional method, diamond abrasive grains having an average abrasive grain diameter of 10 μm are generally used in the flattening step S17 of the conventional method (fig. 26 and 27). In the flattening step S17 of the conventional method, it is considered that the machining-affected layer 30 is introduced to a depth of the same degree as the abrasive grain diameter of the diamond abrasive grain used. Therefore, in the case of using diamond abrasive grains having a grain size of 10 μm which are generally used, it is theorized that the depth of the work-affected layer 30 introduced in the flattening step S17 of the conventional method is about 10 μm per one face of the SiC wafer 20.

On the other hand, the depth of the work-affected layer 30 newly introduced into the surface of the SiC wafer 20 by the planarization step S142 in the present invention is 3 μm or less on each side of the SiC wafer 20.

In this way, the depth of the work-affected layer 30 introduced in the planarization step S142 of the present invention is smaller than the work-affected layer 30 introduced in the planarization step S17 of the conventional method.

In the work-affected layer removing step S20, which is a subsequent step, it is necessary to remove all the work-affected layer 30 introduced in this planarization step S142 or the planarization step S17 of the conventional method. Therefore, by employing the planarization step S142 using abrasive grains with a modified mohs hardness of less than 15 in which the depth of the work-affected layer 30 introduced into the SiC wafer 20 is small, the amount of work and the processing time in the subsequent work-affected layer removal step S20 can be reduced as compared with the case of employing the planarization step S17 of the conventional method using diamond abrasive grains in the conventional method.

Further, in the planarization step S17 of the conventional method using diamond abrasive grains, since deep scratches are randomly generated, there is a problem in quality management.

On the other hand, in the flattening step S142 in the present invention using the abrasive grains having a modified mohs hardness of less than 15, such scratches are difficult to generate, and thus are very advantageous in terms of quality management.

Further, the depth of the work-affected layer 30 introduced in the planarization step S142 in the present invention is as small as 3 μm or less and uniform. The Si vapor pressure etching performed in the subsequent etching step S21 is suitable for removing such a small and uniform process-altered layer 30 with a minimal amount of material loss.

That is, by combining the planarization step S142 and the etching step S21 using the abrasive particles having the modified mohs hardness of less than 15, the material loss can be significantly reduced.

<2> process-altered layer removal step (etching step)

The work-affected layer removing step S20 is a step of removing the work-affected layer 30 introduced into the SiC wafer 20 in the previous step. In the method for manufacturing a SiC wafer of the present invention, the step S20 of removing the affected layer includes: the etching step S21 etches the SiC wafer 20 by heating under Si vapor pressure.

As described above, the work-affected layer removing step S20 is a step of removing the work-affected layer 30 introduced into the SiC wafer 20 in the previous step. Therefore, it is preferable that the work-altered layer removing step S20 including the etching step S21 is performed after the wafer shape forming step S10 including the flattening step S142, the imprint forming step S15, and the chamfering step S16, as shown in fig. 6 and 7.

The method of manufacturing a SiC wafer of the present invention that solves the third problem has a significant effect of reducing the amount of material loss in the process-altered layer removing step S20. The following description is made in detail.

The work-affected layer removing step S20 in the conventional method includes: a rough grinding step (step S22) of performing rough grinding using diamond abrasive grains; and a finish grinding step (step S23) of performing fine grinding using diamond abrasive grains finer than the abrasive grain size used in the rough grinding step S22 (fig. 26 and 27).

In the rough grinding step S22 in the conventional method, processing is performed to a depth of 10 to 15 μm from the main surface 21 and the back surface 22 of the SiC wafer 20. Therefore, the amount of material loss per wafer accompanying the rough grinding step S22 is 20 μm to 30 μm on both sides.

The time taken for the rough grinding step S22 is generally 10 to 15 minutes on both sides.

As a grinding means in the finish grinding step S23, fixed abrasive polishing or the like can be exemplified as in the rough grinding step S22.

In general, in the finish grinding step S23, the SiC wafer 20 is processed to a depth of 3 μm to 10 μm from the main surface 21 and the back surface 22. Therefore, the amount of material loss per wafer accompanying the finish grinding step S23 is 6 μm to 20 μm on both surfaces.

The time taken for the finish grinding step S23 is generally 6 to 20 minutes on both sides.

Thus, in the conventional method, a material loss of 20 μm to 30 μm is generated in the rough grinding step S22, and a material loss of 6 μm to 20 μm is generated in the finish grinding step S23. That is, a total material loss of 30 μm to 50 μm occurs in the entire affected layer removing step S20.

On the other hand, in the method for producing a SiC wafer of the present invention, the work-affected layer 30 introduced in the flattening step S142 using abrasive grains having a modified mohs hardness of less than 15 in the previous wafer shape forming step S10 is as small as 3 μm or less on each surface and is uniform.

Here, the etching step S21 employed in the present invention is suitable for removing the thin and uniform work-affected layer 30. Specifically, the Si vapor pressure etching has a feature of preferentially etching and removing unstable sites that are liable to thermal decomposition. Therefore, by performing Si vapor pressure etching on the work-affected layer 30 introduced in the flattening step S142, which is thin and uniform as described above, the work-affected layer 30 can be preferentially etched, and thus the occurrence of unnecessary material loss can be suppressed.

That is, only on each side³A material loss of 6 μm on both sides of the wafer can be reduced to a minimum as compared with the conventional method (total material loss of 30 μm to 50 μm), and the affected layer introduced in the previous step S10 of forming the wafer shape can be removed³0。

In this way, the method for producing a SiC wafer of the present invention can achieve a significant reduction in material loss by combining the flattening step S142 and the etching step S21 using the abrasive grains having a modified mohs hardness of less than 15.

From the viewpoint of removing a necessary and sufficient amount of the work-affected layer 30, specifically, it is desirable that in the etching step S²1 pair of SiC wafers²0, the etching is preferably 10 μm or less, more preferably 5 μm or less, and still more preferably 0³And is less than μm.

Further, it is desirable that in the etching step S²1, the SiC wafer 20 is etched on each surface, and the etching is preferably 0.5 μm or more, and more preferably 1 μm or more.

In addition, the method for manufacturing a SiC wafer of the present invention includes the step S of removing the affected layer²0 is also excellent in terms of the ease of the steps required. Hereinafter, the description will be specifically made.

In the rough grinding step S22 in the conventional method, diamond abrasive grains having an average abrasive grain diameter of 3 to 10 μm are used. In the rough grinding step S22, the work-affected layer 30 is introduced to the same depth as the abrasive grains of the diamond abrasive grains used. Thus, when using an average abrasive particle size of³In the case of diamond abrasive grains of μm to 10 μm, it is considered that the work-affected layer introduced in the rough grinding step S22³The depth of 0 is generally about 3 μm to 10 μm.

Further, in the finish grinding step S23 in the conventional method, diamond abrasive grains having an average abrasive grain diameter of 0.1 to 3 μm are used. In the finish grinding step S23, the machining-affected layer 30 is also introduced to the same depth as the abrasive grains of the diamond abrasive grains used, as in the rough grinding step S22. Therefore, when the diamond abrasive grains having an average grain size of 0.1 μm to 3 μm are used, it is considered that the depth of the work-affected layer 30 introduced in the finish grinding step S23 is generally about 0.1 μm to 3 μm.

In this way, in the conventional method, in order to remove the work-affected layer 30 introduced in the wafer shape forming step S10, the rough grinding step S22 is first performed, and the work-affected layer 30 is newly introduced in this step as well. In order to remove the newly introduced work-affected layer 30, a finish-grinding step S23 is performed.

That is, in the conventional method, in order to remove the work-affected layer 30 of the SiC wafer 20, a multi-stage step is required, and there is a problem in terms of the ease of the step.

On the other hand, the method for manufacturing a SiC wafer of the present invention enables removal of the work-affected layer 30 introduced in the previous wafer shape forming step S10 to be achieved in one step of the etching step S21 (fig. 6 and 7).

This is because the work-affected layer 30 is an extremely small value as compared with the conventional method in which the work-affected layer 30 introduced in the flattening step S142 using abrasive grains having a modified mohs hardness of less than 15 in the previous wafer shape forming step S10 is 3 μm or less on each side.

That is, the method for manufacturing a SiC wafer of the present invention combines the planarization step S142 and the etching step S21 using the abrasive grains having the modified mohs hardness of less than 15, thereby significantly improving the work efficiency of the modified layer removing step S20.

In addition, in the conventional method, grinding work is usually performed on each surface in the rough grinding step S22 and the finish grinding step S23, and there is a problem that warpage of the wafer due to the tayman (Twyman) effect occurs in addition to an increase in the workload of mounting, detaching, and the like of the wafer.

On the other hand, in the etching step S21 employed in the method for producing an SiC wafer of the present invention, since both surfaces can be etched simultaneously, the wafer is not warped by the tayman (Twyman) effect.

In the etching step S21, the work-affected layer 30 (see fig. 7) drawn into the portions other than the main surface 21 and the back surface 22 (the periphery of the outer peripheral portion 23 and the engraved portion 25) may be removed, which may contribute to the improvement in the quality of the SiC wafer 20.

Further, the method of manufacturing a SiC wafer of the present invention that solves the fourth problem has a significant effect that more SiC wafers can be manufactured from one ingot. The following description is made in detail.

As described above, in the conventional method, diamond abrasive grains having an average abrasive grain diameter of 10 μm were used in the flattening step S17 of the conventional method, and as a rule, the work-affected layer 30 having the same degree of average abrasive grain diameter, i.e., 10 μm, was introduced into the SiC wafer 20 in this step.

In the conventional method, in order to remove the 10 μm work-affected layer 30, as the work-affected layer removing step S20, it includes: a rough grinding step (step S22) of performing rough grinding using diamond abrasive grains; and a finish grinding step (step S23) of performing fine grinding using diamond abrasive grains finer than the abrasive grain size used in the rough grinding step S22 (fig. 26 and 27).

In the rough grinding step S22 in the conventional method, diamond abrasive grains having an average abrasive grain diameter of 3 μm to 10 μm are used to perform machining from the main surface 21 and the back surface 22 of the SiC wafer 20 to a depth of 10 μm to 15 μm. Therefore, the amount of material loss per wafer accompanying the rough grinding step S22 is 20 μm to 30 μm on both sides. Then, in this step, a machining-degraded layer 30 of about 3 μm to 10 μm having the same average grain size as that of the diamond abrasive grains is newly introduced.

The time taken for the rough grinding step S22 is generally 10 to 15 minutes on both sides.

In the subsequent finish grinding step S23, as in the rough grinding step S22, fixed abrasive polishing or the like can be exemplified.

In general, in the finish grinding step S23, diamond abrasives having an average abrasive grain diameter of 0.1 to 3 μm are used to process the SiC wafer 20 from the main surface 21 and the back surface 22 to a depth of 3 to 10 μm. Therefore, the amount of material loss per wafer accompanying the finish grinding step S23 is 6 μm to 20 μm on both surfaces. Then, the machining-degraded layer 30 having a diameter of about 0.1 to 3 μm, which is about the same as the average grain diameter of the diamond grains, is newly introduced in the process.

The time taken for the finish grinding step S23 is generally 6 to 20 minutes on both sides.

In this way, in the conventional method, in order to remove the process-altered layer 30 of about 10 μm introduced in the flattening step S17 of the conventional method, a material loss of 20 μm to 30 μm is generated in the rough grinding step S22, and a material loss of 6 μm to 20 μm is generated in the finish grinding step S23. That is, a total material loss of 30 μm to 50 μm occurs in the entire affected layer removing step S20.

On the other hand, in the method for manufacturing a SiC wafer of the present invention, the work-affected layer 30 introduced in the previous planarization step S142 is removed by the etching step S21.

In a preferred embodiment, approximately the same amount as the depth of the work-affected layer 30 introduced in the planarization step S142, specifically, an amount in the range of ± 1 μm, more preferably in the range of ± 0.5 μm, and still more preferably in the range of ± 0.2 μm with respect to the depth of the work-affected layer 30 is etched and removed.

In this way, in the etching step S21, by performing etching while suppressing the amount of material loss, more SiC wafers 20 can be produced from one ingot.

The Si vapor pressure etching has a characteristic that it preferentially etches and removes unstable portions that are easily thermally decomposed. Therefore, by performing Si vapor pressure etching on the work-affected layer 30 introduced in the flattening step S142, the work-affected layer 30 can be preferentially etched, and thus the occurrence of unnecessary material loss can be suppressed.

That is, since the work-affected layer 30 introduced in the previous wafer shape forming step S10 can be removed preferentially without generating an additional material loss, the work-affected layer 30 can be removed with only a very small material loss as compared with the conventional method (material loss of 30 μm to 50 μm in total).

In this way, the method for manufacturing a SiC wafer of the present invention achieves a significant reduction in the amount of material loss by removing the structure of the work-affected layer 30 introduced in the planarization step S142 by the etching step S21.

From the viewpoint of removing a necessary and sufficient amount of the work-affected layer 30, it is specifically desirable to etch each surface of the SiC wafer 20 in the etching step S21, and the etching is preferably 10 μm or less, more preferably 5 μm or less, and further preferably 3 μm or less.

It is desirable that each surface of the SiC wafer 20 is etched in the etching step S21, and the etching is preferably 0.5 μm or more, more preferably 1 μm or more.

Further, as described above, in order to remove the work-affected layer 30 introduced in the planarization step S17 of the conventional method, a multi-stage step is required, and in the present invention, the work-affected layer 30 introduced in the planarization step S142 may be removed in one step of the etching step S21.

That is, according to the present invention, the SiC wafer 20 can be manufactured in a smaller number of steps than the conventional method.

In addition, in the conventional method, grinding work is usually performed on each surface in the rough grinding step S22 and the finish grinding step S23, and there is a problem that warpage of the wafer due to the tayman (Twyman) effect occurs in addition to an increase in the workload of mounting, detaching, and the like of the wafer.

On the other hand, in the etching step S21 employed in the method for producing an SiC wafer of the present invention, since both surfaces can be etched simultaneously, the wafer is not warped by the tayman (Twyman) effect.

In the etching step S21, the work-affected layer 30 (see fig. 3) drawn into the portions other than the main surface 21 and the back surface 22 (the outer peripheral portion 23 and the periphery of the scribe portion 25) may be removed, which may contribute to the improvement in the quality of the SiC wafer 20.

That is, the work-affected layer removing step S20 is a step of removing the work-affected layer 30 introduced into the SiC wafer 20 in the previous step. Therefore, as shown in fig. 6 and 7, the process-altered layer removing step S20 including the etching step S21 is performed after the planarization step S142. By performing the etching step S21 after the planarization step S142, the work-affected layer 30 introduced into the SiC wafer by the planarization step S142 can be removed in the etching step S21.

In the SiC wafer subjected to the etching step S21, not only the lattice strain of the surface but also the lattice strain inside (strain layer 32 in fig. 22) is removed. By performing the subsequent chemical mechanical polishing step S32 on this SiC wafer 20, a high-quality SiC wafer 20 with lattice strain within the wafer removed and with high flatness can be manufactured.

Further, it is preferable that the imprint forming step S15 and the chamfering step S16 are performed before the etching step S21, in addition to the planarization step S142. This makes it possible to remove the work-affected layer 30 and the stress (see fig. 7) introduced around the outer peripheral portion 23 and the imprint portion 25, and to contribute to the improvement in quality of the SiC wafer 20.

Further, as described above, it is desirable that the lattice under the surface (the main surface 21 and the back surface 22) of the SiC wafer 20 subjected to the etching step S21 not be lattice-strained. Thus, since lattice strain does not occur in the SiC wafer 20, the SiC wafer 20 preferable for device manufacturing steps can be provided.

<3> mirror polishing step

One embodiment of the method for manufacturing a SiC wafer of the present invention includes a mirror polishing step S30.

The mirror polishing step S30 includes: a Chemical Mechanical Polishing (CMP) step (step S32) of combining the mechanical action of the polishing pad and the chemical action of the slurry for polishing.

In the manufacturing method of the SiC wafer of the present invention that solves the fifth problem, after the etching step S21, more preferably after the etching step S21, the chemical mechanical polishing step S32 is performed without intervening other steps (more specifically, a step that introduces the process-altered layer 30).

The chemical mechanical polishing step S32 is a step of processing a mirror surface of a surface state preferable for the subsequent device manufacturing step. Although fig. 7 shows a state in which the main surface 21 of the SiC wafer 20 is mirrored (a two-dot chain line portion), both the main surface 21 and the rear surface 22 may be mirrored, or only the rear surface 22 may be mirrored.

From the viewpoint of product control, it is preferable to perform the chemical mechanical polishing step S32 only on the main surface 21 to produce the SiC wafer 20 having a mirror surface and a pearskin surface. The main surface 21 subjected to the chemical mechanical polishing step S32 is a surface having high flatness without the work-affected layer 30, and the remaining back surface 22 also has an excellent surface without the work-affected layer 30. That is, according to the method for producing a SiC wafer of the present invention, a high-quality SiC wafer 20 having a mirror surface and a peaked surface can be produced.

In general, in the chemical mechanical polishing step S32, processing is performed from the surface of the SiC wafer 20 to a depth of 0.5 μm to 1.5. mu.m. Therefore, the material loss per wafer accompanying the chemical mechanical polishing step S32 is 0.5 μm to 1.5 μm in the case of single-side processing and 1 μm to 3 μm in the case of double-side processing.

In addition, the time taken for this chemical mechanical polishing step S32 is generally 15 minutes to 45 minutes in single-side polishing and 30 minutes to 90 minutes in double-side polishing.

In addition, the chemical mechanical polishing step S32 in the conventional method has a technical meaning of removing the work-affected layer 30 newly introduced in the finish grinding step S23 in the work-affected layer removing step S20 (fig. 26 and 27). On the other hand, in the method for manufacturing a SiC wafer of the present invention, all the work-affected layer 30 can be removed in the previous etching step S21. Therefore, in the chemical mechanical polishing step S32 in the method for manufacturing a SiC wafer of the present invention, the technical significance of removing the work-affected layer 30 is small compared to the conventional method.

<4> summary

The amounts of material loss in the respective steps of the conventional method and the method for manufacturing a SiC wafer of the present invention that solves the third problem, and the depths of the introduced work-affected layers 30 are summarized in table 1.

[ Table 1]

As shown in Table 1, in the conventional method, a material loss of 87 μm to 152 μm in total was generated. In particular, in the conventional method, in order to reliably remove the work-affected layer 30, 100 μm or more is generally removed in each SiC wafer 20.

On the other hand, the amount of material loss in the method for producing an SiC wafer of the present invention is 61 μm to 108 μm. As described above, according to the present invention, the amount of material loss in the production of the SiC wafer can be greatly reduced.

Further, the pre-processing thickness D1 of the SiC wafer 20 sliced from the ingot 10 in the slicing step S13 sets the amount of material loss as an index. That is, the thickness obtained by adding the material loss amount to the thickness D of the SiC wafer 20 to be finally obtained (the thickness of the SiC wafer 20 at the end of surface processing) is set as the pre-processing thickness D1.

In this way, the thickness D1 before the surface processing is determined by adding the material loss amount to the thickness of the SiC wafer after the surface processing is completed. The "surface processing" referred to herein is processing for reducing the thickness of the SiC wafer 20, as in the planarization step S142, the etching step S21, and the chemical mechanical polishing step S32.

That is, the pre-process thickness D1 is set by adding the material loss amount to the thickness of the SiC wafer 20 up to the point at which the thickness no longer decreases in the subsequent steps.

Therefore, the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness with the lower limit of 61 μm or more, more preferably 62 μm or more, and still more preferably 63 μm or more is preferably set to the thickness D1 before processing.

Further, by setting the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 108 μm or less, more preferably 106 μm or less, and still more preferably 96 μm or less as the upper limit as the thickness D1 before processing, more SiC wafers 20 can be produced from one ingot 10.

Further, as described above, in the conventional method, 100 μm or more is generally removed in each SiC wafer 20. Therefore, the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 100 μm or less, more preferably less than 100 μm, as the upper limit is preferably set to the thickness D1 before processing. Thereby, more SiC wafers 20 can be manufactured than when a conventional method that is generally performed is used.

In addition, as shown in Table 1, the lower limit of the material loss amount in the conventional method was 87 μm. Therefore, the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 87 μm or less, more preferably less than 87 μm, and still more preferably 80 μm or less as the upper limit is preferably set to the thickness D1 before processing. Thereby, the SiC wafer 20 can be manufactured with high yield which is difficult to achieve in the conventional method.

In addition, the thickness D of the SiC wafer 20 that has undergone the steps from the dicing step S13 to the mirror polishing step S30 may exemplify: typically 100 to 600. mu.m, more typically 150 to 550. mu.m, still more typically 200 to 500. mu.m, yet still more typically 250 to 450. mu.m, yet still more typically 300 to 400. mu.m.

That is, the thickness D1 before processing is preferably set by adding the material loss amount according to the method for producing a SiC wafer of the present invention to the thickness of these typical SiC wafers 20.

Specifically, in the case where it is intended to obtain, as a final product, the SiC wafer 20 having a thickness D of 350 μm by the method for producing a SiC wafer of the present invention, it is preferable to obtain the SiC wafer 20 having a pre-processing thickness D1 as a lower limit of 411 μm or more, more preferably 412 μm or more, and still more preferably 413 μm or more in the slicing step S13.

Further, it is preferable to obtain the SiC wafer 20 having the pre-processing thickness D1 as an upper limit of 458 μm or less, more preferably 456 μm or less, further preferably 450 μm or less, further preferably less than 450 μm, further preferably 446 μm or less, further preferably 437 μm or less in the dicing step S13.

Further, in the conventional method, the total processing time from after the dicing step S13 to after the chemical mechanical polishing step S32 is 91 minutes to 180 minutes.

On the other hand, in the present invention, the total processing time from after the dicing step S13 to after the chemical mechanical polishing step S32 is 23 minutes to 63 minutes.

As described above, the method for producing a SiC wafer of the present invention is effective also from the viewpoint of shortening the processing time.

Next, the amounts of material loss in the respective steps of the conventional method and the method for manufacturing a SiC wafer of the present invention that solves the fourth and fifth problems, and the depth of the introduced work-affected layer 30 are summarized in table 2.

[ Table 2]

As shown in Table 2, in the conventional method, a material loss of 87 μm to 152 μm in total was generated. In particular, in the conventional method, in order to reliably remove the work-affected layer 30 introduced in each step, 100 μm or more is generally removed in each SiC wafer 20.

On the other hand, the material loss in the method for producing an SiC wafer of the present invention is 61 μm to 122 μm as shown in table 2. As described above, according to the present invention, the amount of material loss in the production of the SiC wafer can be greatly reduced.

Further, the pre-processing thickness D1 of the SiC wafer 20 sliced from the ingot 10 in the slicing step S13 sets the amount of material loss as an index. That is, the thickness obtained by adding the material loss amount to the thickness D of the SiC wafer 20 to be finally obtained (the thickness of the SiC wafer 20 at the end of surface processing) is set as the pre-processing thickness D1.

In this way, the thickness D1 before the surface processing is determined by adding the material loss amount to the thickness of the SiC wafer after the surface processing is completed. The "surface processing" referred to herein is processing for reducing the thickness of the SiC wafer 20, as in the planarization step S142, the etching step S21, and the chemical mechanical polishing step S32.

That is, the pre-process thickness D1 is set by the amount of material loss plus the thickness of the SiC wafer 20 at which point the thickness no longer decreases through subsequent steps.

Therefore, the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness with the lower limit of 61 μm or more, more preferably 62 μm or more, and still more preferably 63 μm or more is preferably set to the thickness D1 before processing.

Further, it is preferable that the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 122 μm or less, more preferably 120 μm or less, and still more preferably 110 μm or less as the upper limit is set to the thickness D1 before processing. Thereby, more SiC wafers 20 can be manufactured from one ingot 10.

Further, as described above, in the conventional method, 100 μm or more is generally removed in each SiC wafer 20. Therefore, the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 100 μm or less, more preferably less than 100 μm, as the upper limit is preferably set to the thickness D1 before processing. Thereby, more SiC wafers 20 can be manufactured than when a conventional method that is generally performed is used.

In addition, as shown in Table 2, the lower limit of the material loss amount in the conventional method was 87 μm. Therefore, by setting the thickness obtained by adding the thickness D of the SiC wafer 20 to the thickness of 87 μm or less, more preferably less than 87 μm, and still more preferably 80 μm or less as the upper limit as the thickness D1 before processing, the SiC wafer 20 can be manufactured with high yield which has been difficult to achieve by conventional methods.

In addition, the thickness D of the SiC wafer 20 that has undergone the steps from the dicing step S13 to the mirror polishing step S30 may exemplify: typically 100 to 600. mu.m, more typically 150 to 550. mu.m, still more typically 200 to 500. mu.m, yet still more typically 250 to 450. mu.m, yet still more typically 300 to 400. mu.m.

That is, the thickness D1 before processing is preferably set by adding the material loss amount according to the method for producing a SiC wafer of the present invention to the thickness of these typical SiC wafers 20.

Specifically, in the case where it is intended to obtain, as a final product, the SiC wafer 20 having a thickness D of 350 μm by the method for producing a SiC wafer of the present invention, it is preferable to obtain the SiC wafer 20 having a pre-processing thickness D1 as a lower limit of 411 μm or more, more preferably 412 μm or more, and still more preferably 413 μm or more in the slicing step S13.

In this case, it is preferable to obtain the SiC wafer 20 having the pre-processing thickness D1 as the upper limit of 472 μm or less, more preferably 470 μm or less, further preferably 460 μm or less, further preferably 450 μm or less, further preferably less than 450 μm, further preferably 437 μm or less in the dicing step S13.

In the planarization step S142, when abrasive grains having a modified mohs hardness of less than 15 are used, or when planarization is performed while grinding the abrasive grains, the depth of the work-affected layer 30 introduced in this step can be suppressed to 3 μm or less.

The amount of material loss and the depth of the introduced work-affected layer 30 in each step in this case are shown in table 3 below.

[ Table 3]

As shown in table 3, when the preferred method of suppressing the depth of the work-affected layer 30 introduced in the flattening step S142 to 3 μm or less is adopted, the material loss amount is 61 μm to 108 μm. As described above, according to the present invention, the amount of material loss in the production of the SiC wafer can be greatly reduced.

Therefore, in the preferred embodiment of the present invention, by setting the thickness added with the thickness of preferably 108 μm or less, more preferably 106 μm or less, and still more preferably 96 μm or less as the thickness D1 before processing, more SiC wafers 20 can be produced from one ingot 10.

Specifically, in the case where it is intended to obtain, as a final product, the SiC wafer 20 having a thickness D of 350 μm by the preferred mode of the present invention, it is preferable to obtain the SiC wafer 20 having the pre-processing thickness D1 as an upper limit of 458 μm or less, more preferably 456 μm or less, further preferably 450 μm or less, further preferably less than 450 μm, further preferably 446 μm or less, further preferably 437 μm or less, further preferably less than 437 μm in the dicing step S13.

In addition, values in the case where the etching amount in the etching step S21 is 20 μm or less and 6 μm or less are summarized in tables 2 and 3, and specific values regarding the pre-processing thickness D1 are described based on these values, but the embodiment of the present invention is of course not limited thereto.

When the etching amount in the etching step S21 is different from each other, the total material loss amount may be calculated based on the value, and the thickness D1 before processing may be set. Although the specific value of the pre-processing thickness D1 in the case where the etching amount is different is not described in the present specification, it can be determined by a simple calculation, and thus it can be said that the same is described in the present specification.

In addition, by performing the planarization step S142 before the etching step S21, the work-affected layer 30 (crack layer and strain layer) introduced by the planarization step S142 can be removed by the etching step S21. By performing the chemical mechanical polishing step S32 after this etching step S21, a high-quality SiC wafer 20 having no work-affected layer 30 and having high flatness can be manufactured.

[ examples ]

The present invention will be described in more detail below while showing examples. However, it is needless to say that the present invention is not limited to the following examples.

Production of SiC wafer of the present invention for solving the first and second problems, and observation and evaluation thereof

SiC wafers of example 1 and example 2 were produced by the following method.

< example 1>

(slicing step)

The single crystal SiC ingot was sliced using a slurry containing diamond abrasive grains having an average abrasive grain diameter of 10 μm to obtain a SiC wafer having a diameter of 6 inches.

(Pear skin surface processing step) and (flattening step)

The SiC wafer was polished by using a polishing composition containing B having an average abrasive grain size of 40 μm₄C abrasive grain slurry free abrasive grain mode, at a working pressure of 150g/cm²The pear peel surface processing was performed under the conditions of a fixed disc rotation speed of 15rpm, a head rotation speed of 5rpm, a processing time of 20 minutes, and a processing speed of about 1.0 μm/min.

At this time, B at the end of the pear peel processing step₄The average grain diameter of the C grains was 10 μm.

(etching step)

The SiC wafer after the flattening step was subjected to Si vapor pressure etching under conditions of an etching amount of 3 μm (processing time of about 3 minutes, processing speed of 1 μm/minute), an etching amount of 6 μm (processing time of about 6 minutes, processing speed of 1 μm/minute), and an etching amount of 9 μm (processing time of about 9 minutes, processing speed of 1 μm/minute). The thickness of the SiC wafer after the etching step was 350 μm.

< example 2>

(slicing step)

A dicing step was performed under the same conditions as in example 1, and a SiC wafer having a diameter of 6 inches was obtained.

(Pear skin surface processing step) and (flattening step)

The SiC wafer was flattened under the following conditions by a fixed abrasive grain method using a grindstone (ceramic bond) containing diamond abrasive grains having an average abrasive grain diameter of 30 μm.

Grinding the stone at a rotating speed: 1250rpm

Cutting-in distance: 2 μm

Front and back feeding: 190 m/min

Left-right feeding: 21 m/min

Processing speed: 100 μm/hr

(etching step)

Si vapor pressure etching was performed under the same conditions as in example 1. The thickness of the SiC wafer after the etching step was 350 μm.

< Observation and evaluation of Pear skin surface >

The back surfaces of the SiC wafers of example 1 and example 2 were observed using a white interference microscope. The results are shown in fig. 8 and 9.

Fig. 8 is a white interference microscope image (95 μm × 75 μm) of example 1, and (a) in fig. 8 shows before the etching step, and (b) in fig. 8 shows after the etching step (etching amount 3 μm).

Fig. 9 is a white interference microscope image (95 μm × 75 μm) of example 2, and (a) in fig. 9 shows before the etching step, and (b) in fig. 9 shows after the etching step (etching amount 3 μm).

As shown in fig. 8 and 9, the peaked surface was formed on the back surface of the SiC wafers of examples 1 and 2. Specifically, as shown in fig. 8, a rind surface in which irregular fine spot-like irregularities are randomly combined together is formed on the back surface of the SiC wafer of example 1. As shown in fig. 9, the back surface of the SiC wafer of example 2 was formed with a peaked surface in which stripe-like irregularities extending in one direction were arranged. As can be seen from fig. 8 and 9, the pearskin surface after etching has a surface structure with smooth edges from which fine burrs are removed.

Table 4 summarizes the arithmetic average roughness Ra and the maximum height Rz with respect to the etching amount for examples 1 and 2.

[ Table 4]

As shown in table 4, by increasing the etching amount, the arithmetic average roughness Ra and the maximum height Rz tended to decrease. In particular, in example 1, it can be seen that the arithmetic average roughness Ra and the maximum height Rz tend to decrease.

This result shows that a significant effect of controlling the roughness of the pear peel surface of the SiC wafer made of a material difficult to process can be obtained by adjusting the etching amount.

The rind surfaces of the SiC wafers of examples 1 and 2 were not easily slid during transportation or in the apparatus, and were easily peeled from the sample stage of the electrostatic chuck system. Further, the roughness of the pearskin surface can be set so that the adhesion of particles is less likely to occur and that defects such as deterioration of the flatness of the wafer do not occur when the wafer is held on the sample stage.

In addition, if the principal surface 21 of the SiC wafer is made to be a mirror surface by a known method, detection can be performed by an optical sensor, and the SiC wafer having advantages in device manufacturing steps can be obtained.

< reflectance and transmittance of SiC wafer >

The reflectance and the external transmittance of the SiC wafer of example 1 were measured using a spectrophotometer (model U-4000 spectrophotometer). Fig. 10 shows the measurement result of the reflectance, and fig. 11 shows the measurement result of the external transmittance. In addition, as comparative examples, fig. 10 and 11 show the reflectance and external transmittance of SiC wafers whose principal surfaces and rear surfaces are mirror surfaces.

Fig. 10 (a) shows the result of measuring the reflectance of the electromagnetic wave having a wavelength of 300nm to 1500nm incident from the main surface side of the SiC wafer and reflected to the main surface side. It is understood that the reflectance of the comparative example having mirror surfaces on both sides varies in each wavelength in the visible light region, and shifts between the reflectance of 19% and 27%. On the other hand, the reflectance of example 1 having a pearskin surface as the back surface was lower than that of the comparative example in all wavelength regions, and the difference in the respective wavelengths in the visible light region was small, and was found to shift between the reflectance of 19% and 23%.

Fig. 10 (b) shows the result of measuring the reflectance of the SiC wafer when an electromagnetic wave having a wavelength of 300nm to 1500nm is incident on the back surface side of the SiC wafer and reflected to the back surface side. While reflectance of 19% or more was measured in the wavelength region of visible light in the results of example 1 of fig. 10 (a), reflectance of 3% or less was measured in the wavelength region of visible light in the results of fig. 10 (b).

As described above, in example 1, the reflectance difference between the main surface and the back surface is large, and thus the main surface and the back surface can be easily recognized.

Fig. 11 shows the result of measuring the transmittance of the SiC wafer when an electromagnetic wave having a wavelength of 300nm to 1500nm is incident from the main surface side of the SiC wafer. The transmittance of example 1, in which the back surface is a pearskin surface, is lower than that of a SiC wafer in which both surfaces are formed as mirror surfaces in all wavelength regions.

In particular, in the results of example 1, the transmittance of 25% or less was measured in all the wavelength regions. Therefore, in example 1 in which the pear skin surface is formed on the back surface, the transmission of visible light can be suppressed, and the detection rate of the optical sensor can be improved.

< measurement of a work-affected layer by SEM-EBSD >

The stresses present in the SiC wafers of examples 1 and 2 before and after the etching step were observed by the SEM EBSD method. The results are shown in fig. 12 and 13. The section of the SiC wafer cleaved in example 1 and example 2 was measured using a scanning electron microscope under the following conditions.

SEM device: merline manufactured by Zeiss

EBSD analysis: OIM crystal orientation analysis device manufactured by TSL Solutions

Acceleration voltage: 15kV

Current of the probe: 15nA

Step length: 200nm

Depth of reference point R: 20-25 mu m

FIG. 12 is a sectional SEM-EBSD imaged image of example 1, and FIG. 13 is a sectional SEM-EBSD imaged image of example 2.

As shown in fig. 12 (a) and 13 (a), lattice strain was observed in the SiC wafer in both example 1 and example 2 before the etching step. This is the lattice strain introduced by the rind processing step or the like. In addition, compressive stress was observed.

On the other hand, as shown in (b) in fig. 12 and (b) in fig. 13, after the etching step, the lattice strain of the crystal lattice under the surface with respect to the reference lattice was 0.001% or less, and no lattice strain was observed in the SiC wafers of example 1 and example 2.

From the results, it is understood that stress hardly occurs in the SiC wafer 20 and the strain layer that is difficult to remove in the work-affected layer 30 is removed. That is, it is shown that the stress in the SiC wafer introduced by the planarization step or the like can be removed by the etching step.

< measuring affected layer by TEM >

The SiC wafers of example 1 and example 2 were observed for cross section using a Transmission Electron Microscope (TEM). The results are shown in fig. 14 and 15.

FIG. 14 is a cross-sectional TEM image (50 nm. times.50 nm) of example 1, in which (a) in FIG. 14 shows the (0001) plane side with an etching amount of 3 μm, (b) in FIG. 14 shows the (000-1) plane side with an etching amount of 3 μm, (c) in FIG. 14 shows the (0001) plane side with an etching amount of 6 μm, and (d) in FIG. 14 shows the (000-1) plane side with an etching amount of 6 μm.

FIG. 15 is a cross-sectional TEM image (50 nm. times.50 nm) of example 2, in which (a) in FIG. 15 is the (0001) surface side with an etching amount of 3 μm, (b) in FIG. 15 is the (000-1) surface side with an etching amount of 3 μm, (c) in FIG. 15 shows the (0001) surface side with an etching amount of 6 μm, and (d) in FIG. 15 shows the (000-1) surface side with an etching amount of 6 μm.

Based on the cross-sectional TEM image, the presence or absence of the altered layer and the depth thereof were evaluated by the following methods.

[ evaluation method ] A cross-sectional TEM image is enlarged to a magnification at which a machining-deteriorated layer of several nm can be observed, the contrast between the front surface side and the block side is compared, and the image is evaluated as "having a machining-deteriorated layer" when there is a contrast difference, and as "not having a machining-deteriorated layer" when there is no contrast difference.

In the case of "having a process-altered layer", the depth thereof was measured based on a cross-sectional TEM image.

As a result, no processing-affected layer was observed in the SiC wafer of example 1, both when the etching amount was 3 μm and when the etching amount was 6 μm.

On the other hand, in the case of the SiC wafer of example 2, when the etching amount was 3 μm, a 10nm work-affected layer was observed on the (0001) surface side, and a 43nm work-affected layer was observed on the (000-1) surface side. However, when the etching amount was 6 μm, no processing-deteriorated layer was observed.

As is clear from the SEM-EBSD measurement of the work-affected layer and the TEM measurement of the work-affected layer, the Si vapor pressure etching was performed, and thus substantially no work-affected layer was observed in examples 1 and 2.

If the chemical mechanical polishing process is applied to the SiC wafer in a state where the affected layer is removed, as in the SiC wafers of examples 1 and 2, a high-quality SiC wafer having no cracks (damage) or lattice strain inside and having a high degree of flatness can be obtained.

Production of SiC wafer of the present invention for solving the third and fourth problems, and observation and evaluation thereof

SiC wafers of example 3, example 4, comparative example 1, and comparative example 2 were produced by the following methods.

< example 3>

(slicing step)

The single crystal SiC ingot was sliced using a slurry containing diamond abrasive grains having an average abrasive grain diameter of 10 μm to obtain a SiC wafer having a diameter of 6 inches.

(flattening step)

The SiC wafer was polished by using a polishing composition containing B having an average abrasive grain size of 40 μm₄C abrasive grain slurry free abrasive grain mode, at a working pressure of 150g/cm²The surface was flattened under the conditions of a surface plate rotation speed of 15rpm, a head rotation speed of 5rpm, a processing time of 20 minutes, and a processing speed of about 1.0 μm/min.

At this time, B at the end of the planarization step₄The average grain diameter of the C grains was 10 μm.

(etching step)

The SiC wafer after the flattening step was subjected to Si vapor pressure etching under conditions in which the etching amount was 3 μm (the processing time was about 3 minutes, and the processing speed was 1 μm/minute).

< example 4>

(slicing step)

A dicing step was performed under the same conditions as in example 3, and a SiC wafer having a diameter of 6 inches was obtained.

(flattening step)

The SiC wafer was flattened under the following conditions by a fixed abrasive grain method using a grindstone (ceramic bond) containing diamond abrasive grains having an average abrasive grain diameter of 30 μm.

Grinding the stone at a rotating speed: 1250rpm

Cutting-in distance: 2 μm

Front and back feeding: 190 m/min

Left-right feeding: 21 m/min

Processing speed: 100 μm/hr

(etching step)

Si vapor pressure etching was performed under the same conditions as in example 3, except that the processing time was set to 6 minutes. The etching amount was 6 μm.

< comparative example 1>

(slicing step)

A dicing step was performed under the same conditions as in example 3, and a SiC wafer having a diameter of 6 inches was obtained.

(etching step)

For the obtained SiC wafer, Si vapor pressure etching was performed under the same conditions as in example 3.

< comparative example 2>

(slicing step)

A dicing step was performed under the same conditions as in example 3, and a SiC wafer having a diameter of 6 inches was obtained.

(flattening step)

The SiC wafer was flattened under the following conditions by a fixed abrasive grain method using a grindstone (vitrified bond) containing diamond abrasive grains having an average abrasive grain diameter of 30 μm.

Grinding the stone at a rotating speed: 1250rpm

Cutting-in distance: 2 μm

Front and back feeding: 190 m/min

Left-right feeding: 21 m/min

Processing speed: 100 μm/hr

(etching step)

Si vapor pressure etching was performed under the same conditions as in example 3.

< Observation and evaluation of affected layer >

The SiC wafers of example 3, example 4, comparative example 1, and comparative example 2 were observed for cross section using a Transmission Electron Microscope (TEM). The results are shown in fig. 16, 17, 18, and 19. In each figure, (a) is a sectional TEM image obtained by enlarging the (0001) surface side in the range of 50nm angle, and (b) is a sectional TEM image obtained by enlarging the (000-1) surface side in the range of 50nm angle.

Based on the cross-sectional TEM image, the presence or absence of the altered layer and the depth thereof were evaluated by the following methods.

[ evaluation method ] A cross-sectional TEM image is enlarged to a magnification at which a machining-deteriorated layer of several nm can be observed, the contrast between the front surface side and the block side is compared, and the image is evaluated as "having a machining-deteriorated layer" when there is a contrast difference, and as "not having a machining-deteriorated layer" when there is no contrast difference.

In the case of "having a process-altered layer", the depth thereof was measured based on a cross-sectional TEM image.

As a result, no process-altered layer was observed in the SiC wafers of example 3 and example 4.

On the other hand, in the SiC wafer of comparative example 1, a work-affected layer of 12nm was observed on the (0001) surface side, and a work-affected layer of 28nm was observed on the (000-1) surface side.

Further, in the SiC wafer of comparative example 2, a 10nm work-affected layer was observed on the (0001) surface side, and a 43nm work-affected layer was observed on the (000-1) surface side.

From these results, it was found that by combining a flattening step of flattening the SiC wafer using abrasive grains having a modified mohs hardness of less than 15 and an etching step of heating and etching the SiC wafer under Si vapor pressure in the production of the SiC wafer, the SiC wafer from which the affected layer was removed can be produced with a small material loss of 3 μm per surface.

From these results, it was found that by combining a flattening step of flattening the SiC wafer while grinding abrasive grains and an etching step of heating and etching the SiC wafer under Si vapor pressure in the production of the SiC wafer, the SiC wafer from which the affected layer was removed can be produced with a small material loss of 3 μm per surface.

Further, from the results of example 3 and example 4, it is understood that the work-affected layer introduced by the planarization step can be removed by the etching step with a smaller material loss amount of 10 μm or less than that of the prior art.

These results show that by being configured to remove the work-affected layer introduced in the planarization step by the etching step, the material loss can be reduced, whereby more SiC wafers can be produced from one ingot.

Production of SiC wafer of the present invention for solving the fifth problem, and observation and evaluation thereof

SiC wafers of example 5 and example 6 were produced by the following method.

< example 5>

(slicing step)

The single crystal SiC ingot was sliced using a slurry containing diamond abrasive grains having an average abrasive grain diameter of 10 μm to obtain a SiC wafer having a diameter of 6 inches.

(flattening step)

The SiC wafer was polished by using a polishing composition containing B having an average abrasive grain size of 40 μm₄C abrasive grain slurry free abrasive grain mode, at a working pressure of 150g/cm²The surface was flattened under the conditions of a surface plate rotation speed of 15rpm, a head rotation speed of 5rpm, a processing time of 20 minutes, and a processing speed of about 1.0 μm/min.

At this time, B at the end of the planarization step₄The average grain diameter of the C grains was 10 μm.

(etching step)

The SiC wafer after the flattening step was subjected to Si vapor pressure etching under conditions in which the etching amount was 3 μm (the processing time was about 3 minutes, and the processing speed was 1 μm/minute).

< example 6>

(slicing step)

A dicing step was performed under the same conditions as in example 5, and a SiC wafer having a diameter of 6 inches was obtained.

(etching step)

For the obtained SiC wafer, Si vapor pressure etching was performed under the same conditions as in example 5. The etching amount was 3.5. mu.m.

< measurement of stress by SEM-EBSD >

Further, the stresses present in the SiC wafers of example 5 and example 6 before and after the etching step were observed by the SEM-EBSD method. The results are shown in fig. 20 and 21. The section of the SiC wafer cleaved in example 1 and example 2 was measured using a scanning electron microscope under the following conditions.

SEM device: merline manufactured by Zeiss

EBSD analysis: OIM crystal orientation analysis device manufactured by TSL Solutions

Acceleration voltage: 15kV

Current of the probe: 15nA

Step length: 200nm

Depth of reference point R: 20-25 mu m

FIG. 20 is a sectional SEM-EBSD imaged image of example 5, and FIG. 21 is a sectional SEM-EBSD imaged image of example 6.

As shown in (a) in fig. 20 and (a) in fig. 21, lattice strain was observed in the SiC wafers of example 5 and example 6 before the etching step. This is the lattice strain introduced by the rind processing step or the like. In addition, compressive stress was observed.

On the other hand, as shown in (b) in fig. 20 and (b) in fig. 21, after the etching step, the lattice strain of the crystal lattice under the surface with respect to the reference lattice was 0.001% or less, and no lattice strain was observed in the SiC wafers of example 5 and example 6.

This result indicates that the stress in the SiC wafer introduced by the etching step can be removed by the etching step.

If the chemical mechanical polishing process is applied to the SiC wafer in the state where the stress is removed like the SiC wafers of example 5 and example 6, a high-quality SiC wafer having no lattice strain inside and having high flatness can be obtained.

Description of the reference numerals

10 ingot

20 SiC wafer

21 major face

22 back side

23 outer peripheral portion

24 plane of orientation

25 imprinting part

30 working affected layer

31 crack layer

32 strained layer

33 layers of blocks

40 crucible

41 upper container

42 lower container

43 support table

50 high-temperature vacuum furnace

51 main heating chamber

52 preheating chamber

53 Mobile station

54 valve for vacuum forming

55 inert gas injection valve

56 vacuum gauge

57 heater

S10 wafer shape Forming step

S11 ingot shaping step

S12 Crystal orientation Forming step

S13 slicing step

S141 pear peel processing step

S142 planarization step

S15 imprint forming step

S16 chamfering step

S17 planarization step of conventional method

S20 procedure for removing the affected layer

S21 etching step

S22 rough grinding step

S23 finish grinding step

S30 mirror polishing step

S31 mirror finishing step

S32 chemical mechanical polishing step