阅读说明：本技术 基于重金属层磁性隧道结对的自旋轨道矩磁性随机存储器 (Spin orbit torque magnetic random access memory based on heavy metal layer magnetic tunnel junction pair ) 是由 薛晓勇 方晋北 赵晨阳 陈德扬 杨何勇 张洵铭 于 2020-11-20 设计创作，主要内容包括：本发明属于存储器技术领域,具体为一种基于重金属层磁性隧道结对的自旋轨道矩磁性随机存储器。本发明的随机存储器,其存储单元包括：一个重金属导电层、两个磁阻元件和三个开关元件；所述的两个磁阻元件第一层是磁化方向固定的磁性材料层,第二层是非磁性材料层,第三层是磁化方向可变的磁性材料层,这两个磁阻元件均邻接到同一重金属导电层上,组成差分结构。本发明的自旋轨道矩磁性随机存储器,利用一组共用重金属层的互补磁性隧道结构建自旋轨道矩磁性随机存储器的存储单元,差分结构提高其读取裕度,重金属层的共用使面积代价减小,也使写入控制逻辑更为简单。(The invention belongs to the technical field of memories, and particularly relates to a spin orbit torque magnetic random access memory based on a heavy metal layer magnetic tunnel junction pair. The random access memory of the present invention has a memory cell including: one heavy metal conductive layer, two magnetoresistive elements, and three switching elements; the first layer of the two magnetic resistance elements is a magnetic material layer with fixed magnetization direction, the second layer is a non-magnetic material layer, the third layer is a magnetic material layer with variable magnetization direction, and the two magnetic resistance elements are adjacent to the same heavy metal conducting layer to form a differential structure. The spin orbit torque magnetic random access memory utilizes a group of complementary magnetic tunnel junctions sharing the heavy metal layer to construct a storage unit of the spin orbit torque magnetic random access memory, the difference structure improves the reading margin of the storage unit, the sharing of the heavy metal layer reduces the area cost, and the writing control logic is simpler.)

1. A spin orbit torque magnetic random access memory based on a heavy metal layer magnetic tunnel junction pair is characterized in that a storage unit comprises a heavy metal conducting layer, two magnetoresistive elements and three switching elements; wherein:

the first end of the first switch element is connected with a write bit line; the second end of the first switching element is connected with the first end of the heavy metal conducting layer; the control end of the first switch element is connected with a writing line;

the second end of the heavy metal conducting layer is connected with a source line;

the first end of the first magnetic resistance element is connected with the first end of the second switch element; the second end of the first magnetic resistance element is abutted to the middle position between the first end and the second end of the heavy metal conducting layer; the first end of the second magnetic resistance element is connected with the first end of the third switch element; the second end of the second magnetic resistance element is abutted to the middle position between the first end and the second end of the heavy metal conducting layer;

the second end of the second switch element is connected with the first reading bit line; the control end of the second switch element is connected with the read word line;

a second end of the third switching element is connected with a second reading bit line; the control end of the third switching element is connected with the reading word line;

the two magnetoresistive elements of the memory cell constitute a differential circuit, and the value stored in the memory cell is read out by comparing their read currents with each other.

2. The spin-orbit torque magnetic random access memory of claim 1, wherein the heavy metal conductive layer is platinum, tantalum, gold, tungsten or palladium.

3. The spin-orbit torque magnetic random access memory according to claim 1, wherein the magnetoresistive element is composed of three layers, a first layer being a magnetic material layer whose magnetization direction is fixed, a second layer being a non-magnetic material layer, and a third layer being a magnetic material layer whose magnetization direction is variable; the magnetic material layer with the fixed magnetization direction of the magnetic resistance element is used as a first end of the magnetic resistance element, and the magnetic material layer with the variable magnetization direction of the magnetic resistance element is used as a second end of the magnetic resistance element and is abutted to the middle position between the first end and the second end of the heavy metal conducting layer.

4. The spin-orbit-torque magnetic random access memory according to claim 1 or 3, wherein the magnetization directions of the two magnetic material layers whose magnetization directions are fixed are opposite to each other.

5. The spin-orbit torque magnetic random access memory according to claim 1, wherein the first switching element is for controlling on or off of two magnetoresistive element write paths; the switching element is an NMOS transistor.

6. The spin-orbit torque magnetic random access memory according to claim 1, wherein the second switching element is used to control the first magnetoresistive element read path to be turned on or off; the switching element is an NMOS transistor.

7. The spin-orbit torque magnetic random access memory of claim 1, wherein the third switching element is used to control the second magnetoresistive element read path to be turned on or off; the switching element is an NMOS transistor.

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a spin orbit torque magnetic random access memory.

Background

Static Random Access Memory (SRAM) has been the mainstream solution for on-chip embedded memories for the past decades. With the continuous development of the process and the design technology, the number of processor cores integrated on a single integrated circuit is increased, so that the requirements of a single chip on the integration level, the capacity and the bandwidth of the on-chip static random access memory are increased. Therefore, with these increasing requirements, the development of static random access memory is rapid during the decades of 1994-2008: at each new process generation, the cell area of the sram is reduced by half. In recent years, however, this trend has been met with great resistance. The reduction of the process size increases the difficulty of process manufacturing, and random variation of parameters in the manufacturing process causes fluctuation of the threshold voltage of a device, so that the stability of a memory cell is influenced, and a high-density memory array is difficult to have a wide noise margin. This also limits the performance improvement and power consumption reduction of high-density static random access memory, and thus the static random access memory cannot be developed in a given direction. Therefore, finding new memory solutions to replace sram becomes a necessary route to further significantly improve chip performance.

Further, the next generation memory solution is required to have the following four characteristics at the same time: low power consumption, high performance, good compatibility with CMOS standard process and strong scalability. Spin-orbit-torque Magnetic Random Access Memory (SOT MRAM) is thus a competitor, being made non-volatile based on Magnetic Tunnel Junction (MTJ), with very low static power consumption; the read-write path can be optimized independently, and the dynamic power consumption is quite low; the read-write speed is high, the integration is easy, and the CMOS standard process is compatible; in addition, the durability of the sensor is almost unlimited, and the retentivity at normal temperature is over 10 years, so that the sensor has great potential in the fields of sensor networks, Internet of things, big data and the like.

However, the Tunnel Magneto-resistance Ratio (TMR) of the current spin-orbit torque magnetic random access memory is still smaller than that of other resistance random access memories, and the small read margin results in a slow read speed and a high requirement for the accuracy of the read device, thereby affecting the performance of the spin-orbit torque magnetic random access memory. To solve this problem, it is common practice to use a differential circuit to increase the tunnel-to-magnetic resistance ratio by comparing the resistance values of the complementary magnetic tunnel junctions with each other. However, this scheme is very area-expensive and complicated in control logic, uses two magnetic tunnel junctions, four transistors per memory cell, and is controlled by four word lines (two read word lines and two write word lines), two source lines, and two bit lines. How to increase the tunnel magnetic resistance ratio by using the differential circuit and relatively reduce the area cost of the memory cell is a problem to be solved.

Disclosure of Invention

The invention aims to provide a spin orbit torque magnetic random access memory which has large reading margin, small area cost and simple control logic.

The invention provides a spin orbit torque magnetic random access memory, which is based on a shared heavy metal layer magnetic tunnel junction pair. The first switch element has a first end connected to the write bit line, a second end connected to the first end of the heavy metal conductive layer, and a control end connected to the write word line. And the second end of the heavy metal conducting layer is connected with the source line. The first end of the first magneto-resistive element is connected to the first end of the second switching element, and the second end of the first magneto-resistive element is adjacent to a middle position between the first end and the second end of the heavy metal conductive layer. The second magnetoresistive element has a first end connected to the first end of the third switching element and a second end adjacent to an intermediate position between the first end and the second end of the heavy metal conductive layer. The second switch element has a second terminal connected to the first read bit line and a control terminal connected to the read word line. The second end of the third switch element is connected with the second reading bit line, and the control end is connected with the reading word line.

The two magnetoresistive elements of the spin-orbit torque magnetic random access memory cell constitute a differential circuit, and the values stored in the memory cell are read out by comparing the read currents with each other.

The heavy metal conductive layer may be platinum, tantalum, gold, tungsten or palladium.

The two magnetoresistive elements are composed of three layers, the first layer being a magnetic material layer whose magnetization direction is fixed, the second layer being a non-magnetic material layer, and the third layer being a magnetic material layer whose magnetization direction is variable. The magnetic material layer with fixed magnetization direction is used as the first end of the magnetic resistance element, and the magnetic material layer with variable magnetization direction is used as the second end of the magnetic resistance element and is abutted to the middle position between the first end and the second end of the heavy metal conducting layer. The magnetization directions of the two magnetic material layers of which the magnetization directions are fixed are opposite.

The first switching element is used for controlling the on/off of the writing paths of the two magnetoresistive elements, and can be an NMOS transistor.

The second switching element is used for controlling the on/off of the read path of the first magnetoresistive element, and may be an NMOS transistor.

The third switching element is used for controlling the second magnetoresistive element read path to be turned on or off, and may be an NMOS transistor.

According to the specific embodiment provided by the invention, the invention has the following technical effects: the spin orbit torque magnetic random access memory based on the shared heavy metal layer magnetic tunnel junction pair provided by the invention utilizes a group of complementary magnetic tunnel junctions sharing the heavy metal layer to construct a storage unit of the spin orbit torque magnetic random access memory, the reading margin of the storage unit is improved by a differential structure, the area cost is reduced by sharing the heavy metal layer, and the writing control logic is simpler.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a circuit diagram of a hardware implementation of a spin-orbit torque magnetic random access memory storage unit based on a shared heavy metal layer magnetic tunnel junction pair according to the present invention;

FIG. 2 is a memory array based on the spin-orbit torque MRAM memory cell described above.

Reference numerals in the figures

100 is a circuit diagram of a hardware implementation of the spin orbit torque magnetic random access memory storage unit based on the magnetic tunnel junction pair of the common heavy metal layer; 110 is a first magnetoresistive element; 110 a is a magnetic material layer in which the magnetization direction of the first magnetoresistive element is fixed; 110 b is a non-magnetic material layer of the first magnetoresistive element; 110 c is a magnetic material layer in which the magnetization direction of the first magnetoresistive element is changeable; 111 a second magnetoresistive element; 112 is a heavy metal conductive layer; 120 is a first switching element NMOS transistor; 121 is a second switching element NMOS transistor; 122 is a third switching element NMOS transistor; 130 is a port to which a write bit line is connected; 131 is a port connected with a write word line; 132 is a port connected to a read word line; 133 is a port connecting a first read bit line; 134 is a port connecting a second read bit line; 135 are ports to which source lines are connected.

200 is a memory array based on the spin orbit torque magnetic random access memory; 210 is a write word line connecting the first row of memory cells; 211 is a write word line connecting the memory cells of the second row; 212 is a write word line connecting the Nth row of memory cells; 220 is a read word line connecting the memory cells of the first row; 221 is a read word line connecting the memory cells in the second row; 222 is a read word line connecting the memory cells in the Nth row; 230 is a source line connecting the memory cells of the first row; 231 is a source line connecting the memory cells of the second row; 232 is the source line connecting the memory cells in the Nth row; 240 is a write bit line connecting the memory cells of the first column; 241 is a write bit line connecting the memory cells of the second column; 242 is a write bit line connecting the memory cells in the Mth column; 250 is a first read bit line connecting the memory cells in the first column; 251 a first read bit line connected to a second column of memory cells; 252 is a first read bit line connecting the memory cells in the Mth column; 260 is a second read bit line connecting the memory cells in the first column; 261 is a second read bit line connecting the memory cells in the second column; 262 is a second read bit line connecting the memory cells in the Mth column; 270 is the sense amplifier for the first column of memory cells; 271 is the sense amplifier of the second column of memory cells; 272 is the sense amplifier for the mth column of memory cells.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a spin orbit torque magnetic random access memory based on a shared heavy metal layer magnetic tunnel junction pair.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

FIG. 1 is a circuit diagram of a hardware implementation of a spin-orbit torque magnetic random access memory cell based on a common heavy metal layer magnetic tunnel junction pair according to the present invention. As shown in fig. 1, when it is desired to write a "1" (or a "0", depending on the magnetic field applied to the magnetoresistive element) into the memory cell, a positive voltage VDD is applied to the write word line, a positive voltage VWP is applied to the write bit line, and a zero voltage is applied to the source line; when it is desired to write a "0" (or a "1", depending on the magnetic field applied to the magnetoresistive element) into the memory cell, a positive voltage VDD is applied to the write word line, a negative voltage VWN is applied to the write bit line, and a zero voltage is applied to the source line; when data in the memory cell needs to be read, a positive voltage VDD is applied to the read word line, a read voltage VREAD is applied to the two read bit lines, a zero voltage is applied to the source line, and the data in the target memory cell can be obtained by comparing the currents on the two read bit lines, namely comparing the values stored in the two magnetoresistive elements.

FIG. 2 is a memory array based on the spin-orbit torque MRAM memory cell described above. As shown in fig. 2, a row of the memory array has M memory cells, and the data stored in the M memory cells form a word; a column of the memory array has N memory cells. If the write operation for a specific word is to be completed, a positive voltage VDD is applied to the corresponding write word line, and a positive voltage VWP or a negative voltage VWN is applied to all M write bit lines, and a zero voltage is applied to all M source lines; if the read operation for a specific word is to be completed, positive voltage VDD is applied to the corresponding read word line, positive voltage VREAD is applied to all 2M read bit lines, and zero voltage is applied to all M source lines, after which the M sense amplifiers compare the current levels of the corresponding two read bit lines to obtain the values for M memory cells.