阅读说明：本技术 半导体装置的形成方法 (Method for forming semiconductor device ) 是由 李健玮 宋学昌 李彦儒 林俊池 徐梓翔 杨丰诚 于 2020-04-20 设计创作，主要内容包括：此处提供半导体装置与半导体装置的形成方法,且半导体装置包括的源极/漏极区具有V形下表面并延伸于与栅极堆叠相邻的栅极间隔物之下。在一实施例中,方法包括形成栅极堆叠于鳍状物上；形成栅极间隔物于栅极堆叠的侧壁上；由非等向的第一蚀刻工艺蚀刻鳍状物,以形成与栅极间隔物相邻的第一凹陷；由第二蚀刻工艺蚀刻鳍状物,以自第一凹陷移除蚀刻残留物,且第二蚀刻工艺与第一蚀刻工艺采用的蚀刻剂不同；由非等向的第三蚀刻工艺蚀刻第一凹陷的表面以形成第二凹陷,第二凹陷延伸至栅极间隔物之下且具有V形下表面,且第三蚀刻工艺与第一蚀刻工艺采用的蚀刻剂不同；以及外延形成源极/漏极区于第二凹陷中。(Semiconductor devices and methods of forming semiconductor devices are provided herein and include source/drain regions having V-shaped lower surfaces and extending under gate spacers adjacent to a gate stack. In one embodiment, a method includes forming a gate stack on a fin; forming a gate spacer on sidewalls of the gate stack; etching the fin by a non-isotropic first etch process to form a first recess adjacent to the gate spacer; etching the fin by a second etching process to remove the etching residues from the first recess, wherein the second etching process uses a different etchant than the first etching process; etching the surface of the first recess by a non-isotropic third etching process to form a second recess, the second recess extending below the gate spacer and having a V-shaped lower surface, the third etching process using a different etchant than the first etching process; and epitaxially forming source/drain regions in the second recesses.)

1. A method of forming a semiconductor device, comprising:

forming a gate stack on a fin extending from a substrate;

forming a gate spacer on sidewalls of the gate stack;

etching the fin by a first etch process to form a first recess adjacent the gate spacer, wherein the first etch process is non-isotropic;

etching the fin by a second etching process to remove an etching residue from the first recess, wherein the second etching process uses a different etchant than the first etching process;

etching the surface of the first recess by a third etching process to form a second recess extending below the gate spacer in a direction perpendicular to the major surface of the substrate, the second recess having a V-shaped lower surface, wherein the third etching process is non-isotropic along the crystallographic plane of the substrate and the third etching process uses a different etchant than the first etching process; and

a source/drain region is epitaxially formed in the second recess.

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to improved source/drain regions and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate and lithographically patterning the various material layers to form electronic components and cells thereon.

The semiconductor industry continues to shrink the minimum feature size to continuously improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, or the like) to allow more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems arise that need to be solved.

Disclosure of Invention

A method of forming a semiconductor device according to an embodiment of the invention includes forming a gate stack on a fin extending from a substrate; forming a gate spacer on sidewalls of the gate stack; etching the fin by a first etch process to form a first recess adjacent the gate spacer, wherein the first etch process is non-isotropic; etching the fin by a second etching process to remove the etching residues from the first recess, wherein the second etching process uses a different etchant than the first etching process; etching the surface of the first recess by a third etching process to form a second recess extending below the gate spacer in a direction perpendicular to the major surface of the substrate, the second recess having a V-shaped lower surface, wherein the third etching process is non-isotropic along the crystallographic plane of the substrate and the third etching process uses a different etchant than the first etching process; and epitaxially forming source/drain regions in the second recesses.

An embodiment of the present invention provides a semiconductor device, including: a fin extending from a substrate; a gate stack on the fin; a gate spacer on a sidewall of the gate stack; and a source/drain region in the fin adjacent to the gate spacer, the source/drain region having a V-shaped lower surface in a (111) crystallographic plane, the source/drain region extending below the gate spacer in a direction parallel to the major surface of the substrate and in a (110) crystallographic plane, wherein the source/drain region extends below the gate spacer by at least 4nm to 8nm in a depth of 20nm to 30nm and in a direction parallel to the major surface of the substrate.

A method for forming a semiconductor device according to an embodiment of the present invention includes: forming a fin in a semiconductor substrate; forming a dummy gate stack on the fin; etching the fin adjacent to the dummy gate stack by a first etching process to form a first recess, wherein the first etching process anisotropically etches the fin, and the etching direction is perpendicular to the main surface of the semiconductor substrate; removing etching residues from the first recess after etching the fin using the first etching process; etching the first recess using a second etch process to form a second recess, the second etch process being non-isotropic along the (111) crystallographic plane and along the (110) crystallographic plane; forming source/drain regions in the second recesses; and replacing the dummy gate with a gate stack.

Drawings

Figure 1 is a three-dimensional view of a finfet in some embodiments.

Fig. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 14A, 14B, 14C, 14D, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 18C, 19A, 19B, 20A, and 20B are cross-sectional views of intermediate stages in forming a fin field effect transistor in some embodiments.

Fig. 13A and 13B are schematic diagrams of systems for performing a plasma cleaning process in some embodiments.

Description of reference numerals:

θ₁: angle of rotation

A-A, B-B, C-C: section plane

D₁: distance between two adjacent plates

D₂,D₃: depth of field

D₄: diameter of

50: substrate

50N, 50P: region(s)

51: separation line

52: fin

54: insulating material

56: shallow trench isolation region

58: channel region

60: virtual dielectric layer

62: dummy gate layer

64: mask layer

72: virtual grid

74: shade cover

80: gate seal spacer

82: epitaxial source/drain regions

86: gate spacer

87: contact etch stop layer

88: first interlayer dielectric layer

89: region(s)

90,102,103: depressions

92: gate dielectric layer

94: grid electrode

94A: cushion layer

94B: work function adjusting layer

94C: filling material

96: grid mask

104: etching residue

108: second interlayer dielectric layer

110: gate contact

112: source/drain contact

200: etching system

203: process chamber

205: first supply system

207: second supply system

209: gas supply device

211: air flow controller

213: gas controller

215: control unit

219: manifold

221: catheter tube

223: plasma generating chamber

225: shell body

227: exhaust outlet

229: vacuum pump

231: sprinkler head

233: gas distribution plate

235,235a,235b,235 c: opening of the container

237: mounting platform

239: a first electrode

241: second RF generator

243: first radio frequency generator

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. In addition, the structures of the embodiments of the present invention are formed on, connected to, and/or coupled to another structure, and the structures may directly contact the other structure, or additional structures may be formed between the structures and the other structure (i.e., the structures do not contact the other structure). Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

Various embodiments provide improved source/drain regions for semiconductor devices and methods of forming the same. The source/drain regions may be formed by etching recesses in the semiconductor fin using an anisotropic etch process, removing etch residues from the recesses using an ammonia-based etch, and expanding the recesses using a hydrogen-based plasma etch. The completed recess may have a V-shaped lower surface and may extend under the gate spacers. Source/drain regions are then formed in the recesses. Semiconductor devices including such source/drain regions may have improved difference in on-current and leakage current (e.g., increased on-current and reduced leakage current), reduced drain induced barrier lowering effects, reduced device defects, and overall improved device performance.

Figure 1 is a three-dimensional view of a finfet in some embodiments. The finfet includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation regions 56 are located in substrate 50, and fins 52 are formed between adjacent shallow trench isolation regions 56 and protrude above shallow trench isolation regions 56. Although the shallow trench isolation regions 56 are shown separately from the substrate 50, the term "substrate" as used herein may be considered a semiconductor substrate alone, or a semiconductor substrate containing isolation regions. Furthermore, although fin 52 is shown as a single continuous material such as substrate 50, fin 52 and/or substrate 50 may comprise a single material or a plurality of materials. In this case, fin 52 may be considered to be the portion extending between adjacent sti regions 56.

Gate dielectric 92 is along the sidewalls and top surface of fin 52 and gate 94 is situated on gate dielectric 92. Epitaxial source/drain regions 82 are located on both sides of fin 52 relative to gate dielectric 92 and gate 94. Fig. 1 also shows a reference section used in subsequent figures. Cross-section a-a is along the longitudinal axis of gate 94 and is oriented perpendicular to the direction of current flow between epitaxial source/drain regions 82 of the finfet. Cross-section B-B is perpendicular to cross-section a-a and along the longitudinal axis of fin 52 and is in the direction of current flow between epitaxial source/drain regions 82 of the finfet. Section C-C is parallel to section a-a and extends through the source/drain regions of the finfet. Subsequent figures may be based on these reference profiles to clarify the drawings.

Some embodiments described herein employ a gate post-processing method for forming a finfet. In other embodiments, a gate first process may be employed. Furthermore, some embodiments may be used in planar devices such as planar field effect transistors.

Fig. 2-12B and 14A-20B are cross-sectional views of intermediate stages of forming a finfet in some embodiments. Fig. 2-7 are along the reference section a-a shown in fig. 1, with the difference that a plurality of fins or finfet transistors are present. Fig. 8A, 9A, 10A, 11A, 12A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A are along a reference section a-a shown in fig. 1, while fig. 8B, 9B, 10B, 11B, 12B, 14B, 15B, 16B, 17B, 18C, 19B, and 20B are along a similar section B-B shown in fig. 1, with the difference being a plurality of fins or fin field effect transistors. Fig. 14C and 14D are along the reference section C-C shown in fig. 1, with the difference being a plurality of fins or finfet transistors.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer may be provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multilayer substrates or compositionally graded substrates may also be employed. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), a semiconductor alloy (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide), or a combination thereof.

The substrate 50 has a region 50N and a region 50P. The region 50N may be used to form an N-type device such as an N-type metal oxide semiconductor transistor (e.g., an N-type finfet). The region 50P may be used to form a P-type device such as a P-type transistor (e.g., a P-type finfet). The region 50N is physically separated from the region 50P (e.g., as shown by separation line 51), and any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) may be present between the regions 50N and 50P.

In fig. 3, fin 52 is formed on substrate 50. Fin 52 may be a semiconductor ribbon. In some embodiments, a trench may be etched into substrate 50 to form fin 52 in substrate 50. The etching may be any acceptable etching process, such as reactive ion etching, neutral beam etching, the like, or combinations thereof. The etching may be anisotropic.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes that produce a pattern pitch that is smaller than that obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. Spacers are formed along the patterned sacrificial layer sides using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may be used to pattern the fin. In some embodiments, a mask (or another layer) may remain over fins 52.

In fig. 4, insulative material 54 is formed over substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide such as silicon oxide, nitride, the like, or combinations thereof, and may be formed by high density plasma chemical vapor deposition, flowable chemical vapor deposition (such as depositing a chemical vapor deposition-based material in a remote plasma system and then curing the material to convert it to another material such as an oxide), the like, or combinations thereof. Other insulating materials formed by any acceptable process may also be used. In the illustrated embodiment, insulative material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, insulative material 54 is formed such that excess insulative material 54 covers fin 52. Although the insulating material 54 in the figures is a single layer, some embodiments may employ multiple layers of insulating material 54. For example, some embodiments may first form a liner layer (not specifically shown) along the surfaces of substrate 50 and fins 52. A fill material may then be formed on the liner layer as described above.

In fig. 5, a removal process is applied to insulative material 54 to remove excess insulative material 54 on fin 52. In some embodiments, a planarization process such as chemical mechanical polishing, etch back process, combinations thereof, or the like may be employed. The planarization process exposes fin 52 so that after the planarization process is complete, fin 52 is flush with the upper surface of insulative material 54. In embodiments where a mask remains over fin 52, the planarization process may expose the mask or remove the mask so that the top surface of fin 52 is flush with the top surface of insulative material 54 after the planarization process is complete.

In fig. 6, insulating material 54 is recessed to form shallow trench isolation regions 56. Upper portions of fins 52 in regions 50N and 50P protrude from between adjacent shallow trench isolation regions 56 due to recessing of insulating material 54. Furthermore, the upper surface of the sti region 56 may have a flat surface, such as shown, a convex surface, a concave surface (e.g., a dish), or a combination thereof. The upper surface of the shallow trench isolation region 56 may be planar and/or recessed (as a result of an appropriate etch). The method of recessing shallow trench isolation regions 56 may employ an acceptable etch process, such as an etch process that is selective to insulative material 54 (which etches the insulative material at a rate that is greater than the material of fin 52). For example, a method of removing oxide may employ dilute hydrofluoric acid.

The processes illustrated in figures 2-6 are only one example of how fins 52 may be formed. In some embodiments, the method of forming fin 52 may be an epitaxial growth process. For example, a dielectric layer may be formed on the upper surface of the substrate 50 and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form fin 52. Furthermore, heteroepitaxial structures in some embodiments may be used for fin 52. For example, fin 52 in figure 5 may be recessed, while other materials different from the material of fin 52 may be epitaxially grown on recessed fin 52. In these embodiments, fin 52 includes a recessed material and the epitaxially grown material is located on the recessed material. In another embodiment, a dielectric layer may be formed on the upper surface of the substrate 50 and trenches etched through the dielectric layer. A heteroepitaxial structure of a material different from that of substrate 50 may then be epitaxially grown in the trench and the dielectric layer recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fin 52. In embodiments where a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may omit a prior or subsequent implant. Although in-situ doping and implant doping may also be used in combination.

Furthermore, there are advantages to having a material grown in regions 50N (e.g., N-type metal oxide semiconductor regions) that is different from the material in regions 50P (e.g., P-type metal oxide semiconductor regions). In various embodiments, the composition of the upper portion of fin 52 may be silicon germanium (Si)_xGe_1-xWhere x may be 0 to 1), silicon carbide, pure or substantially pure germanium, a group III-V semiconductor compound, a group II-VI semiconductor compound, or the like. For example, forming III-V semiconductorsPossible materials for the compound include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, or the like.

In fig. 6, appropriate wells (not shown) may also be formed in fin 52 and/or substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well (or N-well) may be formed in the region 50N and the region 50P.

In embodiments having different well morphologies, a photoresist or other mask (not shown) may be used to achieve different implantation steps for regions 50N and 50P. For example, a photoresist may be formed on shallow trench isolation regions 56 and fins 52 in region 50N. The photoresist is patterned to expose a region 50P (e.g., a pmos region) of the substrate 50. The photoresist may be formed by spin-on coating techniques, and the photoresist may be patterned by acceptable photolithography techniques. Once the photoresist is patterned, an implant of N-type impurities may be performed in the region 50P, and the photoresist may serve as a mask to substantially prevent the N-type impurities from being implanted into the region 50N (e.g., an N-type mos region). The n-type impurity may be phosphorus, arsenic, antimony, or the like, implanted into the region at a concentration of less than or equal to 10¹⁸cm^-3E.g. between about 10¹⁶cm^-3To about 10¹⁸cm^-3In the meantime. The photoresist may be removed after implantation and the removal process may be an acceptable ashing process.

After implanting region 50P, a photoresist may be formed on sti regions 56 and fin 52 in region 50P. The photoresist is patterned to expose regions 50N (e.g., N-type metal oxide semiconductor regions) of the substrate 50. The photoresist may be formed by spin-on coating techniques, and the photoresist may be patterned by acceptable photolithography techniques. Once the photoresist is patterned, a P-type impurity implant may be performed in the region 50N, and the photoresist may serve as a mask to substantially prevent the P-type impurity implant into the region 50P (e.g., a P-type mos region). The p-type impurity may be boron, boron fluoride, indium, or the like, which is implanted into the regionConcentration less than or equal to 10¹⁸cm^-3E.g. between about 10¹⁶cm^-3To about 10¹⁸cm^-3In the meantime. The photoresist may be removed after implantation and the removal process may be an acceptable ashing process.

After implanting the region 50N and the region 50P, an anneal may be performed to repair the implant damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material may be doped in situ when growing the epitaxial fin, which may omit implantation. However, in-situ doping and implant doping may be used in combination.

In fig. 7, dummy dielectric layer 60 is formed on fin 52. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, combinations thereof, or the like, and the dummy dielectric layer 60 may be deposited or thermally grown according to acceptable techniques. Dummy gate layer 62 is formed on dummy dielectric layer 60 and mask layer 64 is formed on dummy gate layer 62. Dummy gate layer 62 may be deposited over dummy dielectric layer 60 and then chemical mechanical polishing (cmp) may be used to planarize dummy gate layer 62. A mask layer 64 may be deposited over dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material, which may be amorphous silicon, polysilicon, poly-silicon-germanium, metal nitride, metal silicide, metal oxide, or metal. The dummy gate layer 62 may be deposited by physical vapor deposition, chemical vapor deposition, sputter deposition, or other techniques known in the art for depositing selected materials. The dummy gate layer 62 may be comprised of other materials that have a high etch selectivity when etching the isolation region. For example, the mask layer 64 may comprise silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed in the regions 50N and 50P. Note that dummy dielectric layer 60 only covers fin 52 in the figures, but this configuration is for illustration purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the sti regions 56 (extending between the dummy gate layer 62 and the sti regions 56).

Fig. 8A-12B and 14A-20B illustrate various additional steps in forming the device of an embodiment. Fig. 8A to 12B and fig. 14A to 20B show the structure in the region 50N and the region 50P. For example, the structures shown in fig. 8A-12B and 14A-20B may be used in the region 50N and the region 50P. If there is any difference in the structures of the region 50N and the region 50P, the differences will be described with reference to the drawings.

In fig. 8A and 8B, the mask layer 64 (see fig. 7) may be patterned using acceptable photolithography and etching techniques to form the mask 74. The pattern of mask 74 may be transferred to dummy gate layer 62 using an acceptable etch technique to form dummy gate 72. In some embodiments, the pattern of mask 74 may also be transferred to dummy dielectric layer 60. Dummy gates 72 cover respective channel regions 58 of fins 52. The pattern of mask 74 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The vertical direction of dummy gate 72 may also be substantially perpendicular to the vertical direction of the respective epitaxial fin.

In fig. 8A and 8B, gate seal spacers 80 may be formed on dummy gate 72, mask 74, and/or the exposed surface of fin 52. A thermal oxidation or deposition may be followed by an anisotropic etch to form gate seal spacers 80. The composition of the gate seal spacers 80 may be silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the gate seal spacers 80 are formed, an implant for lightly doped source/drain regions may be performed. In various device type embodiments, a mask, such as a photoresist, may be formed over region 50N and exposing region 50P, similar to the implantation described above with reference to fig. 6, and an impurity of appropriate type, such as P-type, may be implanted into the exposed fins 52 in region 50P. The mask can then be removed. A mask, such as a photoresist, may be formed over the regions 50P and exposing the regions 50N, and an appropriate dopant profile (e.g., N-type) may be implanted into the exposed fins 52 in the regions 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source/drain region may be about 10¹⁵cm^-3To about 10¹⁹cm^-3. Annealing may be used to repair implanted damage and to activate implanted impurities.

In fig. 9A and 9B, gate spacers 86 are formed on gate seal spacers 80 along sidewalls of dummy gate 72 and mask 74. The gate spacers 86 may be formed by conformably depositing an insulating material followed by anisotropically etching the insulating material. The insulating material of the gate spacers 86 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or the like.

It is noted that the above generally describes the process of forming the spacers and lightly doped source/drain regions. Other processes and sequences may be used. For example, fewer or more spacers or a different sequence of steps may be employed, such as the gate seal spacer 80 may not be etched prior to forming the gate spacer 86 to result in an L-shaped gate seal spacer, spacers may be formed and removed, and/or the like. In addition, different structures or steps may be used to form the n-type device and the p-type device. For example, lightly doped source/drain regions for n-type devices may be formed before the gate seal spacers 80 are formed, and lightly doped source/drain regions for p-type devices may be formed after the gate seal spacers 80 are formed.

Fig. 10A-12B illustrate a process for forming a recess 102 (see fig. 12B) in fin 52 between adjacent dummy gates 72. In fig. 10A and 10B, a recess 103 is formed in fin 52. The recess 103 may extend between adjacent gate spacers 86. The etch process for recess 103 may employ a suitable etch process such as an anisotropic dry etch process employing gate spacer 86, gate seal spacer 80, and mask 74 as a combined mask. In some embodiments, the method of etching the recesses 103 may employ reactive ion etching, neutral beam etching, a combination thereof, or the like. In some embodiments where reactive ion etching is used to form the recesses 103, process parameters such as process gas mixture, bias voltage, or RF power may be selected such that the etching is primarily physical etching, such as ion bombardment, rather than chemical etching, such as radical etching via chemical reaction. In some embodiments, the bias voltage may be increased to increase the ion energy used for the ion bombardment process and increase the physical etch rate. Since the physical etch is anisotropic and the chemical etch is isotropic, the etch rate of this etch process is greater in the vertical direction than in the lateral direction. In some embodiments, the anisotropic etch process may be performed using a process gas mixture containing methane fluoride, methane, hydrogen bromide, oxygen, argon, combinations thereof, or the like.

As shown in fig. 10B, the recess 103 may have a U-shaped lower surface. After etching the recesses, etching residues 104 may remain on the surfaces of the recesses 103. The etch residue 104 may include native oxide formed along the surface of the recess 103 as well as carbon residue. The thickness of the etch residue 104 may be about 0.1nm to about 1 nm. After the formation of epitaxial source/drain regions 82, if etch residues 104 are present in the completed device, resistance may increase and cause defects. As such, the etching residues 104 need to be removed.

In fig. 11A and 11B, a first etch process may be employed to remove etch residues 104 from the recesses 103. In some embodiments, the first etching process may employ ammonia, nitrogen trifluoride, combinations thereof, or the like, and may include a carrier gas such as helium or the like. In some examples, the first etching process may reduce or remove carbon residues and native oxide of the etching residues formed on the sidewalls and/or bottom surface of the recess 103. The flow rate of the ammonia gas for the first etching process may be about 100sccm to about 200sccm, the flow rate of the nitrogen trifluoride for the first etching process may be about 10sccm to about 50sccm, and the flow rate of the carrier gas for the first etching process may be about 100sccm to about 500 sccm. The temperature of the first etching process may be about 100 ℃ to about 200 ℃. The pressure of the first etching process is about 1Torr to about 5 Torr. The first etch process is for a time sufficient to physically clean the etch residues 104 from the recesses 103. For example, the first etch process of some embodiments takes about 10 seconds to about 50 seconds. The short first etching process reduces the risk of damaging the profile of the recess 103 or the dummy gate 72 during the first etching process. The first etching process may use different etchants and different etching parameters than those used to form the recesses 103 as described in fig. 10A and 10B. Removing the etch residues 104 may reduce the resistance of the subsequently formed epitaxial source/drain regions 82 and reduce defects in the final device containing the epitaxial source/drain regions 82.

In fig. 12A and 12B, a second tool is used to expand the recess 103 to form the recess 102. Fin 52 is exposed to a second etch process to expand recess 103. The second etch process exposes fin 52 to hydrogen radicals (H) to remove portions of fin 52. Exposing fins 52 to hydrogen radicals may increase the hydrogen concentration in fins 52 such that the hydrogen concentration in fins 52 adjacent to recess 102 after exposing fins 52 to the second etch process is about 5x 10¹⁸Atom/cm³To about 5x 10¹⁹Atom/cm³. For example, the hydrogen radicals may be formed by flowing hydrogen gas into a plasma generation chamber (such as plasma generation chamber 223 shown in fig. 13A) and igniting a plasma in plasma generation chamber 223. In some embodiments, an additional gas, such as argon, may be ignited in the plasma generation chamber 223. In some embodiments, the substrate 50 may be placed into a process chamber (e.g., the process chamber 203 shown in fig. 13A), and the plasma generation chamber 223 may be a separate chamber coupled to the process chamber 203. In this manner, the plasma generated may be a remote plasma. An example of a system for performing the second etching process will be described below with reference to fig. 13A and 13B. The tool performing the second etching process may be the same as or different from the tool performing the first etching process. In some embodiments, the first etching process and the second etching process may be performed using the same etchant and process parameters. In addition, the etchant and process parameters used for performing the first etching process and the second etching process may be different from the etchant and process parameters used for forming the recess 103, as described in conjunction with fig. 10A and 10B. In other embodiments, a first etch process may optionally be performed, and a second etch process may be employed to remove etch residues 104 and expand recess 103 to form recess 102.

In the second etching process, the flow rate of hydrogen into the plasma generation chamber (e.g., the plasma generation chamber 223 shown in fig. 13A) may be about 50 seem to about 200 seem, and the flow rate of carrier gas into the plasma generation chamber may be about 100 seem to about 500 seem. The power applied to the plasma generation chamber may be about 20W to about 400W, and the frequency may be greater than or equal to about 13.56 MHz. The pressure of the second etch process performed in the process chamber, such as the process chamber 203 shown in fig. 13A, may be about 0.1Torr to about 1Torr, and the pressure may be about 250 c to about 450 c. The second etching process may be performed in the process chamber for a time period ranging from about 10 seconds to about 200 seconds.

In some embodiments, the hydrogen radicals of the second etch process more readily etch some crystalline planes of the semiconductor material of fin 52, and thus may be non-isotropic along the crystalline planes. For example, in embodiments in which the material of fin 52 is silicon, hydrogen radicals may selectively etch the (100) plane rather than the (111) plane or the (110) plane. In some embodiments, the etch rate of the (100) plane may be about 3 times the etch rate of the (111) plane. Due to the hydrogen radical etch selectivity at the second etch process, the etch is slower or even stopped along the (111) plane or the (110) plane of the silicon.

As fig. 12B accommodates, the recess 102 may have a V-shaped lower surface. An angle θ between a lower surface of one of the recesses 102 and a line formed on a major surface of the substrate 50₁And may be about 55 deg. to about 65 deg. (e.g., about 60 deg.). Recess 102 extends a distance D below gate spacer 86₁And may be about 4nm to about 8nm, such as about 6 nm. Distance D₁At a depth D₂(below the upper surface of fin 52) has a maximum from about 20nm to about 30nm (e.g., about 25 nm). Depth D of recess 102₃And may be about 40nm to about 50nm (e.g., about 45 nm).

Recess 102 extends under gate spacer 86 and has a V-shaped lower surface to allow more dopant to diffuse from subsequently formed epitaxial source/drain regions 82 to channel region 58. This can reduce the channel resistance R_ch. In addition, the recess 102 extending under the gate spacer 86 in the (110) direction improves device performance, avoids drain-induced energy barrier lowering, and improves the difference between the on-current and the leakage current (e.g., increases the on-current and decreases the leakage current).

The etching system 200 shown in fig. 13A and 13B may be used to perform a second etching process. The etching system 200 includes a plasma generation chamber 223 coupled to a process chamber 203. In one embodiment, the etching system 200 receives a first process gas (e.g., hydrogen) from the first supply system 205 and/or a second process gas from the second supply system 207. The first supply system 205 and the second supply system 207 may cooperate with each other to supply a plurality of different process gases to the process chamber 203 where the substrate 50 is placed. The first feed system 205 and the second feed system 207 may have similar physical components to each other. In other embodiments, fewer or more feed systems may be employed.

In one embodiment, the first supply system 205 and the second supply system 207 may each include a gas supply 209 and a gas flow controller 211. The gas supply 209 may be a vessel, such as a gas tank, which may be located near or remote from the process chamber 203. In other embodiments, the gas supply 209 facilitates independently preparing and supplying the process gas flow controller 211. Any suitable source may be employed as the gas supply 209 for the process gas, and all such sources are fully included within the scope of the embodiments.

The gas supplier 209 may supply a desired process gas to the gas flow controller 211. The gas flow controller 211 may be used to control the flow of process gases to the gas controller 213 and ultimately to the plasma generation chamber 223, thereby helping to control the pressure in the plasma generation chamber 223. The gas flow controller 211 may be a proportional valve, a regulator valve, a needle valve, a pressure regulator, a mass flow controller, combinations thereof, or the like. However, any suitable method may be employed to control and regulate the flow of process gases, and such components and methods are fully included within the scope of the embodiments.

Although the first supply system 205 and the second supply system 207 are described herein as having the same components, this is merely an illustrative example and is not intended to limit the embodiments to any mode. Any type of suitable process gas supply system may be substituted, including any variety and number of individual components, which may or may not be the same as any other supply system in the etching system 200. These supply systems are fully included within the scope of the embodiments.

In various embodiments, the process gas may comprise a mixture of a precursor and a carrier gas. In embodiments where the precursor is stored in a solid or liquid state, the gas supply 209 may store a carrier gas and may direct the carrier gas into a precursor tank (not shown) that stores the precursor in a solid or liquid state. The precursor is volatilized or sublimated into a gaseous portion in a precursor canister prior to being delivered to the gas controller, and is then propelled and carried with a carrier gas. Any suitable method and combination of units may be employed to provide the precursor, and such combination of units is fully included within the scope of the embodiments. The carrier gas may comprise nitrogen, helium, argon, xenon, combinations thereof, or the like, although other suitable carrier gases may be used instead.

The first supply system 205 and the second supply system 207 may supply respective process gases to the gas controller 213. The gas controller 213 is connected to and isolates the first supply system 205 and the second isolation system 207 from the plasma generation chamber 223 to supply the required process gases to the plasma generation chamber 223. The gas controller 213 may include devices such as valves, sensors, and the like to control the supply rate of each process gas, and may receive instructions from the control unit 215 to control the gas controller 213.

The gas controller 213 may receive instructions from the control unit 215 to open or close valve elements, connect one or more of the first supply system 205 or the second supply system 207 to the plasma generation chamber 223, and introduce desired process gases into the plasma generation chamber 223 via the manifold 219.

In some embodiments, the plasma generation chamber 223 may include a transformer coupled plasma generator, and may be a coil. The coil may be coupled to a first rf generator 243 for providing power to the plasma generation chamber 223 to ignite a plasma when introducing the process and/or carrier gases. Although the plasma generation chamber 223 described above includes a transformer-coupled plasma generator, embodiments are not limited to a transformer-coupled plasma generator. Rather, the plasma may be generated using any suitable method, such as inductively coupled plasma systems instead, magnetically assisted reactive ion etching, electron cyclotron resonance, remote plasma generators, or the like. All such methods are fully encompassed within the scope of the embodiments.

The process chamber 203 further comprises a showerhead 231 connected to the plasma generation chamber 223 via a conduit 221. The conduit 221 may transport plasma products (such as hydrogen radicals h. or other plasma products) from the plasma generation chamber 223 into the showerhead 231. The showerhead 231 may be used to disperse plasma products into the process chamber 203 and may be designed to uniformly disperse plasma products to minimize unwanted process conditions (from non-uniform dispersion). In one embodiment, the showerhead 231 may comprise a gas distribution plate 233, which may have a plurality of openings 235 to distribute plasma products into the process chamber 203.

Figure 13B illustrates one embodiment of the sprinkler head 231. The showerhead 231 shown in fig. 13B may be configured to uniformly distribute plasma products (e.g., hydrogen radicals) in the process chamber 203. In prior art showerheads, the distribution of plasma products exiting from the conduit and entering the showerhead remains concentrated near the axis of the alignment conduit. For example, the plasma products are concentrated near the center of the showerhead. Due to the uneven distribution of plasma products away from the showerhead, the plasma products may impinge unevenly on the substrate, such as substrate 50, thereby causing uneven etching or cleaning during the second etching process. As such, the showerhead 231 is provided to more evenly distribute the plasma products striking the substrate 50.

In FIG. 13B, the gas distribution plate 233 includes openings 235 that include three sizes of openings 235a,235B, and 235 c. The diameter of the openings 235 gradually increases from the center of the gas distribution plate 233 toward the edge of the gas distribution plate 233, and the distribution of the openings decreases from the center of the gas distribution plate 233 toward the edge of the gas distribution plate 233. As shown in FIG. 13B, the opening 235a may be located in the center of the gas distribution plate 233 and have a smallest diameter, the opening 235B may surround the opening 235a and have a medium diameter, and the opening 235c may surround the opening 235B and have a largest diameter. Opening 235a has a diameter of about 5mm to about 15mm (e.g., about 10mm), opening 235b has a diameter of about 25mm to about 35mm (e.g., about 30mm), and opening 235c has a diameter of about 40mm to about 60mm (e.g., about 50 mm). Further, the distribution of openings 235a is larger than the distribution of openings 235b, and the distribution of openings 235b is larger than the distribution of openings 235 c. For example, the distribution of openings 235a may be about 4 openings/cm²To about 8 openings/cm²The distribution of openings 235b may be about 2 openings/cm²To about 6 openings/cm²And the distribution of the openings 235c may be about 1 opening/cm²To about 4 openings/cm². In some embodiments, the diameter D of the gas distribution plate 233₄And may be about 100mm to about 200 mm. Openings 235a may be located in a circle having a diameter of up to about 20mm, openings 235b may be located in a ring having an inside diameter of about 20mm to about 50mm and an outside diameter of about 50mm to about 80mm, and openings 235c may be located in a ring having an inside diameter of about 80mm to about 130mm and an outside diameter of about 130mm to about 180 mm.

The larger size of the openings 235c near the edge of the gas distribution plate 233 allows hydrogen radicals in the showerhead 231 to leave the showerhead 231 closer to the edge of the gas distribution plate 233. The smaller size of the openings 235c near the center of the gas distribution plate 233 allows plasma products in the showerhead 231 to exit the showerhead 231 in a smaller amount near the center of the gas distribution plate 233. In addition, the distribution of the openings 235a near the center of the gas distribution plate 233 is larger than the distribution of the openings 235c near the edge of the gas distribution plate 233, so that the amount of plasma products near the center of the gas distribution plate 233 is larger than the amount of plasma products near the edge of the gas distribution plate 233 when the plasma products leave the showerhead 231. The size and distribution of the openings together provide a more uniform distribution of plasma products entering the showerhead 231 from the conduit 221 and exiting the showerhead 231. For example, the plasma product flow rate near the edge of the showerhead 231 (e.g., within 50mm of the edge of the showerhead 231) may be 70% of the plasma product flow rate near the center of the showerhead 231 (e.g., within 20mm of the center of the showerhead 231). In the illustrative example shown in FIG. 13B, the openings 235 include openings 235a,235B, and 235 c. The number of openings 235, the configuration of the openings 235, the number of openings 235 of different sizes, the configuration of the openings 235, the relative sizes of the openings 235, and other characteristics (e.g., shape, spacing, or distribution, etc.) of the openings 235 may be different in other embodiments without departing from the scope of embodiments of the present invention.

However, the above description of the introduction of plasma products into the process chamber 203 via a single showerhead 231 or a single introduction point is for illustrative purposes only and is not intended to be limiting. Any number of separate independent showerhead 231 or other openings may be used instead to introduce plasma products into the process chamber 203. All combinations of spray heads and other points of introduction are fully included within the scope of the embodiments.

As shown in fig. 13A, the process chamber 203 may receive plasma products and expose the substrate 50 to the plasma products. The process chamber 203 may be any desired shape that may be suitable for dispersing and contacting plasma products with the substrate 50. The housing 225 may surround the process chamber 203, and the constituent material of the housing 225 is inert to a variety of process materials. As such, the housing 225 may be any suitable material that can withstand the chemicals and pressures associated with the deposition process. In one embodiment, the housing 225 may be steel, stainless steel, nickel, aluminum, alloys thereof, ceramics, combinations thereof, or the like.

In the process chamber 203, the substrate 50 may be placed on a mounting platform 237 to position and control the substrate 50 during the deposition process. Although fig. 13A shows a single mounting platform 237, any number of mounting platforms 237 may additionally be included in the process chamber 203. In addition, multiple wafers or substrates 50 may be placed on a single mounting platform 237.

In some embodiments, the material of construction of the mounting platform 237 is suitable to withstand the relatively high temperatures of the process. For example, the mounting platform 237 may be composed of an aluminum nitride material, another metal alloy material, or another suitable material. The mounting platform 237 may be configured to evenly distribute heat to a wafer or substrate 50 mounted on the mounting platform 237.

The mounting platform 237 may additionally include a first electrode 239 coupled to a second rf generator 241. During the second etching process or other processes, the second rf generator 241 may electrically bias the first electrode 239 by an rf voltage under the control of the control unit 215.

The process chamber 203 may also have an exhaust outlet 227 so that the process chamber 203 may exhaust materials. A vacuum pump 229 may be connected to the exhaust outlet 227 of the process chamber 203 to facilitate the extraction of waste material. The vacuum pump 229 may also be used to reduce and control the pressure in the process chamber 203 to a desired pressure under the control of the control unit 215, and may be used to evacuate waste materials or reaction byproducts from the process chamber 203.

In fig. 14A and 14B, once recesses 102 are formed, epitaxial source/drain regions 82 are formed in fin 52 and fill recesses 102 to apply stress in respective channel regions 58 to improve performance. Epitaxial source/drain regions 82 are formed in fin 52 such that each dummy gate 72 is located between a respective adjacent pair of epitaxial source/drain regions 82. In some embodiments, epitaxial source/drain regions 82 may extend into fin 52 and may also extend through fin 52. In some embodiments, gate spacers 86 are used to space epitaxial source/drain regions 82 a suitable lateral distance from dummy gate 72 so that epitaxial source/drain regions 82 do not short out to the final finfet gate to which they are subsequently formed.

Epitaxial source/drain regions 82 in region 50N (e.g., an N-type mos region) may be formed by masking region 50P (e.g., a P-type mos region). The epitaxial source/drain regions 82 in the epitaxially grown region 50N are then in the recesses 102. The epitaxial source/drain regions 82 in the region 50N (e.g., an N-type metal oxide semiconductor region) may comprise any acceptable material, such as a material suitable for an N-type finfet. For example, if fin 52 is silicon, epitaxial source/drain regions 82 in region 50N may comprise a material that exerts a tensile stress in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. Epitaxial source/drain regions 82 in region 50N may have surfaces raised from respective surfaces of fin 52 and may have crystallographic planes.

Epitaxial source/drain regions 82 in region 50P (e.g., a pmos region) may be formed by masking region 50N (e.g., an nmos region) and etching the source/drain regions of fin 52 in region 50P to form recesses 102 in fin 52. The epitaxial source/drain regions 82 in the epitaxially grown region 50P are then in the recesses 102. The epitaxial source/drain regions 82 in the region 50P (e.g., a P-type metal oxide semiconductor region) may comprise any acceptable material, such as a material suitable for a P-type finfet. For example, if fin 52 is silicon, epitaxial source/drain regions 82 in region 50P may comprise a material that exerts a compressive stress in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like. Epitaxial source/drain regions 82 in region 50P may also have surfaces raised from respective surfaces of fin 52 and may have crystallographic planes.

Epitaxial source/drain regions 82 and/or fin 52 may be doped to form source/drain regions, followed by an anneal. The dopant implantation step is similar to the process described above for forming lightly doped source/drain regions. The impurity concentration of epitaxial source/drain regions 82 may be between about 10¹⁹cm^-3To about 10²¹cm^-3In the meantime. The n-type and/or p-type impurities used for epitaxial source/drain regions 82 may be any of the aforementioned impurities. In some embodiments, the epitaxial source/drain regions 82 may be doped in-situ as they are grown.

The epitaxial process used to form epitaxial source/drain regions 82 in regions 50N and 50P results in the upper side surfaces of the epitaxial source/drain regions having crystallographic planes that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these crystal planes cause adjacent epitaxial source/drain regions 82 of the same finfet transistor to merge, as shown in fig. 14C. Other embodiments maintain the separation of adjacent epitaxial source/drain regions 82 after the epitaxial growth process is completed, as shown in figure 14D. In the embodiment shown in fig. 14C and 14D, gate spacers 86 cover sidewall portions of fin 52 extending over sti regions 56 to block epitaxial growth. In some embodiments, the etch spacer step used to form the gate spacers 86 may be adjusted to remove the spacer material and extend the epitaxially grown region to the surface of the sti region 56.

In fig. 15A and 15B, a first interlayer dielectric layer 88 is deposited over the structure shown in fig. 14A and 14B. The composition of the first interlayer dielectric layer 88 may be a dielectric material, and the deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may comprise phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer is located between first interlayer dielectric 88 and epitaxial source/drain regions 82, mask 74, and gate spacers 86. The contact etch stop layer 87 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material on the first interlayer dielectric layer 88.

In fig. 16A and 16B, a planarization process, such as chemical mechanical polishing, may be performed to make the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 over the dummy gate 72 and portions of the gate seal spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, dummy gate 72, gate seal spacer 80, gate spacer 86 are flush with the upper surface of first interlayer dielectric 88. In summary, the upper surface of the dummy gate 72 is exposed through the first interlayer dielectric layer 88. In some embodiments, mask 74 may be retained and the planarization process makes the upper surface of first interlayer dielectric layer 88 flush with the upper surface of mask 74.

In fig. 17A and 17B, an etch step removes dummy gate 72 and mask 74 (if present) to form recess 90. Portions of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed and the dummy dielectric layer 60 remains, and the recess 90 exposes the dummy dielectric layer 60. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., the core logic region), but the dummy dielectric layer 60 of the recess 90 in a second region of the die (e.g., the input/output region) remains. In some embodiments, the dummy gate 72 may be removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using a reactive gas that may selectively etch the dummy gate 72 without etching the first interlayer dielectric layer 88 or the gate spacer 86. Each recess 90 exposes and/or overlaps channel region 58 of a respective fin 52. Each channel region 58 is located between an adjacent pair of epitaxial source/drain regions 82. The dummy dielectric layer 60 may serve as an etch stop layer when the dummy gate 72 is etched away. After the dummy gate 72 is removed, the dummy dielectric layer 60 may then be optionally removed.

In fig. 18A and 18B, a gate dielectric 92 and a gate 94 are formed as replacement gates. Fig. 18C shows a detail view of region 89 of fig. 19B. Gate dielectric layer 92 is conformably deposited in recess 90, such as on the sidewalls and upper surface of fin 52 and the sidewalls of gate seal spacers 80 and/or gate spacers 86. A gate dielectric layer 92 may also be formed on the upper surface of the first interlayer dielectric layer 88. In some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 92 comprises a high-k dielectric material. In these embodiments, the gate dielectric layer 92 has a dielectric constant greater than about 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The method of forming the gate dielectric layer 92 may include molecular beam deposition, atomic layer deposition, plasma assisted chemical vapor deposition, or the like. In embodiments where portions of dummy dielectric layer 60 remain in recess 90, gate dielectric layer 92 comprises a material of dummy dielectric layer 60, such as silicon oxide.

Gates 94 are deposited on gate dielectric layers 92 and fill the remainder of recesses 90, respectively. Gate 94 may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although the gate 94 shown in fig. 18B is a single layer, the gate 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and fill material 94C, as shown in fig. 18C. After filling recess 90, a planarization process, such as chemical mechanical polishing, may be performed to remove excess portions of the material of gate dielectric 92 and gate 94 on the upper surface of first interlayer dielectric 88. The remaining portions of the material of gate 94 and gate dielectric layer 92 form the replacement gates of the final finfet. The gate 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and gate stack may extend along sidewalls of channel region 58 of fin 52.

Gate dielectric 92 may be formed in both regions 50N and 50P such that gate dielectric 92 in each region is comprised of the same material. The gate 94 may be formed simultaneously such that the gate 94 in each region is comprised of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by a separate process, with the gate dielectric layer 92 in each region being a different material, and/or the gate 94 in each region may be formed by a separate process, with the gate 94 in each region being a different material. When a separate process is employed, various masking steps may be used to mask and expose the appropriate areas.

In fig. 19A and 19B, a second interlayer dielectric layer 108 is deposited over the first interlayer dielectric layer 88. In some embodiments, the second interlayer dielectric layer 108 is a flowable film formed by a flowable chemical vapor deposition process. In some embodiments, the composition of the second interlayer dielectric layer 108 is a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof may be any suitable method such as chemical vapor deposition or plasma-assisted chemical vapor deposition. Some embodiments recess the gate stack (including gate dielectric 92 and corresponding upper gate 94) prior to forming second interlayer dielectric 108 to form a recess directly above the gate stack and between opposing portions of gate spacer 86, as shown in fig. 19A and 19B. The gate mask 96 comprises one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, which may be filled into the recess and then subjected to a planarization process to remove excess portions of the dielectric material extending above the first interlayer dielectric layer 88. Subsequently formed gate contacts 110 (see fig. 20A and 20B) pass through the gate mask 96 to contact the upper surface of the recessed gates 94.

In some embodiments as shown in fig. 20A and 20B, a gate contact 110 and source/drain contacts 112 are formed through the second interlayer dielectric 108, the first interlayer dielectric 88, and the gate mask 96. Openings for source/drain contacts 112 are formed through the first interlayer dielectric 88 and the second interlayer dielectric 108, and openings for gate contacts 110 are formed through the second interlayer dielectric and the gate mask 96. The formation of the opening may be performed by acceptable photolithography and etching techniques. A liner layer (e.g., a diffusion barrier layer, adhesion layer, or the like) and a conductive material may be formed in the opening. The liner layer may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second ild layer 108. The remaining liner layer and conductive material may form source/drain contacts 112 and gate contacts 110 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source/drain regions 82 and the source/drain contacts 112. Source/drain contact 112 is physically and electrically coupled to epitaxial source/drain region 82, and gate contact 110 is physically and electrically coupled to gate 94. The source/drain contacts 112 and the gate contact 110 may be formed by different processes or may be formed by the same process. Although the source/drain contacts 112 and the gate contact 110 are formed in the same cross-section in the drawings, it is understood that the two may be formed in different cross-sections to avoid contact shorting.

As described above, removing the etch residues 104 may reduce device defects and improve device performance. Forming recesses 102 (filled with epitaxial source/drain regions 82) having V-shaped lower surfaces allows more dopant to diffuse from the subsequently formed epitaxial source/drain regions into the channel region 58 to reduce the channel resistance R in the channel region 58_ch. In addition, forming the recess 102 (filled with the epitaxial source/drain regions 82) extending below the gate spacer 86 improves device performance, avoids drain induced barrier lowering, and improves the difference between the on-current and the leakage current (e.g., increases the on-current and decreases the leakage current). Thus, the device formed by the method can have improved device performance and reduced device defects.

In one embodiment, a method includes forming a gate stack on a fin extending from a substrate; forming a gate spacer on sidewalls of the gate stack; etching the fin by a first etch process to form a first recess adjacent the gate spacer, wherein the first etch process is non-isotropic; etching the fin by a second etching process to remove the etching residues from the first recess, wherein the second etching process uses a different etchant than the first etching process; etching the surface of the first recess by a third etching process to form a second recess extending below the gate spacer in a direction perpendicular to the major surface of the substrate, the second recess having a V-shaped lower surface, wherein the third etching process is non-isotropic along the crystallographic plane of the substrate and the third etching process uses a different etchant than the first etching process; and epitaxially forming source/drain regions in the second recesses. In one embodiment, the etch residue comprises native oxide or carbon residue. In one embodiment, the second etching process is an ammonia-based etching process. In one embodiment, the temperature of the second etching process is 100 ℃ to 200 ℃. In one embodiment, the third etch process is a hydrogen-based plasma etch process. In one embodiment, the first etching process is reactive ion etching. In one embodiment, the second etching process and the third etching process use the same etchant. In one embodiment, the step of etching the surface of the first recess by the third etching process includes flowing hydrogen radicals through the showerhead with a higher density of openings near the center of the showerhead than near the edge of the showerhead.

In another embodiment, an apparatus comprises: a fin extending from a substrate; a gate stack on the fin; a gate spacer on a sidewall of the gate stack; and a source/drain region in the fin adjacent to the gate spacer, the source/drain region having a V-shaped lower surface in a (111) crystallographic plane, the source/drain region extending below the gate spacer in a direction parallel to the major surface of the substrate and in a (110) crystallographic plane, wherein the source/drain region extends below the gate spacer by at least 4nm to 8nm in a depth of 20nm to 30nm and in a direction parallel to the major surface of the substrate. In one embodiment, the angle between the V-shaped lower surface of the source/drain region and a line parallel to the major surface of the substrate is 55 ° to 65 °. In one embodiment, the source/drain regions extend 40nm to 50nm below the major surface of the substrate. In one embodiment, the fin has a 5x hydrogen concentration adjacent to the source/drain regions10¹⁸Atom/cm³To 5x 10¹⁹Atom/cm³。

In yet another embodiment, a method comprises: forming a fin in a semiconductor substrate; forming a dummy gate stack on the fin; etching the fin adjacent to the dummy gate stack by a first etching process to form a first recess, wherein the first etching process anisotropically etches the fin, and the etching direction is perpendicular to the main surface of the semiconductor substrate; removing etching residues from the first recess after etching the fin using the first etching process; etching the first recess using a second etch process to form a second recess, the second etch process being non-isotropic along the (111) crystallographic plane and along the (110) crystallographic plane; forming source/drain regions in the second recesses; and replacing the dummy gate with a gate stack. In one embodiment, the second etching process removes the etching residues. In one embodiment, the second etch process comprises a hydrogen-based plasma etch. In one embodiment, the step of removing the etch residue from the first recess employs an ammonia-based etch process, wherein the first recess is etched using a second etch process after the etch residue is removed from the first recess, and wherein the step of etching the first recess using the second etch process employs a hydrogen-based plasma etch process. In one embodiment, the ammonia-based etch process temperature is 100 ℃ to 200 ℃, and the hydrogen-based plasma etch process temperature is 250 ℃ to 450 ℃. In one embodiment, the method further includes forming a gate spacer adjacent to the dummy gate stack, wherein after etching the fin using the first etch process, sidewalls of the first recess are adjacent to sidewalls of the gate spacer, and after etching the first recess using the second etch process, sidewalls of the second recess extend below the gate spacer in a direction perpendicular to the major surface of the semiconductor substrate. In one embodiment, the etch residue comprises native oxide or carbon residue. In one embodiment, after the fin adjacent to the dummy gate stack is etched using the first etch process and before the etch residue is removed from the first recess, the etch residue has a thickness of 0.1nm to 1 nm.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.