阅读说明：本技术 半导体器件及其制备方法 (Semiconductor device and method for manufacturing the same ) 是由 孙超 于 2020-11-19 设计创作，主要内容包括：本发明提供一种半导体器件及其制备方法,半导体器件包括：半导体衬底；阱区设置在半导体衬底中；栅极设置于半导体衬底上,且栅极在半导体衬底的厚度方向上与阱区的一部分重叠,以在阱区中定义沟道区；重掺杂源极区及重掺杂漏极区设置在阱区中,且位于沟道区的两侧,轻掺杂漏区设置在阱区中,且位于重掺杂源极区与沟道区之间及重掺杂漏极区与沟道区之间；栅氧化层设置在半导体衬底上,位于栅极与阱区之间,且在半导体衬底的厚度方向上栅氧化层与轻掺杂漏区至少部分重叠；隔离层设置在轻掺杂漏区与栅氧化层之间,隔离层的导电类型与轻掺杂漏区的导电类型互补。本发明减小了界面缺陷对轻掺杂漏区的影响,提高了半导体器件的可靠性等性能。(The invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: a semiconductor substrate; the well region is arranged in the semiconductor substrate; the grid is arranged on the semiconductor substrate and is overlapped with a part of the well region in the thickness direction of the semiconductor substrate so as to define a channel region in the well region; the heavily doped source region and the heavily doped drain region are arranged in the well region and positioned at two sides of the channel region, and the lightly doped drain region is arranged in the well region and positioned between the heavily doped source region and the channel region and between the heavily doped drain region and the channel region; the gate oxide layer is arranged on the semiconductor substrate, is positioned between the grid electrode and the well region, and at least partially overlaps with the lightly doped drain region in the thickness direction of the semiconductor substrate; the isolation layer is arranged between the lightly doped drain region and the gate oxide layer, and the conductivity type of the isolation layer is complementary to that of the lightly doped drain region. The invention reduces the influence of the interface defect on the lightly doped drain region and improves the performances of the semiconductor device, such as reliability and the like.)

1. A semiconductor device, comprising:

a semiconductor substrate;

the well region is arranged in the semiconductor substrate;

the grid electrode is arranged on the semiconductor substrate and is overlapped with a part of the well region in the thickness direction of the semiconductor substrate so as to define a channel region in the well region;

a heavily doped source region and a heavily doped drain region arranged in the well region and located at two sides of the channel region

The lightly doped drain region is arranged in the well region and is positioned between the heavily doped source region and the channel region and between the heavily doped drain region and the channel region;

the gate oxide layer is arranged on the semiconductor substrate, is positioned between the grid electrode and the well region, and at least partially overlaps with the lightly doped drain region in the thickness direction of the semiconductor substrate;

and the isolation layer is arranged between the lightly doped drain region and the gate oxide layer, and the conductivity type of the isolation layer is complementary with that of the lightly doped drain region.

2. The semiconductor device of claim 1, wherein a doping concentration of the isolation layer is less than a doping concentration of the lightly doped drain region.

3. The semiconductor device of claim 1, wherein the isolation layer is formed by doping the lightly doped drain region at a contact interface of the lightly doped drain region and the gate oxide layer.

4. The semiconductor device of claim 1, wherein a conductivity type of the isolation layer is the same as a conductivity type of the well region, and a doping concentration of the isolation layer is less than a doping concentration of the well region.

5. The semiconductor device of claim 1, wherein a thickness of the isolation layer is less than a thickness of the lightly doped drain region.

6. The semiconductor device according to claim 1, wherein the semiconductor device is a high-voltage semiconductor device.

7. A method for manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate;

forming a well region in the semiconductor substrate;

forming a gate oxide layer and a gate on the semiconductor substrate, wherein the gate overlaps with a part of the well region in the thickness direction of the semiconductor substrate to define a channel region in the well region, and the gate oxide layer is located between the gate and the well region;

forming lightly doped drain regions on two sides of the channel region, wherein the lightly doped drain regions are at least partially overlapped with the grid oxide layer in the thickness direction of the semiconductor substrate;

forming an isolation layer between the lightly doped drain region and the gate oxide layer, wherein the conductivity type of the isolation layer is complementary to that of the lightly doped drain region,

and after the isolation layer is formed or before the isolation layer is formed, forming a heavily doped source region and a heavily doped drain region outside the lightly doped drain region.

8. The method of claim 7, wherein the isolation layer is formed by ion implantation or diffusion doping.

9. The method of claim 7, wherein the step of forming an isolation layer between the lightly doped drain region and the gate oxide layer further comprises: and doping the lightly doped drain region at the contact interface of the lightly doped drain region and the gate oxide layer to form the isolation layer.

10. The method of claim 7, wherein a doping concentration of the isolation layer is less than or equal to a doping concentration of the lightly doped drain region.

11. The method of claim 7, wherein a thickness of the isolation layer is less than a thickness of the lightly doped drain region.

Technical Field

The invention relates to the field of integrated circuits, in particular to a semiconductor device and a preparation method thereof.

Background

For HV MOS devices, e.g. HV NMOS (high voltage NMOS) or HV PMOS (high voltage PMOS), LDD (lightly doped drain)) Upper Si/SiO₂Interface traps (interface traps) are created at the interface during electrical stress (stress) and can affect the LDD concentration. For example, interface defects generated under Hot Carrier Injection (HCI) stress may affect LDD concentration, causing variations in parameters such as threshold voltage, mobility, transconductance, etc. of the device, resulting in reduced drain current and degradation of the device.

Therefore, a new semiconductor device and a method for fabricating the same are needed to overcome the above-mentioned drawbacks.

Disclosure of Invention

The invention aims to provide a semiconductor device and a preparation method thereof, which can reduce the influence of interface defects generated in the electrical stress process on a lightly doped drain region and improve the performance of the semiconductor device.

In order to solve the above problems, the present invention provides a semiconductor device comprising: a semiconductor substrate; the well region is arranged in the semiconductor substrate; the grid electrode is arranged on the semiconductor substrate and is overlapped with a part of the well region in the thickness direction of the semiconductor substrate so as to define a channel region in the well region; a heavily doped source region and a heavily doped drain region which are arranged in the well region and positioned at two sides of the channel region, and a lightly doped drain region which is arranged in the well region and positioned between the heavily doped source region and the channel region and between the heavily doped drain region and the channel region; the gate oxide layer is arranged on the semiconductor substrate, is positioned between the grid electrode and the well region, and at least partially overlaps with the lightly doped drain region in the thickness direction of the semiconductor substrate; and the isolation layer is arranged between the lightly doped drain region and the gate oxide layer, and the conductivity type of the isolation layer is complementary with that of the lightly doped drain region.

Optionally, a doping concentration of the isolation layer is less than a doping concentration of the lightly doped drain region.

Optionally, the isolation layer is formed by doping the lightly doped drain region at a contact interface between the lightly doped drain region and the gate oxide layer.

Optionally, a conductivity type of the isolation layer is the same as a conductivity type of the well region, and a doping concentration of the isolation layer is less than a doping concentration of the well region.

Optionally, a thickness of the isolation layer is smaller than a thickness of the lightly doped drain region.

Optionally, the semiconductor device is a high voltage semiconductor device.

The invention also provides a preparation method of the semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a well region in the semiconductor substrate; forming a gate oxide layer and a gate on the semiconductor substrate, wherein the gate overlaps with a part of the well region in the thickness direction of the semiconductor substrate to define a channel region in the well region, and the gate oxide layer is located between the gate and the well region; forming lightly doped drain regions on two sides of the channel region, wherein the lightly doped drain regions are at least partially overlapped with the grid oxide layer in the thickness direction of the semiconductor substrate; and forming an isolation layer between the lightly doped drain region and the gate oxide layer, wherein the conductivity type of the isolation layer is complementary to that of the lightly doped drain region, and a heavily doped source region and a heavily doped drain region are formed outside the lightly doped drain region after the isolation layer is formed or before the isolation layer is formed.

Optionally, the isolation layer is formed by ion implantation or diffusion doping.

Optionally, the method for forming the isolation layer between the lightly doped drain region and the gate oxide layer further includes: and doping the lightly doped drain region at the contact interface of the lightly doped drain region and the gate oxide layer to form the isolation layer.

Optionally, a doping concentration of the isolation layer is less than or equal to a doping concentration of the lightly doped drain region.

Optionally, a thickness of the isolation layer is smaller than a thickness of the lightly doped drain region.

The semiconductor device has the advantages that the isolation layer is formed at the interface of the lightly doped drain region and the gate oxide layer, when the semiconductor device is conducted, the isolation layer is used for isolating a current path from the interface of the lightly doped drain region and the gate oxide layer, and under the electrical stress, such as Hot Carrier Injection (HCI) stress, the interface defect generated at the interface of the gate oxide layer and the lightly doped drain region can not cause the depletion of carriers on the upper surface of the lightly doped drain region, so that the influence of the interface defect on the lightly doped drain region is reduced, and the performances of the semiconductor device, such as reliability, are improved. Meanwhile, compared with the existing semiconductor device, the semiconductor device has the advantages that the area is not sacrificed, the cost is not increased, other devices are not influenced, and the scheme is simple and feasible.

Drawings

Fig. 1 is a schematic structural view of a conventional semiconductor device;

FIG. 2 is a schematic diagram of a semiconductor device in accordance with one embodiment of the present invention;

FIG. 3 is a schematic step diagram of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention;

fig. 4A to 4F are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the semiconductor device and the method for manufacturing the same according to the present invention will be made with reference to the accompanying drawings.

The inventors have found that under electrical stress, such as Hot Carrier Injection (HCI) stress, interface defects generated at the interface between the gate oxide layer and the Lightly Doped Drain (LDD) region deplete carriers on the upper surface of the lightly doped drain region, which causes variations in the threshold voltage, mobility, transconductance, and other parameters of the device, resulting in reduced drain current and degradation of the device. Fig. 1 is a schematic structural view of a conventional semiconductor device. Referring to fig. 1, the semiconductor device includes a semiconductor substrate 100, a well region 110 disposed in the semiconductor substrate 100, a gate 120 disposed on an upper surface of the semiconductor substrate 100 and partially overlapping the well region 110, a channel region 160 in the well region 110 corresponding to the gate 120, a gate oxide layer 140 disposed between the gate 120 and the well region 110, and a lightly doped drain region 130, a heavily doped source region 170S, and a heavily doped drain region 170D disposed on two sides of the gate 120 and in the well region 110.

When the semiconductor device is turned on, a current path (shown by a solid arrow in fig. 1) of the semiconductor device is from the heavily doped drain region 170D, through the lightly doped drain region 130, to the channel region 160, through the channel region 160, to the heavily doped source region 170S. The current path flows through the contact interface between the gate oxide layer 140 and the lightly doped drain region 130, and due to electrical stress, the surface carriers on the lightly doped drain region 130 are depleted by the interface defects generated at the interface between the gate oxide layer 140 and the lightly doped drain region 130, which causes the parameters of threshold voltage, mobility, transconductance and the like of the device to change, resulting in the reduction of drain current and the degradation of the device.

Therefore, the invention provides a semiconductor device, which can reduce the influence of interface defects on a lightly doped drain region and improve the performance of the semiconductor device.

Fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, referring to fig. 2, the semiconductor device includes a semiconductor substrate 200, a well region 210, a gate 220, a lightly doped drain 230, a gate oxide 240 and an isolation layer 250.

The semiconductor substrate 200 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like, and an appropriate semiconductor material may be selected as the semiconductor substrate 200 according to actual requirements of devices, which is not limited herein. In this embodiment, the semiconductor substrate 200 is a single crystal silicon substrate.

The well region 210 may be formed by doping into the semiconductor substrate 200, wherein the conductivity type of the well region 210 depends on the type of dopant. For example, if the semiconductor substrate 200 is doped with phosphorus (P), arsenic (As), or another suitable N-type dopant, an N-type well region is formed, and if the semiconductor substrate 200 is doped with boron (B), gallium (Ga), or another suitable P-type dopant, a P-type well region is formed. In this embodiment, the well region is a P-type well region.

The gate 220 is disposed on the semiconductor substrate 200, and the gate 220 overlaps a portion of the well region 210 in a thickness direction of the semiconductor substrate 200 to define a channel region 260 in the well region 210. Specifically, the gate 220 is disposed on the upper surface of the semiconductor substrate 200, and the gate 220 overlaps a portion of the well region 210 in a thickness direction (Y direction in fig. 2) of the semiconductor substrate 200. In the well region 210, a portion overlapping with the gate 220 is defined as a channel region 260. The gate 220 may be a polysilicon layer or a tungsten layer.

The lightly doped drain region 230 is disposed in the well region 210 and located at two sides of the channel region 260. The lightly doped drain region 230 may be formed by doping into the well region 210, wherein the conductivity type of the lightly doped drain region 230 depends on the type of dopant. The lightly doped drain region 230 has a conductivity type complementary to that of the well region 210. For example, if the conductivity type of the well region 210 is N-type, the conductivity type of the lightly doped drain region 230 is P-type; if the conductivity type of the well region 210 is P-type, the conductivity type of the lightly doped drain region 230 is N-type. In this embodiment, the conductivity type of the well region 210 is P-type, and the conductivity type of the lightly doped drain region 230 is N-type. In this embodiment, the lightly doped drain region 230 has an N-type conductivity.

The gate oxide layer 240 is disposed on the semiconductor substrate 200 between the gate 220 and the well region 210, and the gate oxide layer 240 and the lightly doped drain region 230 at least partially overlap in a thickness direction of the semiconductor substrate 200. Specifically, the gate oxide layer 240 is disposed on the upper surface of the semiconductor substrate 200 and between the gate 220 and the well region 210, i.e., the gate oxide layer 240 is located below the gate 220. In the thickness direction (Y direction as shown in fig. 2) of the semiconductor substrate 200, the gate oxide layer 240 at least partially overlaps the lightly doped drain region 230.

In this embodiment, in the thickness direction of the semiconductor substrate 200 (the Y direction shown in fig. 2), the gate oxide layer 240 and the lightly doped drain region 230 are all overlapped, i.e., in the direction parallel to the semiconductor substrate (the X direction shown in fig. 2), the gate oxide layer 240 extends to cover the entire area of the lightly doped drain region 230. In another embodiment of the present invention, in a thickness direction (e.g., Y direction shown in fig. 2) of the semiconductor substrate 200, the gate oxide layer 240 is partially overlapped with the lightly doped drain region 230, that is, in a direction parallel to the semiconductor substrate (e.g., X direction shown in fig. 2), the gate oxide layer 240 extends to cover a partial region of the lightly doped drain region 230, a portion of the lightly doped drain region 230 close to the channel region 260 is covered by the gate oxide layer 240, and a portion of the lightly doped drain region 230 far from the channel region 260 is not covered by the gate oxide layer 240.

The isolation layer 250 is disposed between the lightly doped drain region 230 and the gate oxide layer 240. In this embodiment, the gate oxide layer 240 and the lightly doped drain region 230 are all overlapped, and the isolation layer 250 is disposed between the lightly doped drain region 230 and the gate oxide layer 240 and also all overlapped with the lightly doped drain region 230; in other embodiments of the present invention, the gate oxide layer 240 partially overlaps the lightly doped drain region 230, and the isolation layer 250 is disposed between the lightly doped drain region 230 and the gate oxide layer 240 and also partially overlaps the lightly doped drain region 230.

The conductivity type of the isolation layer 250 is complementary to the conductivity type of the lightly doped drain region 230. Specifically, if the conductivity type of the lightly doped drain region 230 is N-type, the conductivity type of the isolation layer 250 is P-type, and if the conductivity type of the lightly doped drain region 230 is P-type, the conductivity type of the isolation layer 250 is N-type. In this embodiment, the lightly doped drain region 230 has an N-type conductivity, and the isolation layer 250 has a P-type conductivity.

Further, the semiconductor device further includes a heavily doped source region 270S and a heavily doped drain region 270D. The heavily doped source region 270S and the heavily doped drain region 270D are disposed in the well region 210 and located at two sides of the channel region 260. The lightly doped drain region 230 is disposed between the heavily doped source region 270S and the channel region 260 and between the heavily doped drain region 270D and the channel region 260. The lightly doped drain region 230 has the same conductivity type as the heavily doped source region 270S and the heavily doped drain region 270D, and in this embodiment, the conductivity type of the heavily doped source region 270S and the heavily doped drain region 270D is N-type. The lightly doped drain region 230 has a doping concentration less than the doping concentrations of the heavily doped source region 270S and the heavily doped drain region 270D, and in the semiconductor device, the heavily doped source region 270S and the heavily doped drain region 270D need to be electrically connected to a source metal and a drain metal.

Due to the existence of the isolation layer 250, when the semiconductor device is turned on, a current path (as shown by a solid arrow in fig. 2) of the semiconductor device is from the heavily doped drain region 270D, through the lightly doped drain region 230 under the isolation layer 250 to the channel region 260, and through the channel region 260 to the heavily doped source region 270S. Under the electrical stress, for example, under the Hot Carrier Injection (HCI) stress, the interface defect generated at the interface between the gate oxide layer and the lightly doped drain region (LDD) will not cause the depletion of carriers on the upper surface of the lightly doped drain region, thereby reducing the influence of the interface defect on the lightly doped drain region 230 and improving the performance of the semiconductor device, such as reliability. Meanwhile, compared with the existing semiconductor device, the semiconductor device has the advantages that the area is not sacrificed, the cost is not increased, other devices are not influenced, and the scheme is simple and feasible.

Further, the doping concentration of the isolation layer 250 is less than or equal to the doping concentration of the lightly doped drain region 230, so as to further reduce the influence of the interface defect on the lightly doped drain region 230, and the normal conductivity of the lightly doped drain region 230 is not affected.

Further, the isolation layer 250 is formed by doping the lightly doped drain region 230 at the contact interface between the lightly doped drain region 230 and the gate oxide layer 240. That is, the isolation layer 250 is formed within the semiconductor substrate 200, rather than on the upper surface of the semiconductor substrate 200.

Further, the conductivity type of the isolation layer 250 is the same as the conductivity type of the well region 110, and the doping concentration of the isolation layer 250 is less than the doping concentration of the well region 110.

Further, the thickness of the isolation layer 250 is less than that of the lightly doped drain region 230.

Further, in this embodiment, the semiconductor device is a high voltage semiconductor device. In other embodiments of the present invention, the semiconductor device may be other types of MOS devices.

The invention further provides a preparation method of the semiconductor device. Fig. 3 is a schematic step diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, referring to fig. 3, the method includes the following steps: step S30, providing a semiconductor substrate; step S31, forming a well region in the semiconductor substrate; step S32, forming a gate oxide layer and a gate on the semiconductor substrate, where the gate overlaps with a part of the well region in a thickness direction of the semiconductor substrate to define a channel region in the well region, and the gate oxide layer is located between the gate and the well region; step S33, forming lightly doped drain regions at two sides of the channel region, wherein the lightly doped drain regions are at least partially overlapped with the gate oxide layer in the thickness direction of the semiconductor substrate; step S34, forming an isolation layer between the lightly doped drain region and the gate oxide layer, wherein the conductivity type of the isolation layer is complementary to that of the lightly doped drain region; in step S35, a heavily doped source region and a heavily doped drain region are formed outside the lightly doped drain region.

Fig. 4A to 4F are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

In step S30 and fig. 4A, a semiconductor substrate 300 is provided.

The semiconductor substrate 300 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI or GOI, etc., and an appropriate semiconductor material may be selected as the semiconductor substrate 300 according to actual requirements of devices, which is not limited herein. In this embodiment, the semiconductor substrate 300 is a single crystal silicon substrate.

Referring to step S31 and fig. 4B, a well 310 is formed in the semiconductor substrate 300.

Specifically, the semiconductor substrate 300 is doped to form the well region 310. The conductivity type of the well region 310 depends on the type of dopant. For example, if the semiconductor substrate 300 is doped with phosphorus (P), arsenic (As) or other suitable N-type dopant, an N-type well region is formed, and if the semiconductor substrate 300 is doped with boron (B), gallium (Ga) or other suitable P-type dopant, a P-type well region is formed. In this embodiment, the well region 310 is a P-type well region.

Referring to step S32 and fig. 4C, a gate oxide layer 340 and a gate 320 are formed on the semiconductor substrate 300, the gate 320 overlaps a portion of the well region 310 in a thickness direction of the semiconductor substrate 300 to define a channel region 360 in the well region 310, and the gate oxide layer 340 is located between the gate 320 and the well region 310.

Specifically, in this embodiment, the gate oxide layer 340 and the gate electrode 320 are formed by chemical vapor deposition, physical vapor deposition, or the like. The gate electrode 320 overlaps a portion of the well region 310 in a thickness direction (Y direction in fig. 4C) of the semiconductor substrate 300, and a portion overlapping the gate electrode 220 in the well region 310 is defined as a channel region 260. The gate oxide layer 340 extends in a direction parallel to the surface of the semiconductor substrate 300, i.e., the edge of the gate oxide layer 340 exceeds the edge of the gate electrode 320.

Referring to step S33 and fig. 4D, lightly doped drain regions 330 are formed on both sides of the channel region 360, and the lightly doped drain regions 330 at least partially overlap the gate oxide layer 340 in the thickness direction of the semiconductor substrate 300.

In this step, the lightly doped drain regions 330 may be formed on both sides of the channel region 360 by ion implantation or diffusion doping. The conductivity type of the lightly doped drain region 330 depends on the type of dopant. The lightly doped drain region 330 has a conductivity type complementary to the conductivity type of the well region 310. For example, if the conductivity type of the well region 310 is N-type, the conductivity type of the lightly doped drain region 330 is P-type; if the conductivity type of the well region 310 is P-type, the conductivity type of the lightly doped drain region 330 is N-type. In this embodiment, the conductivity type of the well region 310 is P-type, and the conductivity type of the lightly doped drain region 330 is N-type. In this embodiment, the lightly doped drain region 330 has an N-type conductivity.

Wherein the gate oxide layer 340 and the lightly doped drain region 330 at least partially overlap in a thickness direction of the semiconductor substrate 300. Specifically, in the thickness direction (Y direction as shown in fig. 4D) of the semiconductor substrate 300, the gate oxide layer 340 at least partially overlaps the lightly doped drain region 330. In this embodiment, in the thickness direction of the semiconductor substrate 300 (the Y direction shown in fig. 4D), the gate oxide layer 340 and the lightly doped drain region 330 are all overlapped, i.e., in the direction parallel to the semiconductor substrate (the X direction shown in fig. 4D), the gate oxide layer 340 extends to cover the whole area of the lightly doped drain region 330. In other embodiments of the present invention, in the thickness direction of the semiconductor substrate 300, the gate oxide layer 340 partially overlaps the lightly doped drain region 330, that is, in the direction parallel to the semiconductor substrate, the gate oxide layer 340 extends to cover a partial region of the lightly doped drain region 330, a portion of the lightly doped drain region 330 close to the channel region 360 is covered by the gate oxide layer 340, and a portion of the lightly doped drain region 330 far from the channel region 360 is not covered by the gate oxide layer 340.

Referring to step S34 and fig. 4E, an isolation layer 350 is formed between the lightly doped drain region 330 and the gate oxide layer 340, wherein the conductivity type of the isolation layer 350 is complementary to the conductivity type of the lightly doped drain region 330.

In this embodiment, the gate oxide layer 340 and the lightly doped drain region 330 are all overlapped, and the isolation layer 350 is disposed between the lightly doped drain region 330 and the gate oxide layer 340 and also all overlapped with the lightly doped drain region 330; in other embodiments of the present invention, the gate oxide layer 340 is partially overlapped with the lightly doped drain region 330, and then the isolation layer 350 is disposed between the lightly doped drain region 330 and the gate oxide layer 340 and also partially overlapped with the lightly doped drain region 330.

The conductivity type of the isolation layer 350 is complementary to the conductivity type of the lightly doped drain region 330. Specifically, if the conductivity type of the lightly doped drain region 330 is N-type, the conductivity type of the isolation layer 350 is P-type, and if the conductivity type of the lightly doped drain region 330 is P-type, the conductivity type of the isolation layer 350 is N-type. In this embodiment, the lightly doped drain region 330 has an N-type conductivity, and the isolation layer 350 has a P-type conductivity.

The isolation layer 350 may be formed by ion implantation or diffusion doping. For example, in this embodiment, the isolation layer 350 is formed by ion implantation. Further, the lightly doped drain region 330 is doped at the contact interface between the lightly doped drain region 330 and the gate oxide layer 340 to form the isolation layer 350, i.e. the isolation layer 350 is located in the semiconductor substrate 300, not on the surface of the semiconductor substrate 300.

Further, the doping concentration of the isolation layer 350 is less than that of the lightly doped drain region 330, wherein the doping concentration range of the isolation layer 350 is as follows. The thickness of the isolation layer 350 is smaller than that of the lightly doped drain region 330, wherein the thickness range of the isolation layer 350 is as follows.

Further, the conductivity type of the isolation layer 350 is the same as the conductivity type of the well region 110, and the doping concentration of the isolation layer 350 is less than the doping concentration of the well region 310.

Referring to step S35 and fig. 4F, a heavily doped source region 370S and a heavily doped drain region 370D are formed outside the lightly doped drain region 330.

The heavily doped source region 370S and the heavily doped drain region 370D are disposed in the well region 310 and located at two sides of the channel region 360. The lightly doped drain region 330 is disposed between the heavily doped source region 370S and the channel region 360 and between the heavily doped drain region 370D and the channel region 360.

The heavily doped source region 370S and the heavily doped drain region 370D may be formed by ion implantation or diffusion doping. The heavily doped source region 370S and the heavily doped drain region 370D have the same conductivity type as the lightly doped drain region 330, and in this embodiment, the conductivity type of the heavily doped source region 370S and the heavily doped drain region 370D is N-type. The lightly doped drain region 330 has a doping concentration less than that of the heavily doped source region 370S and the heavily doped drain region 370D, and in the semiconductor device, the heavily doped source region 370S and the heavily doped drain region 370D need to be electrically connected to a source metal and a drain metal.

In this embodiment, the heavily doped source region 370S and the heavily doped drain region 370D are formed after the isolation layer 350 is formed, and in other embodiments of the invention, the heavily doped source region 370S and the heavily doped drain region 370D may be formed after the lightly doped drain region 330 is formed and before the isolation layer 350 is formed.

In the preparation method of the semiconductor device, the isolation layer 350 is formed at the interface of the lightly doped drain region 330 and the gate oxide layer 340, when the semiconductor device is switched on, the semiconductor device is isolated by the isolation layer 350, the current path does not pass through the interface of the lightly doped drain region 330 and the gate oxide layer 340, namely the current path is far away from the interface of the lightly doped drain region 330 and the gate oxide layer 340, and under the electrical stress, such as Hot Carrier Injection (HCI) stress, the interface defect generated at the interface of the gate oxide layer and the lightly doped drain region (LDD) can not deplete the Carrier on the upper surface of the lightly doped drain region, so that the influence of the interface defect on the lightly doped drain region 330 is reduced, and the performances of the semiconductor device, such as reliability, are improved. Meanwhile, compared with the existing semiconductor device, the semiconductor device has the advantages that the area is not sacrificed, the cost is not increased, other devices are not influenced, and the scheme is simple and feasible.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.