阅读说明：本技术 具有分离栅增强结构的低栅电阻功率mosfet器件及方法 (Low gate resistance power MOSFET device with split gate enhancement structure and method ) 是由 乔明 马涛 董仕达 王正康 张波 于 2020-11-19 设计创作，主要内容包括：本发明提供一种具有分离栅增强结构的低栅电阻功率MOSFET器件及其制造方法,包括第一导电类型衬底、第一导电类型外延层、槽结构,槽结构中包含控制栅电极与分离栅电极,控制栅电极包括第一栅电极、第二栅电极和第三栅电极,第三栅电极位于第一栅电极和第二栅电极的上方,且与第一栅电极和第二栅电极邻接,第一导电类型外延层上方为第二导电类型阱区,第二导电类型阱区内部上方为第二导电类型重掺杂区,第二导电类型阱区上方为第一导电类型重掺杂源区；本发明所述器件结构既具有低栅电容特性,又具有低栅电阻特性,实现了高开关速度与低开关损耗的目标,得到了低栅电阻的分离栅增强结构的金属氧化物半导体场效应晶体管。(The invention provides a low-gate resistance power MOSFET device with a separation gate enhancement structure and a manufacturing method thereof, and the low-gate resistance power MOSFET device comprises a first conductive type substrate, a first conductive type epitaxial layer and a groove structure, wherein the groove structure comprises a control gate electrode and a separation gate electrode, the control gate electrode comprises a first gate electrode, a second gate electrode and a third gate electrode, the third gate electrode is positioned above the first gate electrode and the second gate electrode and is adjacent to the first gate electrode and the second gate electrode, a second conductive type well region is arranged above the first conductive type epitaxial layer, a second conductive type heavily doped region is arranged above the inside of the second conductive type well region, and a first conductive type heavily doped source region is arranged above the second conductive type well region; the device structure has the characteristics of low gate capacitance and low gate resistance, the aims of high switching speed and low switching loss are fulfilled, and the metal oxide semiconductor field effect transistor with the low-gate-resistance split-gate enhanced structure is obtained.)

1. A low gate resistance power MOSFET device having a split gate enhancement structure, characterized by: the semiconductor device comprises a first conductive type substrate (10), wherein a first conductive type epitaxial layer (11) is arranged on the upper surface of the first conductive type substrate (10), a groove structure (12) is arranged in the first conductive type epitaxial layer (11), a control gate electrode and a separation gate electrode (14) are contained in the groove structure (12), the control gate electrode comprises a first gate electrode (151), a second gate electrode (152) and a third gate electrode (153), the first gate electrode (151) and the second gate electrode (152) are positioned above the separation gate electrode (14) and are separated from the separation gate electrode (14) through a second dielectric layer (132), the first gate electrode (151) and the second gate electrode (152) are separated from a second conductive type well region (16) in the epitaxial layer (11) through a gate dielectric (133), the third gate electrode (153) is positioned above the first gate electrode (151) and the second gate electrode (152) and is adjacent to the first gate electrode (151) and the second gate electrode (152), the separation gate electrode (14) and the first conduction type epitaxial layer (11) are separated by a first dielectric layer (131), a second conduction type well region (16) is arranged above the first conduction type epitaxial layer (11), a second conduction type heavily doped region (18) is arranged above the inner portion of the second conduction type well region (16), a first conduction type heavily doped source region (19) is arranged above the second conduction type well region (16), metal (20) is led out of the second conduction type heavily doped region (18), and the metal (20) and the control gate electrode are separated by a third dielectric layer (134).

2. A low gate resistance power MOSFET device according to claim 1 having a split gate enhancement structure, wherein: the lower half part of the control gate electrode is a first gate electrode (151) and a second gate electrode (152) which are separated by a dielectric layer, the upper half part is a third gate electrode structure (153) which is adjacent to the first gate electrode and the second gate electrode, and the third gate electrode is equivalent to transferring polysilicon between the first gate electrode and the second gate electrode to the upper surfaces of the first gate electrode and the second gate electrode so as to increase the effective conductive area of the gate.

3. A low gate resistance power MOSFET device according to claim 1 having a split gate enhancement structure, wherein: the upper surface of the third gate electrode (153) is higher than the upper surface of the first conductive type heavily doped source region (19).

4. A low gate resistance power MOSFET device according to claim 1 having a split gate enhancement structure, wherein: the second dielectric layer (132) is a low-k material.

5. A low gate resistance power MOSFET device according to claim 1 having a split gate enhancement structure, wherein: the first dielectric layer (131) is a low-k material.

6. A low gate resistance power MOSFET device according to any of claims 1 to 5, wherein the method of manufacture comprises the steps of:

1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;

2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;

3) etching the polysilicon deposited in the step 2), and forming a separation gate electrode at the lower half part of the control gate groove of the active region;

4) forming a second dielectric layer in the groove of the active region and on the upper part of the separation gate;

5) forming a gate dielectric covering the side wall on the upper half part of the control gate groove in the active region; depositing polycrystalline silicon in the active region, and forming a first gate electrode and a second gate electrode which cover the side wall of the upper half part of the control gate groove after etching;

6) depositing a third dielectric layer to isolate the first gate electrode from the second gate electrode, and selectively etching the dielectric layer at the central part of the control gate groove to be lower than the upper surfaces of the first gate electrode and the second gate electrode in the step 5);

7) depositing and etching polysilicon in the active area to form a third gate electrode, wherein the upper surface of the third gate electrode is not higher than that of the third dielectric layer deposited in the step 6);

8) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;

9) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.

7. A power MOSFET device with a low gate resistance having a split-gate enhancement structure as defined in claim 6, wherein: and 6) etching the mask plate of the third dielectric layer in the step 6) to ensure that the opening width is not less than the distance between the inner side walls of the first gate electrode and the second gate electrode.

8. A method of manufacturing a low gate resistance power MOSFET device with a split gate enhancement structure as claimed in any one of claims 1 to 5, comprising the steps of:

1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;

2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;

3) etching the polysilicon deposited in the step 2), and forming a separation gate electrode at the lower half part of the control gate groove of the active region;

4) forming a second dielectric layer in the groove of the active region and on the upper part of the separation gate;

5) forming a gate dielectric covering the side wall on the upper half part of the control gate groove in the active region; depositing polycrystalline silicon in the active region, and forming a first gate electrode and a second gate electrode which cover the side wall of the upper half part of the control gate groove after etching;

6) depositing a third dielectric layer to isolate the first gate electrode from the second gate electrode, and selectively etching the dielectric layer at the central part of the control gate groove to be lower than the upper surfaces of the first gate electrode and the second gate electrode in the step 5);

7) depositing and etching polysilicon in the active area to form a third gate electrode, wherein the upper surface of the third gate electrode is not higher than that of the third dielectric layer deposited in the step 6);

8) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;

9) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a power MOSFET device with a low gate resistance and an enhanced separation gate and a manufacturing method thereof.

Background

Power management systems require power semiconductor devices to have low on-resistance and parasitic capacitance to reduce device turn-on losses and switching losses. The VDMOS of the split gate has low power loss, fast switching speed, small parasitic capacitance, and good high-frequency characteristics, and thus becomes a medium-low voltage device that is mainly used in a power management system. Chinese patent 201910191166.9 and US patent 16/536333 of qianming, wangzhengkang, and zhangbo et al propose a trench MOSFET with a split-gate enhancement structure to reduce the parasitic capacitance Cgs and gate charge Qg between the control gate and the split gate in a split-gate trench device. However, the control gate structure is too narrow, which results in too large gate resistance, which greatly increases the switching loss of the device.

Therefore, in view of the above problems, it is necessary to reduce the problem of too large gate resistance caused by too narrow control gate in the split gate enhanced structure, and embodiments of the present invention are made in this context.

Disclosure of Invention

The invention provides a power MOSFET device with a low gate resistance and enhanced separation gate and a manufacturing method thereof, and a control gate structure of the trench MOSFET with a separation gate enhanced structure, which is proposed in Chinese patent 201910191166.9 of Qiaming, Wangzhenkang, Zhang wave and the like and U.S. patent US16/536333, is too narrow, and the cross-sectional area of gate current flowing is reduced, so that the gate resistance value is increased, the switching loss of the device is further increased, and the switching speed of the device is reduced. As shown in fig. 1, the present invention is based on the device structure proposed by georgine, wangzhengkang, and zhangbo, and the like, and is adjacent to a third gate electrode above a first gate electrode and a second gate electrode. The third gate electrode actually reduces the gate resistance by making up the conductive area of the polysilicon between the first gate electrode and the second gate electrode in the above structure, and the distance between the left and right side walls of the third gate electrode is slightly larger than the distance between the inner side walls of the first gate electrode and the second gate electrode, so that the parasitic capacitance Cgs and the gate charge Qg of the gate electrode and the source region are controlled not to be degraded, thereby achieving the goals of high switching speed and low switching loss.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a low gate resistance power MOSFET device with a split gate enhancement structure comprises a first conductivity type substrate 10, a first conductivity type epitaxial layer 11 is arranged on the upper surface of the first conductivity type substrate 10, a groove structure 12 is arranged in the first conductivity type epitaxial layer 11, a control gate electrode and a split gate electrode 14 are arranged in the groove structure 12, the control gate electrode comprises a first gate electrode 151, a second gate electrode 152 and a third gate electrode 153, the first gate electrode 151 and the second gate electrode 152 are positioned above the split gate electrode 14 and are separated from the split gate electrode 14 through a second dielectric layer 132, the first gate electrode 151 and the second gate electrode 152 are separated from a second conductivity type well region 16 in the epitaxial layer 11 through a gate dielectric 133, the third gate electrode 153 is positioned above the first gate electrode 151 and the second gate electrode 152 and is adjacent to the first gate electrode 151 and the second gate electrode 152, the split gate electrode 14 is separated from the first conductivity type epitaxial layer 11 through a first dielectric layer 131, a second conductivity type well region 16 is arranged above the first conductivity type epitaxial layer 11, a second conductivity type heavily doped region 18 is arranged above the inside of the second conductivity type well region 16, a first conductivity type heavily doped source region 19 is arranged above the second conductivity type well region 16, a metal 20 is led out in the second conductivity type heavily doped region 18, and the metal 20 and the control gate electrode are separated by a third dielectric layer 134.

Preferably, the lower half of the control gate electrode is a first gate electrode 151 and a second gate electrode 152 separated by a dielectric layer, the upper half is a third gate electrode structure 153 adjacent to the first gate electrode and the second gate electrode, and the third gate electrode is equivalent to transferring polysilicon between the first gate electrode and the second gate electrode to the upper surfaces of the first gate electrode and the second gate electrode to increase the effective conductive area of the gate electrode.

Preferably, the upper surface of the third gate electrode 153 is higher than the upper surface of the first conductive-type heavily doped source region 19.

Preferably, the second dielectric layer 132 is a low-k material.

Preferably, the first dielectric layer 131 is a low-k material.

Preferably, the method for manufacturing the low gate resistance power MOSFET device with the split gate enhancement structure comprises the following steps:

1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;

2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;

3) etching the polysilicon deposited in the step 2), and forming a separation gate electrode at the lower half part of the control gate groove of the active region;

4) forming a second dielectric layer in the groove of the active region and on the upper part of the separation gate;

5) forming a gate dielectric covering the side wall on the upper half part of the control gate groove in the active region; depositing polycrystalline silicon in the active region, and forming a first gate electrode and a second gate electrode which cover the side wall of the upper half part of the control gate groove after etching;

6) depositing a third dielectric layer to isolate the first gate electrode from the second gate electrode, and selectively etching the dielectric layer at the central part of the control gate groove to be lower than the upper surfaces of the first gate electrode and the second gate electrode in the step 5);

7) depositing and etching polysilicon in the active area to form a third gate electrode, wherein the upper surface of the third gate electrode is not higher than that of the third dielectric layer deposited in the step 6);

8) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;

9) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.

Preferably, the width of the opening of the mask for etching the third dielectric layer in the step 6) is not less than the distance between the inner side walls of the first gate electrode and the second gate electrode.

To achieve the above object, the present invention further provides a method for manufacturing a low gate resistance power MOSFET device having a split gate enhancement structure, comprising the steps of:

1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;

2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;

3) etching the polysilicon deposited in the step 2), and forming a separation gate electrode at the lower half part of the control gate groove of the active region;

4) forming a second dielectric layer in the groove of the active region and on the upper part of the separation gate;

5) forming a gate dielectric covering the side wall on the upper half part of the control gate groove in the active region; depositing polycrystalline silicon in the active region, and forming a first gate electrode and a second gate electrode which cover the side wall of the upper half part of the control gate groove after etching;

6) depositing a third dielectric layer to isolate the first gate electrode from the second gate electrode, and selectively etching the dielectric layer at the central part of the control gate groove to be lower than the upper surfaces of the first gate electrode and the second gate electrode in the step 5);

7) depositing and etching polysilicon in the active area to form a third gate electrode, wherein the upper surface of the third gate electrode is not higher than that of the third dielectric layer deposited in the step 6);

8) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;

9) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.

The invention has the beneficial effects that: the invention increases the effective cross-sectional area of gate current flow by increasing the upper surface of the third gate electrode adjacent to the first gate electrode and the second gate electrode, reduces the resistance value of the gate, and simultaneously, controls the parasitic capacitance Cgs from the gate electrode to the source region and the gate charge Qg not to be degraded by adjusting the overlapping area of the third gate electrode and the first and second gate electrodes. The device structure has the characteristics of low gate capacitance and low gate resistance, the aims of high switching speed and low switching loss are fulfilled, and the metal oxide semiconductor field effect transistor with the low-gate-resistance split-gate enhanced structure is obtained.

Drawings

Fig. 1 is a schematic structural diagram of a low-gate-resistance power MOSFET device having a split-gate enhancement structure according to embodiment 1 of the present invention.

Fig. 2 is a process diagram of a method for manufacturing a low gate resistance power MOSFET device with a split-gate enhancement structure according to embodiment 1 of the present invention, which is sequentially from left to right and from top to bottom.

Fig. 3 is a schematic structural view of a low gate resistance power MOSFET device having a split gate enhancement structure of embodiment 2.

Fig. 4 is a schematic structural view of a low gate resistance power MOSFET device having a split gate enhancement structure of embodiment 3.

The active matrix substrate is a first conductive type substrate 10, a first conductive type epitaxial layer 11, a trench structure 12, a first dielectric layer 131, a second dielectric layer 132, a gate dielectric layer 133, a third dielectric layer 134, a split gate electrode 14, a first gate electrode 151, a second gate electrode 152, a third gate electrode 153, a second conductive type well region 16, a second conductive type heavily doped region 18, a first conductive type heavily doped source region 19, and a metal 20.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Example 1

As shown in fig. 1, a low gate resistance power MOSFET device with a split gate enhancement structure comprises a first conductivity type substrate 10, a first conductivity type epitaxial layer 11 is arranged on the upper surface of the first conductivity type substrate 10, a trench structure 12 is arranged in the first conductivity type epitaxial layer 11, a control gate electrode and a split gate electrode 14 are contained in the trench structure 12, the control gate electrode comprises a first gate electrode 151, a second gate electrode 152 and a third gate electrode 153, the first gate electrode 151 and the second gate electrode 152 are positioned above the split gate electrode 14 and are separated from the split gate electrode 14 by a second dielectric layer 132, the first gate electrode 151 and the second gate electrode 152 are both separated from a second conductivity type well region 16 in the epitaxial layer 11 by a gate dielectric 133, the third gate electrode 153 is positioned above the first gate electrode 151 and the second gate electrode 152 and is adjacent to the first gate electrode 151 and the second gate electrode 152, the split gate electrode 14 is separated from the first conductivity type epitaxial layer 11 by a first dielectric layer 131, a second conductivity type well region 16 is arranged above the first conductivity type epitaxial layer 11, a second conductivity type heavily doped region 18 is arranged above the inside of the second conductivity type well region 16, a first conductivity type heavily doped source region 19 is arranged above the second conductivity type well region 16, a metal 20 is led out in the second conductivity type heavily doped region 18, and the metal 20 and the control gate electrode are separated by a third dielectric layer 134.

The lower half part of the control gate electrode is a first gate electrode 151 and a second gate electrode 152 which are separated by a dielectric layer, the upper half part is a third gate structure 153 which is adjacent to the first gate electrode and the second gate electrode, and the third gate electrode is equivalent to transferring polysilicon between the first gate electrode and the second gate electrode to the upper surfaces of the first gate electrode and the second gate electrode so as to increase the effective conductive area of the gate.

The manufacturing method comprises the following steps:

1) forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner walls of the groove structures;

2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;

3) etching the polysilicon deposited in the step 2), and forming a separation gate electrode at the lower half part of the control gate groove of the active region;

4) forming a second dielectric layer in the groove of the active region and on the upper part of the separation gate;

5) forming a gate dielectric covering the side wall on the upper half part of the control gate groove in the active region; depositing polycrystalline silicon in the active region, and forming a first gate electrode and a second gate electrode which cover the side wall of the upper half part of the control gate groove after etching;

6) depositing a third dielectric layer to isolate the first gate electrode from the second gate electrode, and selectively etching the dielectric layer at the central part of the control gate groove to be lower than the upper surfaces of the first gate electrode and the second gate electrode in the step 5);

7) depositing and etching polysilicon in the active area to form a third gate electrode, wherein the upper surface of the third gate electrode is not higher than that of the third dielectric layer deposited in the step 6);

8) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region;

9) and depositing a dielectric layer, etching a source contact hole in the source region and the separation gate lead-out region, injecting metal and leading out a potential.

Preferably, the width of the opening of the mask for etching the third dielectric layer in the step 6) is not less than the distance between the inner side walls of the first gate electrode and the second gate electrode.

Preferably, the upper surface of the third gate electrode should be higher than the upper surface of the first conductive-type heavily doped source region.

Example 2

As shown in fig. 3, the present embodiment is different from the structure described in embodiment 1 in that: the second dielectric layer 132 is a low-k dielectric, which further reduces the gate-source capacitance.

Example 3

As shown in fig. 4, the present embodiment is different from the structure described in embodiment 1 in that: the second dielectric layer 132 is a low-k dielectric, the first dielectric layer 131 is a low-k dielectric, and the whole split gate electrode is surrounded by the low-k dielectric, so that the gate-source capacitance and the source-drain capacitance can be further reduced.

While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.