阅读说明：本技术 加电时具有自动后台预处理的存储器 (Memory with automatic background pre-processing at power-up ) 是由 A·D·韦切斯 D·M·贝尔 J·S·雷赫迈耶 R·邦内尔 N·J·迈尔 于 2020-08-25 设计创作，主要内容包括：在本文中公开了在加电时具有自动后台预处理的存储器装置和系统以及相关联方法。在一个实施例中,存储器装置包含存储器阵列,所述存储器阵列在存储器行和存储器列的交叉处具有多个存储器单元。所述存储器装置进一步包含对应于所述存储器行的感测放大器。当所述存储器装置通电时,所述存储器装置在执行从用户、存储器控制器或所述存储器装置的主机装置接收的存取命令之前,将所述多个存储器单元中的一或多个存储器单元写入到随机数据状态。在一些实施例中,为了写入所述一或多个存储器单元,所述存储器装置在不为对应的感测放大器供电的同时激发多个存储器行,使得存储在所述多个存储器行的存储器单元上的数据被覆写和损坏。(Memory devices and systems with automatic background pre-processing at power-up and associated methods are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the rows of memory. When the memory device is powered on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows while not powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.)

1. A memory device, comprising:

a memory array including a plurality of memory cells arranged at intersections of memory rows and memory columns,

wherein the memory device is configured to write at least a portion of the memory array to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device during a power-up operation of the memory device.

2. The memory device of claim 1, further comprising a fuse array having antifuse elements corresponding to the memory array, wherein the antifuse elements are configured to store preprocessed data.

3. The memory device of claim 2, wherein the pre-processing data identifies the portion of the memory array.

4. The memory device of claim 3, wherein the memory device is further configured to automatically read the preprocessed data from the fuse array during the power-up operation of the memory device to identify the portion of the memory array prior to execution of the access command.

5. The memory device of claim 1, further comprising sense amplifiers corresponding to the memory rows, and wherein to write the portion of the memory array to the random data state, the memory device is configured to fire a plurality of memory rows of the memory array while not powering corresponding sense amplifiers such that data stored on memory cells of the plurality of memory rows is overwritten and corrupted.

6. The memory device of claim 1, wherein the memory device is further configured to issue more than one activate command to the portion of the memory array to write the portion of the memory array to the random data state.

7. The memory device of claim 1, wherein the portion of the memory array includes each memory cell of the plurality of memory cells.

8. The memory device of claim 1, wherein the portion of the memory array includes only a subset of memory cells of the plurality of memory cells.

9. The memory device of claim 1, wherein the memory device is a Dynamic Random Access Memory (DRAM) device.

10. A method, comprising:

receiving an indication that a memory device is powering on, the memory device comprising a memory array having a plurality of memory cells arranged at intersections of a plurality of memory rows and a plurality of memory columns;

in response to the indication, at least a portion of the memory array is written to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device.

11. The method of claim 10, further comprising, in response to the indication, automatically reading pre-processed data stored on the memory device prior to executing the access command.

12. The method of claim 11, wherein the pre-processing data specifies the portion of the memory array, and wherein the method further comprises loading the pre-processing data into a command decoder of the memory device.

13. The method of claim 10, wherein writing the portion of the memory array to the random data state includes firing a plurality of memory rows in the portion of the memory array while not powering sense amplifiers corresponding to the plurality of memory rows such that data stored on memory cells of the plurality of memory rows is overwritten and corrupted.

14. The method of claim 10, wherein writing the portion of the memory array to the random data state includes issuing more than one activate command to the portion of the memory array.

15. The method of claim 10, further comprising:

receiving (a) an indication that a RESET pin of the memory device is asserted or (b) a pre-process data command; and

in response to the indication that a RESET pin of the memory device is asserted or the pre-process data command, writing the portion of the memory array to the random data state prior to executing an access command.

16. A memory device, comprising:

a memory array having a plurality of memory cells arranged at intersections of memory rows and memory columns; and

a sense amplifier corresponding to the memory row,

wherein

The memory device is configured to write one or more memory cells of the plurality of memory cells to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device, at power up of the memory device,

to write the one or more memory cells to the random data state, the memory device is configured to fire the plurality of memory rows while not powering sense amplifiers corresponding to the plurality of memory rows such that data stored on memory cells of the plurality of memory rows is overwritten and corrupted, an

At least one memory row of the plurality of memory rows corresponds to the one or more memory cells.

17. The memory device of claim 16, wherein to write the one or more memory cells to the random data state, the memory device is further configured to issue more than one activate command to a memory area containing the one or more memory cells.

18. The memory device of claim 17, wherein the memory area includes only a subset of the memory cells of the plurality of memory cells.

19. The memory device of claim 16, wherein the one or more memory cells include each memory cell of the plurality of memory cells.

20. The memory device of claim 16, further comprising a fuse array having antifuse elements corresponding to the memory array, wherein the antifuse elements are configured to store preconditioning data, and wherein the preconditioning data identifies the one or more memory cells.

21. The memory device of claim 20, wherein the memory device is further configured to read the preprocessed data from the fuse array during the power-up operation of the memory device to identify the one or more memory cells prior to execution of the access command.

Technical Field

The present disclosure relates to memory systems, devices, and associated methods. In particular, the present disclosure relates to memory devices with automatic background pre-processing at power-up.

Background

Memory devices are widely used to store information related to various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. In computers or other electronic devices, memory devices are typically provided as internal, semiconductor, integrated circuit, and or external removable devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), may require the application of power to maintain its data. In contrast, a non-volatile memory can retain its stored data even when no external power is supplied. Non-volatile memory may be used in a variety of technologies including flash memory (e.g., NAND and NOR) Phase Change Memory (PCM), ferroelectric random access memory (FeRAM), Resistive Random Access Memory (RRAM), and Magnetic Random Access Memory (MRAM), among others. Improving memory devices may generally include increasing memory cell density, increasing read/write speed, or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.

Disclosure of Invention

In one aspect, the present disclosure relates to a memory device comprising: a memory array comprising a plurality of memory cells arranged at intersections of memory rows and memory columns, wherein the memory device is configured to write at least a portion of the memory array to a random data state prior to execution of an access command received from a user, a memory controller, or a host device for the memory device during a power-up operation of the memory device.

In another aspect, the present disclosure relates to a method comprising: receiving an indication that a memory device is powering on, the memory device comprising a memory array having a plurality of memory cells arranged at intersections of a plurality of memory rows and a plurality of memory columns; in response to the indication, at least a portion of the memory array is written to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device.

In a further aspect, the present disclosure relates to a memory device comprising: a memory array having a plurality of memory cells arranged at intersections of memory rows and memory columns; and sense amplifiers corresponding to the memory rows, wherein-the memory device is configured to write one or more of the plurality of memory cells to a random data state prior to executing an access command received from a user, a memory controller, or a host device of the memory device at power-up of the memory device, to write the one or more memory cells to the random data state, the memory device is configured to fire the plurality of memory rows while not powering the sense amplifiers corresponding to the plurality of memory rows such that data stored on the memory cells of the plurality of memory rows is overwritten and corrupted, and at least one of the plurality of memory rows corresponds to the one or more memory cells.

Drawings

Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Emphasis instead being placed upon clearly illustrating the principles of the present disclosure. The drawings should not be taken to limit the disclosure to the specific embodiments depicted, but are for explanation and understanding only.

FIG. 1 is a block diagram that schematically illustrates a memory system configured in accordance with various embodiments of the present technology.

FIG. 2 is a flow diagram illustrating a background pre-processing routine of a memory device configured in accordance with various embodiments of the present technology.

FIG. 3 is a schematic diagram of a system including a memory device configured in accordance with various embodiments of the present technique.

Detailed Description

As discussed in more detail below, the techniques disclosed herein relate to memory systems and devices (and associated methods) that pre-process all or a subset of a memory array to a desired state as part of a background operation that is automatically performed when the memory device is powered on. However, those skilled in the art will appreciate that the techniques may have additional embodiments, and that the techniques may be practiced without several of the details of the embodiments described below with reference to fig. 1-3. In the embodiments illustrated below, the memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured in accordance with other embodiments of the present technology may include other types of memory devices and systems that incorporate other types of storage media including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (eprom), electrically erasable programmable ROM (eerom), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and/or NOR) storage media.

A host memory system typically includes one or more memory devices for storing information. The host memory system may employ one or more security measures to prevent malicious actors from reading and/or manipulating information when the memory device is installed in the host memory system. For example, when a malicious actor issues a read request identifying a memory address corresponding to a restricted portion of a memory array of a memory device, the host memory system may prevent the malicious actor from accessing information stored in the restricted portion of the memory array by returning an error message and/or invalid data in response to the read request. As another example, the host memory system may limit certain commands (e.g., read, write, or other access commands) to only authorized users.

When the information is stored on the memory cells of a volatile memory device, the host system is configured to periodically refresh the memory cells to prevent data loss due to charge leakage. When the volatile memory device is powered down or otherwise disconnected from power, the memory cells of the volatile memory device are no longer refreshed. Without an intermediate power supply, charge leaks from the memory cell until the information stored on the memory cell is corrupted (e.g., can no longer be read accurately). However, this damage process is not immediate. Thus, the information may remain accurately readable for a period of time after the volatile memory device is powered down or otherwise disconnected from the power source. As a result, a malicious actor may potentially extract information stored on a conventional memory device by quickly transferring (e.g., hot-swapping) the conventional memory device from a host memory system to a hostile memory system that does not employ the security measures described above or is configured to circumvent such security measures.

To address this issue, several embodiments of the present technology are directed to memory devices, systems including memory devices and methods of operating memory devices in which memory cells in a memory array of a memory device are programmed to a desired (predetermined) state as part of background operations that are automatically performed during power-up of the memory device (e.g., before the memory device performs access or other commands received from a user, a memory controller, and/or a host device). In some embodiments, the desired state may be a known state (e.g., a predetermined data string) stored in a fuse array of the memory device. In these and other embodiments, the memory device may automatically program all or a subset of the memory array to a known state when the memory device is powered on. In these and other embodiments, the desired state may be a random (e.g., corrupted) state, and the memory device may automatically program all or a subset of the memory array to random states during power-up by firing rows of memory cells in the memory array without powering the corresponding sense amplifiers, such that nearby rows of memory cells overwrite each other with their data and are corrupted. Under either approach, after the memory device is powered down or otherwise disconnected from power, any valid information that persists on the memory cells is automatically overwritten and/or corrupted when the memory device is powered on.

FIG. 1 is a block diagram that schematically illustrates a memory system 190 configured in accordance with an embodiment of the present technology. Memory system 190 may include memory device 100, which memory device 100 may be connected to any one of a number of electronic devices or components thereof that are capable of utilizing memory to store information either temporarily or permanently. For example, memory device 100 may be operatively connected to host device 108 and/or memory controller 101. For example, host device 108 is operatively connected to memory device 100, which memory device 100 may be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet, digital reader, digital media player), or some component thereof (e.g., a central processing unit, co-processor, dedicated memory controller, etc.). The host device 108 may be a networked device (e.g., switch, router, etc.) or a recorder of digital images, audio, and/or video, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, host device 108 may be directly connected to memory device 100, although in other embodiments host device 108 may be indirectly connected to memory device 100 (e.g., through a network connection or through an intermediate device, such as through memory controller 101).

Memory device 100 may employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal receiving the chip select signal CS, a clock terminal receiving the clock signals CK and CKF, a data clock terminal receiving the data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, and power supply terminals VDD, VSS, and VDDQ.

The power supply terminals of the memory device 100 may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in sense amplifiers included in the memory array 150 of the memory device 100, and the internal potential VPERI may be used in many other circuit blocks.

The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input/output (IO) circuit 160 together with the power supply potential VSS. In the embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential than the power supply potential VDD. However, the dedicated power supply potential VDDQ may be used for the IO circuit 160 so that power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, as may the WCK and WCKF signals. The complementary clock signals may have opposite clock levels and transition between the opposite clock levels at the same time. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Further, the complementary clock signal transitions from the high clock level to the low clock level when the clock signal transitions from the low clock level to the high clock level, and transitions from the low clock level to the high clock level when the clock signal transitions from the high clock level to the low clock level.

An input buffer included in the clock input circuit 120 may receive an external clock signal. For example, the input buffers may receive the CK and CKF signals and the WCK and WCKF signals when enabled by the CKE signal from the command decoder 115. The clock input circuit 120 may receive an external clock signal to generate the internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may provide various phase and frequency controlled internal clock signals based on the internal clock signal ICLK and the clock enable signal CKE received from the command decoder 115. For example, the internal clock circuit 130 may include a clock path (not shown in FIG. 1) that receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. Internal clock circuit 130 may further provide an input/output (IO) clock signal. The IO clock signal may be supplied to the IO circuit 160, and may be used as a timing signal for determining output timing of read data and input timing of write data. The IO clock signals may be provided at multiple clock frequencies so that data may be output from and input into the memory device 100 at different data rates. When high memory speeds are desired, higher clock frequencies may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 135 and, thus, may generate various internal clock signals that may be used by the command decoder 115, the column decoder 145, and/or other components of the memory device 100.

Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in a plurality of memory regions, and each memory region may contain a plurality of Word Lines (WLs), a plurality of Bit Lines (BLs), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. In some embodiments, a memory region may be one or more banks of memory, one or more rows of memory in a bank of memory, or another arrangement of memory cells. In these and other embodiments, the memory regions of the memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory banks, one or more logical memory ranks or dies, etc.). The memory cells in memory array 150 may comprise any of a number of different memory media types including capacitive, magnetoresistive, ferroelectric, phase change, and the like. The selection of the word lines WL may be performed by the row decoder 140 and the selection of the bit lines BL may be performed by the column decoder 145. A corresponding bit line BL may be provided with a Sense Amplifier (SAMP) and connected to at least one respective local I/O line pair (LIOT/B), which in turn may be coupled to at least one respective main I/O line pair (MIOT/B) via a Transmission Gate (TG), which may act as a switch. Memory array 150 may also include plate lines and corresponding circuitry for managing its operation.

The command terminal and the address terminal may be supplied with an address signal and a bank address signal from the outside of the memory device 100. The address signal and the bank address signal supplied to the address terminal may be transmitted to the address decoder 110 via the command/address input circuit 105. The address decoder 110 may receive address signals and supply decoded row address signals (XADD) to the row decoder 140 and decoded column address signals (YADD) to the column decoder 145. The address decoder 110 may also receive a bank address signal (BADD) and supply both the bank address signal to the row decoder 140 and the column decoder 145.

The command and address terminals may be supplied with command signals CMD, address signals ADDR, and chip select signals CS (e.g., from memory controller 101 and/or host device 108). The command signals may represent various memory commands (e.g., including access commands, which may include read commands and write commands). The select signal CS may be used to select the memory device 100 in response to commands and addresses provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, commands and addresses may be decoded and memory operations may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the command/address input circuit 105. The command decoder 115 may include circuitry to decode the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. The internal command signals may also include output and input activate commands, such as clock control command CMDCK (not shown) to the command decoder 115. The command decoder 115 may further include one or more registers 118 for tracking various counts or values (e.g., a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100; memory regions enabled for refresh operations; memory cells, memory rows, memory ranks, memory banks, logical memory banks or dies, and/or other memory regions that were last programmed and/or are to be programmed; etc.).

When a read command is issued, and a row address and a column address are timely supplied with the read command, read data may be read from memory cells in the memory array 150 specified by the row address and the column address. The read command may be received by the command decoder 115, and the command decoder 115 may provide internal commands to the IO circuit 160, outputting read data from the data terminals DQ, RDQS, DBI, and DMI via the read/write (RW) amplifier 155 and the IO circuit 160 according to the RDQS clock signal. The read data may be provided at a time defined by read latency information RL, which may be programmed, for example, in the memory device 100 in a mode register (not shown in fig. 1). The read latency information RL may be defined according to the clock period of the CK clock signal. For example, when providing associated read data, the read latency information RL may be a number of clock cycles of the CK signal after the memory device 100 receives a read command.

When a write command is issued and a row address and a column address are timely supplied with commands, write data may be supplied to the data terminals DQ, DBI, and DMI according to WCK and WCKF clock signals. The write command may be received by command decoder 115, which may provide an internal command to IO circuitry 160 so that write data may be received by a data receiver in IO circuitry 160 and supplied to memory array 150 via IO circuitry 160 and RW amplifiers 155. Write data may be written into the memory cells specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write latency WL information. The write latency WL information may be programmed in the memory device 100, for example, in a mode register (not shown in fig. 1). The write latency WL information may be defined according to a clock cycle of the CK clock signal. For example, when receiving associated write data, the write latency information WL may be a number of clock cycles of the CK signal after the memory device 100 receives a write command.

As described herein, the memory array 150 may be refreshed or maintained to prevent data loss due to charge leakage or imprint effects. As described herein, a refresh operation may be initiated by memory system 190 (e.g., by host device 108, memory controller 101, and/or memory device 100) and may include accessing one or more rows (e.g., WLs) and discharging cells of the accessed row to a corresponding SAMP. When a row is opened (e.g., when an accessed WL is activated), SAMP may compare the voltage generated by the discharged cell to a reference value. Then, SAMP may write back the logical value (e.g., charge the cell) to the nominal value for the given logical state. In some cases, this write-back process may increase the charge of the cell to improve the discharge problem described above. In other cases, the write-back process may invert the data state of the cell (e.g., from high to low or from low to high) to improve hysteresis shift, material depolarization, and so forth. Other refresh schemes or methods may also be employed.

In one approach, the memory device 100 may be configured to simultaneously refresh the same row of memory cells in each bank of the memory array 150. In another approach, the memory device 100 may be configured to sequentially refresh the same row of memory cells in each bank of the memory array 150. In yet another approach, the memory device 100 may further include circuitry (e.g., one or more registers, latches, embedded memory, counters, etc.) configured to track row (e.g., word line) addresses, each row address corresponding to one of the banks of memory in the memory array 150. In this approach, memory device 100 is not limited to refreshing the same row in each bank of memory array 150 before refreshing another row in one of the banks of memory.

Regardless of the refresh method, the memory device 100 can be configured to refresh memory cells in the memory array 150 within a given refresh rate or time window (e.g., 32ms, 28ms, 25ms, 23ms, 21ms, 18ms, 16ms, 8ms, etc.). In these embodiments, the memory system 190 may be configured to supply refresh commands to the memory device 100 according to a specified minimum cadence tREFI. For example, memory system 190 may be configured to supply one or more refresh commands to memory device 100 at least every 7.8 μ s, such that approximately a minimum of 4000 refresh commands are supplied to memory device 100 within a 32ms time window.

Memory device 100 may include fuse array 143. Fuse array 143 may include anti-fuse elements. The antifuse element is an element which is insulated in an initial state and is switched to a conductive state when subjected to dielectric breakdown by a connecting operation. After the antifuse element is switched to a conductive state, the antifuse element cannot return to an insulating state. Thus, the anti-fuse elements of fuse array 143 can be used as non-volatile and non-volatile memory elements. The anti-fuse elements of fuse array 143 may be programmed using conventional anti-fuse programming circuitry (not shown).

In some embodiments, the anti-fuse elements of fuse array 143 may be programmed to store preprocessed data. For example, the antifuse elements may be programmed with preconditioning data that specifies that a portion (e.g., all or a subset) of the memory array 150 should be programmed to a known state when the memory device is powered on. For example, a known state may comprise a predetermined string or sequence of data bits (e.g., all "1 s"; all "0 s"; alternating "1 s" and "0 s"; or another string/sequence of data bits) to program to each memory row in a portion of memory array 150. In these and other embodiments, the antifuse elements may be programmed with preconditioning data that identifies a portion (e.g., all or a subset) of the memory array 150 for preconditioning when the memory device is powered on.

As described in more detail below, when memory device 100 is powered on, memory device 100 may be configured to automatically read the preprocessed data from fuse array 143. In embodiments where the pre-processed data specifies a known state to which a portion of memory array 150 should be programmed, the known state may be automatically loaded into I/O circuitry 160 and subsequently (automatically) written to a portion (all or a subset) of memory array 150. In this manner, any valid information remaining in the memory array 150 of the memory device 100 can be automatically overwritten when the memory device 100 is powered on. In these and other embodiments, where the pre-processed data identifies a portion of the memory array 150 for pre-processing, the pre-processed data may be automatically read into the command decoder 115 of the memory device 100. Using the pre-processed data, the command decoder 115 may generate various internal signals and commands for performing pre-processing operations, such as row command signals and column select signals for selecting memory rows and columns, respectively, in the portion of the memory array 150 identified in the pre-processed data. In turn, the memory device 100 may automatically pre-process the portion of the memory array 150 identified in the pre-processed data to a desired state (e.g., a known or random state).

To program the portion of memory array 150 to a random state, memory device 100 may be configured to automatically fire multiple memory rows in the portion of memory array 150 without powering the corresponding sense amplifiers, such that nearby memory rows overwrite each other with their data and are corrupted. Thus, any valid information remaining in the portion of memory array 150 may be automatically corrupted when memory device 100 is powered on. Preconditioning a portion of memory array 150 to a random state is faster and consumes less power than preconditioning a portion of memory array 150 to a known state because memory device 100 does not retrieve and load the known state into IO circuitry 160 or another component of memory device 100, or power a corresponding sense amplifier, before preconditioning a portion of memory array 150. Thus, memory device 100 may be configured to precondition a portion of memory array 150 to a random state in a time or power efficient situation.

FIG. 2 is a flow diagram illustrating a background pre-processing routine 250 of a memory device configured in accordance with various embodiments of the present technology. In some embodiments, the routine 250 may be performed, at least in part, by various components of a memory device. For example, all or a subset of the steps of routine 250 may be performed by a fuse array, a command decoder, an IO circuit, and/or a memory array of a memory device.

The routine 250 may begin at block 251 by receiving an indication that the memory device is being powered on. In some embodiments, the indication that the memory device is powering on may be a voltage generator supplied to the memory device and/or one or more potentials generated by the voltage generator of the memory device. In response to the indication, the routine 250 may automatically proceed to block 252 and/or block 253. In this manner, the routine 250 may be automatically executed without user intervention as an internal background operation of the memory device. In other words, the routine 250 may be performed automatically before the memory device performs an access (e.g., read or write) or other command performed from a user, the memory controller, and/or a host device of the memory device. In other embodiments, the routine 250 may begin at block 251 when one or more other events occur. For example, the routine 250 may begin at block 251 by receiving an indication that a RESET pin of the memory device is asserted and/or that a user has issued a pre-process data command or sequence (e.g., a data "self-destruct" command).

At block 252, the routine 250 retrieves the pre-processed data. All or a subset of the pre-processed data may be stored in the fuse array and/or another component of the memory device. In some embodiments, preprocessing data may include instructions to preprocess a portion of a memory array to a desired state. For example, preprocessing data may include instructions to preprocess a portion of the memory array to a known state and/or may specify a predetermined string or sequence of data bits (e.g., all "1 s"; all "0 s"; alternating "1 s" and "0 s"; or another string/sequence of data bits) to program into the portion of the memory array. In these and other embodiments, preprocessing data may include instructions to preprocess a portion of a memory array to a random or corrupted state. In these and other embodiments, the pre-processing data may identify a portion of the memory array to pre-process. For example, the pre-processing data may include instructions to pre-process the entire memory array to a desired state. In other embodiments, preprocessing data may include instructions to preprocess a subset of a memory array (e.g., a particular memory row, a particular bank of memory, etc.) to a desired state. After retrieving the preprocessed data, the routine 250 may automatically proceed to block 253 to preprocess a portion of the memory array.

In some embodiments, the routine 250 may be configured to automatically proceed to block 253, from block 251 to preprocess a portion of the memory array to a desired state without retrieving the preprocessed data at block 252. For example, in some embodiments, the desired state may be a random or corrupt state (as described in more detail below) such that the routine 250 does not retrieve a known state specified in the pre-processed data stored on the memory device. In these and other embodiments, the routine 250 may be configured to pre-process all or a subset of the memory array to a desired state (e.g., by default) such that the routine 250 does not retrieve pre-processed data stored on the memory device that identifies a portion of the memory array.

At block 253, the routine 250 preprocesses a portion of the memory array to a desired state. In embodiments where a portion of the memory array is specified in the preprocessed data retrieved at block 252, the routine 250 may load the preprocessed data into a command decoder, which may issue a row select command to a row decoder and a column select command to a column decoder to preprocess the corresponding portion of the memory array to a desired state.

As discussed above, the desired state may be a known state and/or a random state. In embodiments where the desired state is a known state specified in the preprocessed data retrieved at block 252, the routine 250 may preprocess a portion of the memory array (e.g., the portion identified in the preprocessed data) to the desired state by loading the known state into the IO circuitry or another component of the memory device. For example, the routine 250 may power up write latches and/or sense amplifiers corresponding to a memory row in a portion of the memory array to a known state. In turn, the routine 250 may write and/or copy the known state on the portion of the memory array such that the routine 250 overwrites any valid information remaining in the portion of the memory array prior to execution of the routine 250.

Using a volatile double data rate fourth generation (DDR4) memory device as an example, routine 250 may pre-process the memory array of the memory device by entering write compression and writing a known desired state to all banks of the memory array using the X16 memory device configuration. In other embodiments, the routine 250 may use a different memory device configuration (e.g., an X4 and/or X8 memory device configuration). In some embodiments, the routine 250 may use a greater amount of compression than standard, such that the routine 250 may write more than one memory rank at a time. In these and other embodiments, the routine 250 may enter a test mode of the memory device to enable the routine 250 to issue more than one activate command to the memory bank. To write a known state to the memory array, for each portion of the memory bank, routine 250 may (i) activate a memory row in the portion, (ii) write a corresponding bit of the known state to each memory column in the activated memory row, and (iii) precharge the memory row. Assuming the memory row of the DDR4 memory device includes 2000 bits, routine 250 (in this example) issues 16 write commands to fully program the memory row. Thus, assuming 1024 memory rows per section and 512 sections in the memory array, routine 250 (in this example) may pre-process the entire memory array in approximately 0.05 ms.

In embodiments where the desired state is a random or corrupted state, routine 250 may preprocess a portion of the memory array (e.g., the portion identified in the preprocessed data retrieved at block 252) to a random state by stepping through the portion of the memory array in a similar manner (e.g., using compression), but by activating multiple memory rows without powering sense amplifiers corresponding to the memory rows. In this manner, nearby (e.g., adjacent) memory lines are overwritten and corrupted with their data, such that the routine 250 corrupts any valid information that persists in a portion of the memory array before the routine 250 is executed. As discussed above, by preconditioning the portion of the memory array to a random state, the routine 250 may save time and power to precondition the portion of the memory array to a known state.

Although the steps of the routine 250 are discussed and illustrated in a particular order, the method illustrated by the routine 250 in FIG. 2 is not so limited. In other embodiments, the methods may be performed in a different order. For example, any step of the routine 250 may be performed before, during, and/or after any other step of the routine 250. Moreover, one of ordinary skill in the related art will readily recognize that the illustrated method may be varied and still remain within these and other embodiments of the present technology. For example, one or more steps of the routine 250 shown in fig. 2 may be omitted and/or repeated in some embodiments.

Further, although DDR4 memory devices are used in the above example, the routine 250 in other embodiments may be used to pre-process other memory devices. For example, the routine 250 may be used to pre-process a memory array of a non-volatile memory device. In these and other embodiments, the routine 250 may be used to pre-process memory devices that use another generation of DDR (e.g., first generation DDR, second generation DDR, third generation DDR, fifth generation DDR, etc.). In these and other embodiments, the routine 250 may be used to pre-process memory arrays having a greater or lesser number of banks, sections per bank, rows of memory per section, columns of memory, and/or columns of memory per row of memory.

In some embodiments, the routine 250 may be enabled or disabled permanently or temporarily. For example, the routine 250 may be enabled (e.g., by the manufacturer, by the end party, by an intermediary party, etc.) as a security feature on the memory device. When enabled, the routine 250 executes automatically without user intervention as a background operation when the memory device is powered on (e.g., each time, next time, selected subsequent time, etc.). In these and other embodiments, the routine 250 may be disabled such that the routine 250 is not executed at one or more subsequent power ups of the memory device. For example, an authorized user (e.g., a vendor, service technician, etc.) may disable the routine 250 to test the device, save power, and/or save data (e.g., in the event of an error, failure, and/or hang-up of the host memory system in which the memory device is installed). In these and other embodiments, the routine 250 may be disabled only when a previous power-up (e.g., a most recent power-up) of the memory device is performed.

In some embodiments, routine 250 may be enabled or disabled using anti-fuse elements of a fuse array. For example, when the first antifuse element is subjected to dielectric breakdown through a connecting operation, routine 250 may be permanently enabled or disabled when the first antifuse element transitions to a conductive state. In other embodiments, routine 250 may be temporarily enabled or disabled when the first antifuse element is transitioned to a conductive state (e.g., until the second antifuse element is transitioned to a conductive state). In these and other embodiments, the routine 250 may switch between enabling and disabling. For example, routine 250 can be disabled when a first anti-fuse element is switched to a conductive state, enabled when a second anti-fuse element is subsequently switched to a conductive state, disabled when a third anti-fuse element is subsequently switched to a conductive state, and so on.

FIG. 3 is a schematic diagram of a system including a memory device in accordance with embodiments of the present technique. Any of the foregoing memory devices described above with reference to fig. 1 and 2 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is the system 390 schematically shown in fig. 3. The system 390 may include a semiconductor device assembly 300, a power supply 392, a driver 394, a processor 396, and/or other subsystems and components 398. The semiconductor device assembly 300 may include features substantially similar to the memory devices described above with reference to fig. 1 and 2, and thus may include various features that automatically background pre-process upon power-up. The resulting system 390 can perform any of a variety of functions, such as memory storage, data processing, and/or other suitable functions. Thus, representative systems 390 may include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 390 may be housed in a single unit or distributed across multiple interconnected units (e.g., over a communications network). The components of system 390 may also include remote devices and any of a variety of computer-readable media.

Conclusion

The above detailed description of embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. While specific embodiments of, and examples for, the technology are described above for illustrative purposes, various equivalent modifications are possible within the scope of the technology, as those skilled in the relevant art will recognize. For example, while steps are presented and/or discussed in a given order, alternative embodiments may perform steps in a different order. Furthermore, the various embodiments described herein may also be combined to provide further embodiments.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. Where the context permits, singular or plural terms may also encompass plural or singular terms, respectively. Further, unless the word "or" is expressly limited to only a single item and not to other items of a list of two or more items, the use of "or" in such lists is to be construed as encompassing (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also encompass plural or singular terms, respectively. In addition, the terms "comprising," "including," "having," and "having" are used throughout to mean including at least the recited features, such that any greater number of the same features and/or other types of other features are not excluded. As used herein, the phrase "and/or" in "a and/or B" refers to a alone, B alone, and both a and B.

From the foregoing, it will also be appreciated that various modifications may be made without departing from the technology. For example, various components of the technology may be further divided into sub-components, or various components and functions of the technology may be combined and/or integrated. Moreover, while advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated techniques may encompass other embodiments not explicitly shown or described herein.