Delay circuit, method, circuit for preventing signal from false triggering and integrated circuit
阅读说明：本技术 一种延时电路、方法、防止信号误触发电路和集成电路 (Delay circuit, method, circuit for preventing signal from false triggering and integrated circuit ) 是由 李征 朱伟东 于 2020-07-14 设计创作，主要内容包括：本发明实施例公开了一种延时电路、方法、防止信号误触发电路和集成电路,其中,延时电路包括：上升沿延时电路和下降沿延时电路；所述上升沿延时电路采用组合逻辑电路,用于对输入信号的上升沿进行延时；所述下降沿延时电路采用组合逻辑电路,用于对输入信号的下降沿进行延时。本发明实施例的技术方案中延时电路不使用寄存器,只使用最基本的组合逻辑电路就能达到现有模拟、数字延时方法同等的延时效果,而且与现有模拟、数字延时方法相比,本发明实施例的技术方案中延时电路所需芯片面积小,成本低,降低了芯片功耗低,契合目前集成电路精密化、小型化的发展趋势,适宜推广应用。(The embodiment of the invention discloses a delay circuit, a method, a circuit for preventing signal false triggering and an integrated circuit, wherein the delay circuit comprises: a rising edge delay circuit and a falling edge delay circuit; the rising edge delay circuit adopts a combinational logic circuit and is used for delaying the rising edge of the input signal; the falling edge delay circuit adopts a combinational logic circuit and is used for delaying the falling edge of the input signal. The delay circuit in the technical scheme of the embodiment of the invention does not use a register, can achieve the same delay effect of the existing analog and digital delay methods only by using the most basic combinational logic circuit, and compared with the existing analog and digital delay methods, the technical scheme of the embodiment of the invention has the advantages of small chip area required by the delay circuit, low cost, low chip power consumption, conformity with the development trend of the precision and miniaturization of the existing integrated circuit, and suitability for popularization and application.)
1. A delay circuit, comprising: a rising edge delay circuit and a falling edge delay circuit; the rising edge delay circuit adopts a combinational logic circuit and is used for delaying the rising edge of an input signal; the falling edge delay circuit adopts a combinational logic circuit and is used for delaying the falling edge of the input signal.
2. The delay circuit of claim 1, wherein the rising edge delay circuit comprises: the first NAND gate, the second NAND gate, the third rising edge delay NOT gate, the fourth NAND gate, the fifth NAND gate, the sixth rising edge delay NOT gate, the seventh NAND gate, the eighth NAND gate and the ninth rising edge delay NOT gate; wherein the content of the first and second substances,
The first input end of the first NAND gate is connected with an input signal, the output of the first NAND gate is connected to the input end of a third rising edge delay NOT gate and the first input end of a second NAND gate, the output of the third rising edge delay NOT gate is connected to the first input end of a fourth NAND gate, and the output of the fourth NAND gate is connected to the input end of a sixth rising edge delay NOT gate and the first input end of a fifth NAND gate; the output of the fifth NAND gate is connected to the second input end of the second NAND gate and the second input end of the fourth NAND gate, the output of the sixth rising edge delay NOT gate is connected to the first input end of the seventh NAND gate, the output of the seventh NAND gate is connected to the input end of the ninth rising edge delay NOT gate and the first input end of the eighth NAND gate, the output of the eighth NAND gate is connected to the second input end of the fifth NAND gate and the second input end of the seventh NAND gate, a clock signal (CLK) is connected to the second input end of the eighth NAND gate, and the output of the ninth rising edge delay NOT gate is connected to the final output end of the circuit.
3. The delay circuit of any one of claims 1 or 2, wherein the falling edge delay circuit comprises: a first nor gate, a second nor gate, a third falling edge delay nor gate, a fourth nor gate, a fifth nor gate, a sixth falling edge delay nor gate, a seventh nor gate, an eighth nor gate, and a ninth falling edge delay nor gate; wherein the content of the first and second substances,
A first input end of the first NOR gate is connected with an input signal, an output end of the first NOR gate is connected to an input end of the third falling edge delay NOR gate and a first input end of the second NOR gate, an output end of the third falling edge delay NOR gate is connected to a first input end of the fourth NOR gate, and an output end of the fourth NOR gate is connected to an input end of the sixth falling edge delay NOR gate and a first input end of the fifth NOR gate; an output of the fifth nor gate is connected to a second input terminal of the second nor gate and a second input terminal of the fourth nor gate, an output of the sixth falling edge delaying nor gate is connected to a first input terminal of the seventh nor gate, an output of the seventh nor gate is connected to an input terminal of the ninth falling edge delaying nor gate and a first input terminal of the eighth nor gate, an output of the eighth nor gate is connected to a second input terminal of the fifth nor gate and a second input terminal of the seventh nor gate, a clock signal (CLK) is connected to a second input terminal of the eighth nor gate, and an output of the ninth falling edge delaying nor gate is connected to a final output terminal of the circuit.
4. The delay circuit of claim 2, wherein the output of the fifth nand gate in the rising edge delay circuit is directly connected to the corresponding input of the fourth nand gate without passing through any other logic gate, and then the corresponding inputs of the second nand gate and the fourth nand gate are connected; the output of the eighth nand gate in the rising edge delay circuit is directly connected to the corresponding input end of the seventh nand gate without any other logic gate, and then the corresponding input ends of the fifth nand gate and the seventh nand gate are connected.
5. The delay circuit of claim 3, wherein the output of the fifth NOR gate in the falling edge delay circuit is directly connected to the corresponding input of the fourth NOR gate without passing through any other logic gate, and then the corresponding inputs of the second and fourth NOR gates are connected; the output of the eighth nor gate in the falling edge delay circuit is directly connected to the corresponding input terminal of the seventh nor gate without passing through any other logic gate, and then the corresponding input terminals of the fifth nor gate and the seventh nor gate are connected.
6. A method of delaying a time, comprising:
the rising edge delay circuit provided by the above embodiment delays the rising edge of the input signal, and the process is as follows:
when the input signal IN is 0, the first nand gate does not need to judge the state of the output V2 of the second nand gate, the output V1 of the first nand gate is directly 1, and the output V3 of the third rising edge delay not-use gate immediately becomes 0; the fourth nand gate does not need to judge the state of the output V5 of the fifth nand gate, and the output V4 of the fourth nand gate is directly 1; the output V6 of the sixth rising edge delay not gate immediately becomes 0; the seventh nand gate does not need to judge the state of the output V8 of the eighth nand gate, the output V7 of the seventh nand gate is directly 1, and the output of the ninth rising edge delay not-gate, that is, the output of the final output OUT of the circuit becomes 0;
When the input signal IN changes from 0 to 1, the output V1 of the first nand gate remains 1 until the control clock signal changes to 0, and the output V1 of the first nand gate cannot change from 1 to 0, and then the output V3 of the third rising-edge-delay not gate changes to 1; the output V4 of the fourth nand gate remains 1 until the control clock signal becomes 1, and the output V4 of the fourth nand gate cannot change from 1 to 0, and then the output V6 of the sixth rising edge delay not gate becomes 1; the output V7 of the seventh nand gate remains 1 until the control clock signal becomes 0 again, and the output V7 of the seventh nand gate cannot change from 1 to 0, and the final output OUT of the circuit becomes 1.
7. The delay method of claim 6, further comprising:
the falling edge delay circuit provided by the above embodiment delays the falling edge of the input signal, and the process is as follows:
when the input signal IN is 1, the first nor gate does not need to determine the state of the output V2 of the second nor gate, the output V1 of the first nor gate is directly 0, and the output V3 of the third falling edge delay nor gate immediately becomes 1; the nor gate 4 does not need to judge the state of the output V5 of the fifth nor gate, and the output V4 of the fourth nor gate is directly 0; the output V6 of the sixth falling edge delay not gate immediately becomes 1; the seventh nor gate does not need to judge the state of the output V8 of the eighth nor gate, the output V7 of the seventh nor gate is directly 0, and the output of the ninth falling edge delay nor gate, that is, the final output OU of the circuit, becomes 1;
When the input signal IN changes from 1 to 0, the output V1 of the first nor gate remains 0 until the control clock signal changes to 1, and the output V1 of the first nor gate cannot change from 0 to 1, and then the output V3 of the third falling-edge-delay nor gate changes to 0; the output V4 of the fourth nor gate remains 0 until the control clock signal becomes 0, and the output V4 of the fourth nor gate cannot change from 0 to 1, whereupon the output V6 of the sixth falling-edge-delay nor gate becomes 0; the output V7 of the seventh nor gate remains 0 until the control clock signal becomes 1 again, and the output V7 of the seventh nor gate cannot change from 0 to 1, whereupon the final output OUT of the circuit becomes 0.
8. A circuit for preventing false triggering of a signal, comprising the delay circuit according to any one of claims 1 to 7; short-time pulses are filtered out through the delay circuit, so that signal false triggering is prevented.
9. An integrated circuit comprising the delay circuit of any one of claims 1 to 7.
10. An integrated circuit comprising the signal false triggering prevention circuit of claim 8.
Technical Field
The embodiment of the invention relates to the field of electronic circuits, in particular to a delay circuit, a delay method, a circuit for preventing signal false triggering and an integrated circuit.
Background
The integrity of the signal is critical to the proper operation of the integrated circuit. During transmission, signals are interfered by other signals or environments, and signal distortion is caused. For example: in the context of a switching power supply, two power transistors connected in a half-bridge manner switch at high speed between on and off states, as shown in fig. 1a to 1 f. Such switching results in a voltage varying at a high rate at the output point VSW of the half bridge, usually the point of connection of the inductor. The magnitude of the voltage change is between the input voltage VIN and ground GND, and the speed of the change is in the order of nanoseconds (ns). Such a signal that changes at a high speed greatly easily affects other signals nearby by coupling of parasitic capacitances on the circuit board. The affected signal can produce a short pulse, i.e., a "glitch," and falsely trigger the circuitry it controls. For example: if the signal that generates the "glitch" is a circuit enable signal, the low "glitch" will cause the circuit to stop operating. Therefore, when receiving a signal, it is necessary to filter the glitch to prevent false triggering.
Currently, it is common practice to filter "glitches" by adding delay circuits. If the change in the signal is less than the specified time, the change is ignored. Changes greater than this time are identified as true changes and further processed. The methods for implementing the delay can be divided into analog and digital methods. The method of simulation is to use a low pass filter, as shown in fig. 2. The low-pass filter composed of the resistor and the capacitor can effectively filter out transient changes of the input signal. The longer the delay time, the longer the "glitch" width that can be filtered, the lower the probability of false triggering, but the larger the area of resistance and capacitance that is required. For example: the technology of 0.18um filters 1us of 'burr', the required resistance and capacitance are about 1M omega and 2pF, and the area occupied by the layout is about 1600um ^2 (without routing, isolating ring and safety distance meeting the design specification, etc.). The digital approach is to use logic circuits. The most common approach is via a register implementation, such as the D flip-flop based implementation shown in fig. 3a and 3 b. Fig. 3a and 3b delay the rising and falling edges of the input signal IN, respectively. Under a clock CLK with a 50% duty ratio, the time of delaying is 0.5-1.5 times of the CLK period. For example: the clock period is at least 2us to filter out 1us "glitches". If the clock period is less than the minimum, the desired period can be achieved by the divider circuit. Since the digital method relies on a clock circuit, it is more suitable for systems with clocks, such as: switching power supplies, and the like. The area for implementing the circuit is about
In summary, both the analog and digital methods for implementing delay require a large chip area, and the digital methods for implementing delay also require registers, which occupy too many precious area resources of the chip, thus not only having high cost, but also causing power consumption waste because the chip area is in direct proportion to the power consumption.
The above problems are urgently needed to be solved.
Disclosure of Invention
To solve the related art problems, the present invention provides a delay circuit, a delay method, a circuit for preventing signal false triggering, and an integrated circuit, so as to solve the problems mentioned in the background section above.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides a delay circuit, including: a rising edge delay circuit and a falling edge delay circuit; the rising edge delay circuit adopts a combinational logic circuit and is used for delaying the rising edge of an input signal; the falling edge delay circuit adopts a combinational logic circuit and is used for delaying the falling edge of the input signal.
Further, the rising edge delay circuit includes: the first NAND gate, the second NAND gate, the third rising edge delay NOT gate, the fourth NAND gate, the fifth NAND gate, the sixth rising edge delay NOT gate, the seventh NAND gate, the eighth NAND gate and the ninth rising edge delay NOT gate; wherein the content of the first and second substances,
The first input end of the first NAND gate is connected with an input signal, the output of the first NAND gate is connected to the input end of a third rising edge delay NOT gate and the first input end of a second NAND gate, the output of the third rising edge delay NOT gate is connected to the first input end of a fourth NAND gate, and the output of the fourth NAND gate is connected to the input end of a sixth rising edge delay NOT gate and the first input end of a fifth NAND gate; the output of the fifth NAND gate is connected to the second input end of the second NAND gate and the second input end of the fourth NAND gate, the output of the sixth rising edge delay NOT gate is connected to the first input end of the seventh NAND gate, the output of the seventh NAND gate is connected to the input end of the ninth rising edge delay NOT gate and the first input end of the eighth NAND gate, the output of the eighth NAND gate is connected to the second input end of the fifth NAND gate and the second input end of the seventh NAND gate, a clock signal (CLK) is connected to the second input end of the eighth NAND gate, and the output of the ninth rising edge delay NOT gate is connected to the final output end of the circuit.
Further, the falling edge delay circuit includes: a first nor gate, a second nor gate, a third falling edge delay nor gate, a fourth nor gate, a fifth nor gate, a sixth falling edge delay nor gate, a seventh nor gate, an eighth nor gate, and a ninth falling edge delay nor gate; wherein the content of the first and second substances,
A first input end of the first NOR gate is connected with an input signal, an output end of the first NOR gate is connected to an input end of the third falling edge delay NOR gate and a first input end of the second NOR gate, an output end of the third falling edge delay NOR gate is connected to a first input end of the fourth NOR gate, and an output end of the fourth NOR gate is connected to an input end of the sixth falling edge delay NOR gate and a first input end of the fifth NOR gate; an output of the fifth nor gate is connected to a second input terminal of the second nor gate and a second input terminal of the fourth nor gate, an output of the sixth falling edge delaying nor gate is connected to a first input terminal of the seventh nor gate, an output of the seventh nor gate is connected to an input terminal of the ninth falling edge delaying nor gate and a first input terminal of the eighth nor gate, an output of the eighth nor gate is connected to a second input terminal of the fifth nor gate and a second input terminal of the seventh nor gate, a clock signal (CLK) is connected to a second input terminal of the eighth nor gate, and an output of the ninth falling edge delaying nor gate is connected to a final output terminal of the circuit.
Furthermore, the output of a fifth nand gate in the rising edge delay circuit is directly connected to the corresponding input end of a fourth nand gate without passing through any other logic gate, and then the corresponding input ends of the second nand gate and the fourth nand gate are connected; the output of the eighth nand gate in the rising edge delay circuit is directly connected to the corresponding input end of the seventh nand gate without any other logic gate, and then the corresponding input ends of the fifth nand gate and the seventh nand gate are connected.
Furthermore, the output of a fifth NOR gate in the falling edge delay circuit is directly connected to the corresponding input end of a fourth NOR gate without any other logic gate, and then the corresponding input ends of the second NOR gate and the fourth NOR gate are connected; the output of the eighth nor gate in the falling edge delay circuit is directly connected to the corresponding input terminal of the seventh nor gate without passing through any other logic gate, and then the corresponding input terminals of the fifth nor gate and the seventh nor gate are connected.
In a second aspect, an embodiment of the present invention further provides a delay method, including:
the rising edge delay circuit provided by the above embodiment delays the rising edge of the input signal, and the process is as follows:
when the input signal IN is 0, the first nand gate does not need to judge the state of the output V2 of the second nand gate, the output V1 of the first nand gate is directly 1, and the output V3 of the third rising edge delay not-use gate immediately becomes 0; the fourth nand gate does not need to judge the state of the output V5 of the fifth nand gate, and the output V4 of the fourth nand gate is directly 1; the output V6 of the sixth rising edge delay not gate immediately becomes 0; the seventh nand gate does not need to judge the state of the output V8 of the eighth nand gate, the output V7 of the seventh nand gate is directly 1, and the output of the ninth rising edge delay not-gate, that is, the output of the final output OUT of the circuit becomes 0;
When the input signal IN changes from 0 to 1, the output V1 of the first nand gate remains 1 until the control clock signal changes to 0, and the output V1 of the first nand gate cannot change from 1 to 0, and then the output V3 of the third rising-edge-delay not gate changes to 1; the output V4 of the fourth nand gate remains 1 until the control clock signal becomes 1, and the output V4 of the fourth nand gate cannot change from 1 to 0, and then the output V6 of the sixth rising edge delay not gate becomes 1; the output V7 of the seventh nand gate remains 1 until the control clock signal becomes 0 again, and the output V7 of the seventh nand gate cannot change from 1 to 0, and the final output OUT of the circuit becomes 1.
Further, the time delay method further includes:
the falling edge delay circuit provided by the above embodiment delays the falling edge of the input signal, and the process is as follows:
when the input signal IN is 1, the first nor gate does not need to determine the state of the output V2 of the second nor gate, the output V1 of the first nor gate is directly 0, and the output V3 of the third falling edge delay nor gate immediately becomes 1; the nor
When the input signal IN changes from 1 to 0, the output V1 of the first nor gate remains 0 until the control clock signal changes to 1, and the output V1 of the first nor gate cannot change from 0 to 1, and then the output V3 of the third falling-edge-delay nor gate changes to 0; the output V4 of the fourth nor gate remains 0 until the control clock signal becomes 0, and the output V4 of the fourth nor gate cannot change from 0 to 1, whereupon the output V6 of the sixth falling-edge-delay nor gate becomes 0; the output V7 of the seventh nor gate remains 0 until the control clock signal becomes 1 again, and the output V7 of the seventh nor gate cannot change from 0 to 1, whereupon the final output OUT of the circuit becomes 0.
In a third aspect, an embodiment of the present invention further provides a circuit for preventing a signal from being triggered erroneously, including the delay circuit provided in the foregoing embodiment; short-time pulses are filtered out through the delay circuit, so that signal false triggering is prevented.
In a fourth aspect, an embodiment of the present invention further provides an integrated circuit, which includes the delay circuit provided in the foregoing embodiment.
In a fifth aspect, embodiments of the present invention further provide an integrated circuit, which includes the circuit for preventing signal mis-triggering provided in the foregoing embodiments.
In the technical scheme of the embodiment of the invention, the delay circuit comprises a rising edge delay circuit and a falling edge delay circuit; the rising edge delay circuit delays the rising edge of the input signal by adopting a combinational logic circuit; the falling edge delay circuit delays the falling edge of the input signal by adopting a combinational logic circuit. The delay circuit in the technical scheme of the embodiment of the invention does not use a register, can achieve the same delay effect of the existing analog and digital delay methods only by using the most basic combinational logic circuit, and compared with the existing analog and digital delay methods, the technical scheme of the embodiment of the invention has the advantages of small chip area required by the delay circuit, low cost, low chip power consumption, conformity with the development trend of the precision and miniaturization of the existing integrated circuit, and suitability for popularization and application.
Drawings
In order to more clearly illustrate and understand the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the background and the embodiments of the present invention will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
FIGS. 1a to 1f are schematic diagrams illustrating the operation principle of step-down DC/DC;
FIG. 2 is a schematic diagram of the delay generated by the simulation method;
FIG. 3a is a schematic circuit diagram of a D-flip-flop based delay of the rising edge of an input signal IN;
FIG. 3b is a schematic circuit diagram of a D flip-flop based delay of the rising edge of the input signal IN;
fig. 4 is a diagram of a rising edge delay circuit according to an embodiment of the present invention;
fig. 5 is a flowchart of a rising edge delay circuit according to an embodiment of the present invention to implement rising edge delay;
fig. 6a is a diagram of simulation results of rising edge delay according to a first embodiment of the present invention: a delay of about 1.5 times the period of CLK;
fig. 6b is a diagram of simulation results of rising edge delay according to a first embodiment of the present invention: a delay of about 0.5 times the period of CLK;
fig. 6c is a diagram of simulation results of rising edge delay according to a first embodiment of the present invention: a delay of about 1 time the period of CLK;
FIG. 7 is a diagram of a falling edge delay circuit according to an embodiment of the present invention;
fig. 8 is a flowchart of a falling edge delay circuit according to an embodiment of the present invention to implement rising edge delay;
fig. 9a is a diagram of simulation results of falling edge delay according to an embodiment of the present invention: a delay of about 1.5 times the period of CLK;
Fig. 9b is a diagram of a simulation result of falling edge delay according to an embodiment of the present invention: a delay of about 0.5 times the period of CLK;
fig. 9c is a diagram of simulation results of falling edge delay according to an embodiment of the present invention: a delay of about 1 time the period of CLK;
FIG. 10a is a diagram illustrating the chip area required for generating delay in the simulation method;
FIG. 10b illustrates the chip area required to generate the delay using conventional digital methods;
fig. 10c shows a chip area required for generating the delay by the delay circuit according to the first embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
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