阅读说明：本技术 通过基于可编程计数器的时钟接口和具有高分辨率和宽操作范围的时间数字转换器进行时钟筛选 (Clock screening by programmable counter based clock interface and time to digital converter with high resolution and wide operating range ) 是由 吴争争 黄德平 J·M·辛里奇斯 M·佩德拉利-诺伊 于 2019-01-24 设计创作，主要内容包括：公开了一种分级时间数字转换器(110),TDC,其包括两个环形振荡器(205,210),该两个环形振荡器(205,210)用于确定两个时钟边沿之间的时间差。在一些实现方式中,TDC包括慢振荡器(205),其被配置为响应于第一时钟边沿而振荡慢振荡器输出信号；粗略计数器(220),其被配置为响应于慢振荡器输出信号的周期而对粗略计数进行计数；快振荡器(210),其被配置为响应于第二时钟边沿而振荡快振荡器输出信号；以及精细计数器(225),其被配置为响应于快振荡器输出信号的周期而对精细计数进行计数,其中快振荡器输出信号的频率大于慢振荡器输出信号的频率。(A hierarchical time-to-digital converter (110), TDC, is disclosed that includes two ring oscillators (205, 210), the two ring oscillators (205, 210) being used to determine a time difference between two clock edges. In some implementations, the TDC includes a slow oscillator (205) configured to oscillate a slow oscillator output signal in response to a first clock edge; a coarse counter (220) configured to count a coarse count in response to a period of the slow oscillator output signal; a fast oscillator (210) configured to oscillate a fast oscillator output signal in response to a second clock edge; and a fine counter (225) configured to count the fine counts in response to a period of the fast oscillator output signal, wherein a frequency of the fast oscillator output signal is greater than a frequency of the slow oscillator output signal.)

1. A time-to-digital converter for measuring time between a first clock edge and a second clock edge, comprising:

a slow oscillator configured to oscillate a slow oscillator output signal in response to the first clock edge;

a coarse counter configured to count a coarse count in response to a period of the slow oscillator output signal;

a fast oscillator configured to oscillate a fast oscillator output signal in response to the second clock edge; and

a fine counter configured to count a fine count in response to a period of the fast oscillator output signal, wherein a frequency of the fast oscillator output signal is greater than a frequency of the slow oscillator output signal.

2. The time-to-digital converter of claim 1, further comprising:

a phase detector configured to latch the coarse counter in response to detecting that the phase of the slow oscillator output signal leads the phase of the fast oscillator output signal.

3. The time-to-digital converter of claim 2, wherein the phase detector is further configured to latch the fine counter in response to the detecting.

4. A time to digital converter as recited in claim 1, wherein said fast oscillator is a first ring oscillator, and wherein said slow oscillator is a second ring oscillator.

5. A time to digital converter as recited in claim 4 wherein said first ring oscillator comprises a first set of at least three inverters and wherein said second ring oscillator comprises a second set of at least three inverters.

6. The time-to-digital converter of claim 1, further comprising:

a first current source configured to sink a first current before the first clock edge and not sink the first current after the first clock edge, wherein the first current is a replica of an operating current drawn by the slow oscillator; and

A second current source configured to sink a second current before the second clock edge and not to sink the second current after the second clock edge, wherein the second current is a replica of an operating current drawn by the fast oscillator.

7. The time-to-digital converter of claim 1, further comprising:

a clock interface configured to select from a plurality of clock signals to generate the first clock edge and the second clock edge.

8. The time to digital converter of claim 7, wherein the clock interface comprises a down converter configured to down convert a selected clock signal from the plurality of clock signals to generate the second clock edge.

9. The time to digital converter of claim 8, wherein the clock interface further comprises decision logic configured to enable clocking of a first selected flip-flop from a plurality of flip-flops by the first clock edge and to enable clocking of a second selected flip-flop from the plurality of flip-flops by the second clock edge.

10. The time to digital converter of claim 7, further comprising tuning logic configured to tune a first delay circuit for delaying a first clock signal having the first clock edge in response to a series of clock measurements.

11. A method, comprising:

oscillating a slow oscillator output signal in response to a first clock edge;

oscillating a fast oscillator output signal in response to a second clock edge subsequent to the first clock edge, wherein a frequency of the fast oscillator output signal is greater than a frequency of the slow oscillator output signal;

counting cycles of the slow oscillator output signal to count a coarse count;

counting cycles of the fast oscillator output signal to count fast counts; and

measuring a delay between a first clock edge and the second clock edge in response to a function of the coarse count and the fine count to form a measure of the delay.

12. The method of claim 11, further comprising:

measuring a cycle jitter of a clock signal having the first clock edge and the second clock edge in response to the measuring of the delay.

13. The method of claim 11, further comprising:

measuring K cycle period jitter of a clock signal having the first clock edge and the second clock edge in response to the measuring of the delay.

14. The method of claim 11, wherein the first clock edge is a rising edge of a clock signal and the second clock edge is a falling edge of the clock signal, the method further comprising: measuring a duty cycle of the clock signal in response to the measurement of the delay.

15. The method of claim 11, wherein the first clock edge is a clock edge of a reference clock signal, and wherein the second clock edge is a clock edge of a phase-locked loop (PLL) clock signal, the method further comprising: measuring a time internal error of the PLL clock signal in response to the measuring of the delay.

16. The method of claim 11, wherein the first clock edge is an edge of an early clock signal, and wherein the second clock edge is an edge of a late clock signal, the method further comprising: in response to the measurement of the delay, measuring a clock skew between the early clock signal and the late clock signal.

17. A digital phase locked loop, comprising:

an accumulator for determining a reference phase from a reference clock signal;

a loop filter configured to filter a phase error between the reference phase and a variable phase to generate a control word;

a digitally controlled oscillator for oscillating a clock output signal in response to the control word; and

a time-to-digital converter configured to measure a delay between a first clock edge of the clock output signal and a second clock edge of the reference clock signal to generate the variable phase, wherein the time-to-digital converter comprises a first ring oscillator and a second ring oscillator, the first ring oscillator configured to oscillate a first oscillator output signal in response to the first clock edge; the second ring oscillator is configured to oscillate a second oscillator output signal in response to the second clock edge, and wherein the time-to-digital converter is configured to measure the delay in response to a period of the first oscillator output signal and in response to a period of the second oscillator output signal.

18. The digital phase locked loop of claim 17 wherein the first ring oscillator comprises three inverters.

19. The digital phase locked loop of claim 17, wherein the second ring oscillator comprises three inverters.

20. The digital phase locked loop of claim 17, wherein the time-to-digital converter further comprises a phase detector for detecting when a phase of the first oscillator output signal leads a phase of the second oscillator output signal.

Technical Field

The present application relates to clock measurement, and more particularly to hierarchical (sub-ranging) time-to-digital clock measurement.

Background

Modern devices such as smartphones and tablets require very stringent clock performance standards for their various subsystems such as digital cores, data converters and frequency synthesizers. For example, the clock performance of the digital core must meet low cycle jitter and low duty cycle error. Also, the data converter requires a clock signal with low absolute jitter (time internal error (TIE)). In addition, frequency synthesizers require clock signals with low phase noise and reduced fractional spurs. Emerging self-driving automotive applications also require stringent clock performance.

To ensure that such stringent clock performance standards are maintained, modern devices often incorporate on-chip clock screening for automatic monitoring purposes or for immediate monitoring purposes. However, conventional clock screening techniques do not address all of the various clock measurement modes, such as cycle jitter, K-cycle jitter, TIE jitter, duty cycle variations, clock skew, and the like. One difficulty that hinders the conventional approach from providing a circuit with uniform clock performance is as follows: this universal clock performance screening requires high resolution, wide input frequency range, and high robustness at the same time. In an attempt to meet these different requirements, existing designs typically employ delay cells to implement time-to-digital (TDC) converters for clock jitter and clock skew measurements. However, meeting high resolution and wide input frequency range requires the use of a large number of delay cells of a conventional flash TDC or Vernier TDC architecture, which occupies a large chip area and increases power consumption. Moreover, such multiple delay cells are prone to handle variations, thereby reducing test robustness and producing erroneous clock screening results.

Accordingly, there is a need in the art for a clock screening circuit that includes a time-to-digital converter that is insensitive to process variations and also includes a clock interface that supports multiple modes for screening various clock performance metrics.

Disclosure of Invention

To provide increased accuracy and frequency input range, a hierarchical time-to-digital converter (TDC) is disclosed that measures a time difference between a first clock edge and a second edge of a clock signal using a fine count and a coarse count. The TDC includes a slow oscillator that begins oscillating a slow oscillator output signal in response to a first clock edge. The coarse counter counts a coarse count in response to the slow oscillator output signal. The TDC also includes a fast oscillator that begins oscillating the fast oscillator output signal in response to a second clock edge, which may arrive later or earlier than the first clock edge. The fine counter counts the fine count in response to the fast oscillator output signal. The TDC may be integrated into a clock measurement circuit that may make a wide variety of clock measurements, such as cycle jitter measurements, K-cycle jitter measurements, duty cycle measurements, Time Internal Error (TIE) measurements, and clock skew measurements. These and other advantageous features will be better appreciated from the following detailed description.

Drawings

Fig. 1 is a block diagram of a clock measurement circuit according to one aspect of the present disclosure.

Fig. 2A is a circuit diagram of a time-to-digital converter (TDC) according to one aspect of the present disclosure.

Figure 2B is a timing diagram of the slow oscillator output signal, the fast oscillator output signal, and the latch command of the TDC of figure 2A.

Figure 3 is a circuit diagram of a stabilized power architecture of the TDC of figure 2A.

Fig. 4A is a circuit diagram for a clock interface circuit according to one aspect of the present disclosure.

Fig. 4B is a timing diagram of a PLL clock signal and two clock edges selected from the PLL clock signal by the clock interface circuit of fig. 4B.

Figure 5A is a graph of ideal TDC output as a function of TDC input.

Figure 5B is a graph of actual TDC output as a function of TDC input.

Figure 6 is a circuit diagram of a TDC including a tunable digital-to-time converter (DTC) for improved linearity according to one aspect of the present disclosure.

Figure 7 illustrates three example histograms recorded by the TDC of figure 6.

Figure 8 is a block diagram of an all-digital phase-locked loop (PLL) including a TDC in accordance with one aspect of the present disclosure.

The implementations of the present disclosure and their advantages are best understood by referring to the following detailed description. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

Detailed Description

Turning now to the drawings, FIG. 1 shows a clock measurement circuit 100 (which may also be referred to as a built-in self test (BIST) circuit). The clock measurement circuit 100 includes a clock interface 105 that supports multiple clock screening modes of operation, such as cycle jitter measurement, K-cycle jitter measurement, duty cycle measurement, clock skew, and internal error in Time (TIE) measurement. Clock interface 105 is quite advantageous because the conventional need for multiple clock measurement circuits for such different clock test modes is eliminated. Depending on the measurement mode, the clock interface 105 will select two clock edges from one or more input clock signals. For example, clock interface 105 may select a Phase Locked Loop (PLL) clock signal to perform cycle jitter measurement, duty cycle measurement, and K-cycle jitter measurement, as will be further explained herein. It should be appreciated that the PLL clock signal may be replaced by other clock signals being measured, such as a Delay Locked Loop (DLL) clock signal or other suitable clock source. In clock skew measurement, the clock interface 105 selects a first clock edge, such as a clock signal received from a clock tree output node, and a second clock edge, such as another clock signal received from another clock tree output node. The first clock edge or the second clock edge may be earlier than the remaining clock edges of the first clock edge and the second clock edge. Thus, the resulting time-digital measurement can measure a positive or negative time difference between two clock edges, depending on whether the first clock edge is earlier or later than the second clock edge. To perform TIE measurements, the clock interface 105 selects edges of a clock signal, such as a PLL clock signal, and edges of a reference clock signal (Ref CLK), such as a crystal oscillator signal.

One of the clock edges selected by clock interface 105 will lead the remaining selected clock edges. The delay between these two selected clock edges is measured by a time-to-digital converter (TDC) 110. As further explained herein, the TDC110 is formed using a hierarchical architecture that includes a pair of ring oscillators (not shown in fig. 1), each including at least three inverters. Thus, the TDC110 is compact, but achieves high resolution over a wide input frequency range. The controller 115 controls the clock interface 105 and the TDC110 and their interaction. The output of the TDC110 is a digital bit corresponding to a measurement of the delay between two clock edges. The processing of such digits into various clock measurements is known to those of ordinary skill in the clock measurement art and will not be discussed herein. It should be appreciated, however, that a post-processing controller (not shown) may receive the digital output from the TDC110 and process it into a desired measurement such as clock skew, cycle jitter, etc.

Figure 2A shows the TDC110 in more detail. As discussed above, the clock interface 105 of fig. 1 has selected two clock edges from the clock signal it receives as a function of the desired clock measurement. The clock edge type (rising or falling) also depends on the desired clock measurement. For example, a period jitter measurement or a K-period jitter measurement may include selecting two rising clock edges such as shown in fig. 2A. Alternatively, two falling clock edges may be selected for such measurement. The selected clock signal edge that leads the remaining selected clock edges is represented in FIG. 2A as the CLK early signal, while the lagging selected clock signal edge is represented as CLK late. The rising edge of the CLK-early signal triggers the slow oscillator 205 to begin oscillating, such as in response to the enable signal En1 being asserted on the rising edge. As the name implies, the slow oscillator 205 oscillates more slowly than the fast oscillator 210, the fast oscillator 210 triggering oscillation by the rising edge of the CLK late signal (such as by a corresponding assertion of the enable signal En 2). Depending on the delay (Δ t) between the CLK early edge and the CLK late edge, the slow oscillator 205 oscillates the slow oscillator output signal for a certain number of oscillation cycles before triggering the fast oscillator 210 to oscillate its fast oscillator output signal.

The slow oscillator output signal clocks the coarse counter 220 to begin counting cycles of the slow oscillator output signal, while the fast oscillator output signal clocks the fine counter 225 to begin counting cycles of the fast oscillator output signal. When the fast oscillator 210 begins oscillating, the first period of the fast oscillator output signal generally lags in phase the slow oscillator output signal from the slow oscillator 205. The fast oscillator output signal will then take a certain number of oscillation cycles before the slow oscillator output signal lags the fast oscillator output signal. Phase detector 215 detects when the fast oscillator output signal catches up in phase and begins to lead the slow oscillator output signal and triggers coarse counter 220 and fine counter 225 to latch their counts. The latched count of the fine counter 225 may be designated as Nfine.

Fig. 2B shows an example timing diagram of a slow oscillator output signal (which is referred to as OSC slow) and a fast oscillator output signal (which is referred to as OSC fast). The delay Δ t (fig. 2A) between the CLK early signal and the CLK late signal is equal to the sum of the coarse delay (Δ tcoarse) and the fine delay (Δ tfine). To distinguish between the periods of the slow and fast oscillator signals, the period of the slow oscillator output signal is denoted herein as Tslow, while the period of the fast oscillator output signal is denoted herein as Tfast. In fig. 2B, the slow oscillator output signal oscillates through two Tslow periods before the rising edge of the fast oscillator output signal plus a fraction of another Tslow period. The total delay deltat is equal to two Tslow periods plus this additional part of the Tslow period. The coarse count Ncoarse is equal to an integer number of Tslow periods between the CLK early edge and the CLK late edge. Thus, it can be seen that the delay Δ t is equal to Ncoarse Tslow + Nfine (Tslow-Tfast). Note that in an alternative implementation, coarse counter 220 may be latched in response to a CLK late edge. In this implementation, Ncoarse is equal to the count latched by coarse counter 220. As shown in fig. 2B, if the coarse counter 220 is latched in conjunction with the fine counter 215, the TDC 110 may adjust the count latched by the coarse counter 220 accordingly to obtain Ncoarse. If the delay Δ t handled by the TDC 110 is negative, the fast oscillator 210 starts earlier than the slow oscillator 205. The counts from the coarse and fine counters 220, 225 may then be collected in a manner similar to that shown in FIG. 2B to solve for a negative time difference value with respect to the TDC input Δ t. Using the counter latch method of fig. 2B, the sign of the difference between counter 220 and counter 225 after latching indicates the polarity of the input Δ t.

Prior to the clock measurement, controller 115 may calibrate the desired ratio between Tslow and Tfast, such as by comparison to a reference clock signal. For example, the controller 115 may count the number of oscillation cycles of the slow oscillator 205 and the fast oscillator 210 in one or more reference clock cycles. The controller 115 will then adjust the frequency tuning word of the slow oscillator 205 and/or the frequency tuning word of the fast oscillator 210 to force the desired relationship between Tslow and Tfast and their absolute values.

The time measurement made by the TDC 110 should be robust to voltage variations in its supply voltage. Variations in the current drawn from the chip power supply or from the slow and fast oscillators 205, 210 may cause the supply voltage of the TDC 110 to fluctuate, which affects the accuracy of the desired clock measurement. Fig. 3 illustrates a robust power scheme for the TDC 110. The oscillator power domain 315 powers the slow oscillator 205 and the fast oscillator 210 based on an oscillator supply voltage Vreg _ out from a linear regulator 305, which linear regulator 305 is isolated from the chip supply and smoothed by a decoupling capacitor Cdecap. The linear regulator 305 converts its own regulator supply voltage Vdd _ IP to supply and regulate the oscillator supply voltage Vreg _ out. However, the regulator supply voltage Vdd _ IP is affected by package and chip parasitics 310 as represented by parasitic inductance Lpar and parasitic capacitance Rpar. To prevent package and chip parasitics 310 from causing the oscillator supply voltage Vreg _ out to dip when the slow 205 and fast 210 oscillators begin to oscillate, the oscillator power domain 315 includes virtual current source loads 320 and 315. The virtual current source load 320 is configured to draw the same current as the current drawn by the slow oscillator 205. Note that the slow oscillator 205 may include as few as three inverters 330 arranged to form a ring oscillator. This is advantageous compared to the typically larger number of delay circuits required by conventional TDC designs. Likewise, the fast oscillator 210 is formed using three inverters 335 arranged to form a ring oscillator. The virtual current source load 325 is configured to draw the same current as the fast oscillator 210.

As discussed with respect to fig. 2, the TDC 110 measures the time delay Δ t between two clock edges. In fig. 3, the two clock edges are denoted Clk1 and Clk2, respectively. For clarity, in fig. 3, the two clock edges are shown as directly driving their corresponding oscillators (fast or slow) without the intermediate enable signals En1 and En2 discussed with respect to fig. 2. The rising edge of the Clk1 signal causes the slow oscillator 205 to start oscillating and draw its operating current. Before the rising edge arrives, the virtual current source load 320 sinks a replica of the operating current. The virtual current source load 320 is configured to stop sinking the replica operating current in response to the rising edge of the Clk1 signal. Therefore, triggering the slow oscillator 205 does not disturb the oscillator supply voltage because there is no need for a sudden current due to the absence of triggering the slow oscillator 205. Likewise, virtual current source load 235 sinks a replica of the operating current drawn by fast oscillator 210 and is configured to stop sinking the replica operating current in response to the rising edge of Clk2 signal. Thus, triggering the fast oscillator 210 also does not result in the need for a sudden current that can disturb the oscillator supply voltage Vreg _ out. In this manner, the clock measurements described herein may be robust to supply voltage variations caused by, for example, package and chip parasitics 310.

Fig. 4A shows the clock interface 105 in more detail. Down counter 405 responds to the enable signal by updating a Q signal bus (counter signal, typically represented in binary) that is clocked by the selected clock signal. As discussed with respect to fig. 1, the clock interface 105 may select from among a plurality of clock signals depending on a clock measurement mode. For example, the clock interface 105 may include a clock multiplexer (not shown) that selects the appropriate clock signal to clock the flip-flops in the down counter 405. In a K-cycle jitter measurement, clock edges that are K cycles apart are tracked by the down counter 405 and detected by the decision logic 412 for selection so that the time delay Δ t between them can be measured by the TDC 110. A series of K flip-flops within the down counter 405 form a binary counter in which a Q signal bus reports count values in response to a selected clock signal. Decision logic circuit 412 detects the Q signal and asserts the enable signal and the D input signal to flip-flops 420 and 425 to generate clock edges that are K cycles apart. The process repeats itself periodically when the down counter 405 is set to roll over and run continuously. In fig. 4A, it is assumed that the clock multiplexer selects the PLL clock signal (PLL _ clk) such that the down counter 405 is clocked by the PLL clock signal, but it will be appreciated that the selected clock signal may be different in alternative implementations depending on the clock measurement mode.

In addition to flip-flops 420 and 425, decision logic 412 may assert enable signals to output flip-flops 415 and 430. The enabling of a given one of the flip-flops is dependent on the clock measurement. For example, in duty cycle measurement of the PLL clock signal, decision logic 412 may enable output flip-flops 415 and 420. The output flip-flop 420 is clocked by the rising edge of the PLL clock signal. In such duty cycle measurements, the down counter 405 may be bypassed or the down counter 405 may be included, with only one of its flip-flops selected. Thus, the output flip-flop 420 will register a binary one value in response to the rising edge of the PLL clock signal. The TDC 110 (fig. 1) receives the asserted output from the output flip-flop (flip-flow)420 as a first clock edge. The falling edge of the PLL clock signal clocks the output flip-flop 415, so the output flip-flop 415 will assert its output in response to the falling edge of the PLL clock signal, which occurs after the rising edge that clocks the output flip-flop 420. The TDC 110 receives the asserted output from the output flip-flop 415 as a second clock edge. In such duty cycle measurement, the delay Δ T between two clock edges is equal to the on-time or pulse width of the PLL output clock signal. The duty cycle measurement is done by forming the ratio between the pulse width and the period of the PLL clock signal.

In jitter measurement (period or K-period jitter measurement), the output flip-flop 420 is triggered by the first edge of the selected clock signal. In a K-cycle jitter measurement, the down counter 405 and decision logic 412 may select a rising edge K cycles after being asserted by the output flip-flop (flip-flow) 405. For example, as shown in the timing diagram of fig. 4B, a rising edge of the PLL clock signal at time t1 may trigger the output flip-flop 420. The delay controlled by the down counter 405 and the decision logic 412 in the K-cycle jitter measurement depends on an integer number K of clock cycles. In a K-cycle measurement of K-4, the down counter 405 is configured to select a rising edge at time t2 four clock cycles after time t 1. The TDC 110 will then measure the delay between times t1 and t2 to perform such K-cycle jitter measurements. In contrast, in the period jitter measurement, the output flip-flop 425 is enabled to capture the first rising edge after time t 1. In the TIE measurement mode, the reference clock signal (ref _ clk) clocks the output flip-flop 430 to capture the rising edge of the reference clock signal. The output flip-flop 425 will then capture the appropriate edge of the PLL clock signal to complete the selection of the two clock edges of the TDC 110 in the TIE measurement. In clock skew measurement, a similar output flip-flop (not shown) is enabled to capture the appropriate edge. Thus, it should be appreciated that output flip-flops 415-430 are merely representative of output flip-flops that may be included in clock interface 105. An output clock multiplexer (not shown) will then select the output signal from the appropriate output flip-flop to present the two selected clock edges to the TDC 110.

The hierarchical measurement by the TDC 110 solves the prior art problem of providing increased resolution over a wide input frequency range while maintaining a compact area and low circuit complexity. However, the accuracy of its measurement depends on the appropriate relationship between the period of the fast oscillator 210, the period of the slow oscillator 205, and the TDC input mode. For implementations in which the period of the fast oscillator output signal is five times faster than the period of the slow oscillator signal, the ideal relationship results in a linear relationship between the input and output of the TDC 110, as shown in figure 5A. Coarse counter 220 (fig. 2A) will increment a single coarse quantizer integer step size within which fine counter 225 (fig. 2A) will count five times. Since the slow and fast oscillator output signals are perfectly combined with knowledge of the exact period, the final output of the TDC 110 (which is designated as the sum of the coarse and fine quantizers) is linear over an input range of 0 to 20.

However, such a linear relationship between the input and output of the TDC 110 is difficult to achieve due to systematic errors and non-idealities. For example, for one implementation, fig. 5B illustrates a non-linear relationship between input and output where ideally the period of the fast oscillator output signal is exactly 1/20 times the period of the slow oscillator output signal. However, due to non-idealities, the period of the slow oscillator 205 and the fast oscillator 210 obtained after calibration has a limited error compared to their ideal values. In one commonly encountered case, starting at input level zero, the output of the TDC 110 (designated as the hierarchical quantizer output in fig. 5B) will gradually exceed the desired value (the fine counter has counted 20 times) at the end of each coarse quantizer increment. Thus, each time the coarse quantizer increments, which corresponds to the beginning of each successive cycle of the slow oscillator output signal, the discontinuity in the output of the TDC 110 is large. If the time difference to be measured produces a TDC output over such a discontinuity, the TDC measurement is affected by systematic errors, such as highlighted in FIG. 5B for the input level 60. In contrast, if the input to be measured occurs in the middle of the coarse quantizer increment (such as about 85 to 95 for the input range, as highlighted in fig. 5B), the desired linear relationship between input and output is preserved.

To avoid discontinuities in the desired linear relationship between the input and output of the TDC 110, the TDC 110 may be configured as shown in fig. 6. The functions of the slow oscillator 205, the fast oscillator 210, the phase detector 215, the coarse counter 220, and the fine counter 220 are as discussed with respect to fig. 2A and 3. However, a selected clock edge (designated CK _ in1) that triggers the slow oscillator 205 is selectively delayed in a delay circuit, which may also be designated as a digital-to-time converter (DTC) 610. The histogram based fine quantizer level detector and DTC tuning logic 605 uses a first tuning Code (Tune Code) based on the fine quantizer output from the fine quantizer 225 and the ratio between the fine quantizer step size and the coarse quantizer step size (ratio _ c2f)₁) DTC 610 is tuned. This ratio can be known from the calibration of the slow oscillator 205 and the fast oscillator 210 discussed previously. The maximum fine quantizer value or output is equal to the proportional ratio _ c2 f. Thus, the ideal region for the TDC input is when the fine quantizer 220 counts to about half the time of ratio _ c2 f. Referring again to fig. 5B, this fine quantizer level produces an input-output relationship for the TDC 110 that avoids discontinuity regions.

As the name implies, the histogram based fine quantizer level detector and DTC tuning logic 605 observes the output of the TDC110 through a series of measurements, such that the resulting histogram reveals whether the fine quantizer output of the TDC110 occurs within the desired ratio _ c2f/2 range for the corresponding coarse quantizer interval. For example, the fine quantizer range within the coarse quantizer interval may be divided into 3 regions: a start interval ranging from 0 to.3 ratio _ c2f, a center interval ranging from 0.3 ratio _ c2f to 0.7 ratio _ c2f, and a final interval ranging from 0.7 ratio _ c2f to ratio _ c2 f. It will be appreciated that each coarse quantizer increment or count may be divided into such fine quantizer intervals. Also, note that the boundary values of the fine quantizer interval may differ from the example just given. Additionally, in some implementations, the number of such fine quantizer intervals may be greater than 3. Regardless of the exact boundaries between the fine quantizer intervals in each coarse quantizer increment, there will be one or more center intervals that define the expected values of the fine quantizer levels.

For three histograms of fine quantizer counts, fig. 7 shows some representative fine quantizer intervals for coarse quantizer increments. In each histogram, the starting and final intervals of coarse quantizer increments are designated as undesired regions, while the center interval of the same coarse quantizer increment is designated as the desired region. Each histogram is obtained from a series of repeated clock measurements. In the first histogram 700, the fine quantizer counts all occur in the desired region. As shown in fig. 7, there may be no reason to tune the DTC 610 of fig. 6 that gives such histogram results, because the output of the TDC110 is avoiding discontinuities in its input-output relationship.

The histogram 705 for the fine quantizer counts results in all counts being in the initial undesired region. In response to such histogram results, the histogram-based fine quantizer level detector and DTC tuning logic 605 may adjust the first tuning code such that the DTC 610 adjusts the delay of the first clock edge sufficiently such that subsequent histogram measurements are made by the fine quantizer count performed in the desired region. This increase in time difference at the TDC input is suitable for converting the fine quantizer count from an initial non-desired range to a desired range. In contrast, histogram 710 causes the fine quantizer count to occur in the final undesired range,such that the histogram based fine quantizer level detector and DTC tuning logic 605 can adjust the first tuning code such that the DTC 610 achieves a reduction in time difference at the TDC input. This reduction moves the resulting fine quantizer count to the desired region. Referring again to FIG. 6, note that the histogram based fine quantizer level detector and DTC tuning logic 605 may also Tune the DTC 615 to pass the second tuning signal, Tune code₂The second clock edge (referred to as CK _ in2) is adaptively delayed. This additional tuning is optional.

Although the TDC 110 has been discussed herein with respect to clock measurement applications, it will be appreciated that the increased resolution and wide input range of the TDC 110 may be advantageously utilized in other circuits requiring such wide range and accurate time-digital measurements. For example, the digital phase locked loop 800 as shown in fig. 8 may include the TDC 110 to compare the output clock signal CKV with the reference clock signal FREF to provide a variable phase output that is a digital word representing the phase difference between corresponding edges of the output clock signal CKV and the reference clock signal. Accumulator 805 generates a reference phase in response to a Frequency Control Word (FCW) and a reference clock signal. The loop filter 810 filters a phase error corresponding to a difference between the reference phase and the variable phase to generate a digital control word that controls an oscillation frequency of a Digitally Controlled Oscillator (DCO)815, thereby controlling a frequency of the output clock signal CKV. Because the jitter is typically much smaller than the coarse quantizer increment, DTC adjustment to the TDC 110 in the digital PLL 800 works well. The occasional output of the TDC 110 that is affected by the systematic error is filtered out by the loop filter 800. As a result of the final adjustment of the relative phase between the reference clock signal and the DCO clock signal (not shown), once lock is achieved, the loop feedback in the digital PLL 800 compensates for the phase detection offset due to the DTC adjustment discussed with respect to fig. 6 and 7. Since the digital PLL 800 does not need to rely on oversampling and noise shaping, its bandwidth is advantageously high, thereby facilitating filtering of DCO noise and facilitating fast setup and tracking.

It will be appreciated by those of ordinary skill in the art that various modifications and applications may be made to the staged TDC discussed herein. Thus, it should be appreciated that many modifications, substitutions, and variations may be made in the materials, apparatus, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the disclosure. In view of this, because the particular implementations illustrated and described herein are by way of example only, the scope of the present disclosure should not be limited by their scope, but rather should be fully commensurate with the scope of the appended claims and their functional equivalents.