阅读说明：本技术 非易失性存储器设备及其操作方法 (Nonvolatile memory device and method of operating the same ) 是由 尹在鹤 任载禹 朱相炫 于 2021-04-02 设计创作，主要内容包括：提供了一种非易失性存储器设备和操作方法。非易失性存储器设备包括：存储器单元阵列,包括多个平面,每个平面包括多个存储器块；地址解码器,连接到存储器单元阵列；电压生成器,被配置为向地址解码器施加操作电压；页缓冲器电路,包括与每个平面相对应的页缓冲器；数据输入/输出电路,连接到被配置为输入和输出数据的页缓冲器电路；以及控制单元,被配置为控制地址解码器、电压生成器、页缓冲器电路和数据输入/输出电路的操作,其中,控制单元被配置为通过检查访问地址的存储器块是否是坏块来在多操作或单一操作中操作。(A non-volatile memory device and an operating method are provided. The nonvolatile memory device includes: a memory cell array including a plurality of planes, each plane including a plurality of memory blocks; an address decoder connected to the memory cell array; a voltage generator configured to apply an operating voltage to the address decoder; a page buffer circuit including a page buffer corresponding to each plane; a data input/output circuit connected to the page buffer circuit configured to input and output data; and a control unit configured to control operations of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.)

1. A non-volatile memory device, comprising:

a memory cell array including a plurality of planes, each plane including a plurality of memory blocks;

an address decoder connected to the memory cell array;

a voltage generator configured to apply an operating voltage to the address decoder;

a page buffer circuit including a page buffer corresponding to each of the planes;

a data input/output circuit connected to the page buffer circuit configured to input and output data; and

a control unit configured to control operations of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit,

wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.

2. The non-volatile memory device of claim 1, wherein the control unit comprises a bad block register configured to store at least one bad block information, and

when receiving the access address from a memory controller, the control unit is configured to compare the access address with the stored bad block information.

3. The non-volatile memory device of claim 2, wherein when a bad block is included as a result of the comparison, the control unit is configured to perform a memory operation on the memory block of the access address in a single operation.

4. The non-volatile memory device of claim 2, wherein the control unit comprises

An address comparator configured to compare the access address with the stored bad block information to output a comparison result; and

a control signal generator configured to generate at least one control signal for the voltage generator, the address decoder, the page buffer circuit, or the data input/output circuit based on a command received from the memory controller and the comparison result.

5. The non-volatile memory device of claim 4, wherein the control signal is applied to the voltage generator to adjust a level of the operating voltage depending on the single operation or the multiple operations.

6. The nonvolatile memory device according to claim 4, wherein the control signal is applied to the page buffer circuit to adjust an enable timing of each of the page buffers.

7. The non-volatile memory device of claim 1, wherein the multi-operation is a memory operation performed at an operating voltage level that is higher than an operating voltage level of the single operation by an amount of the plane.

8. A method of operating a non-volatile memory device comprising an array of memory cells in a multi-plane structure, each plane comprising a plurality of memory blocks, the method comprising:

receiving a command, an access address, and data from a memory controller;

checking whether a bad block is included in the memory block corresponding to the access address;

when there is no bad block in the memory blocks, operating in a multi-operation that performs memory operations on at least two or more memory blocks at the same time; and

when the bad block is included in the memory blocks, operating in a single operation that performs the memory operation on each memory block.

9. The method of operating a non-volatile memory device of claim 8, wherein, in the single operation,

any one of the page buffers connected to the corresponding planes is sequentially enabled,

accessing the memory blocks in word line order to perform the memory operation while the one page buffer is enabled, an

When the memory operation on the enabled page buffer is complete, only a next page buffer is accessed to perform the memory operation on a memory block connected to the next page buffer.

10. The method of operating a non-volatile memory device of claim 8, wherein, in a single operation,

enabling only one of the plurality of word lines,

sequentially opening page buffers of the memory blocks connected to the enabled first word line to perform the memory operation on the memory blocks, an

When the memory operation on the first word line is completed, a next second word line is enabled, and the page buffers are sequentially opened for memory blocks connected to the second word line to perform memory operations on the memory blocks.

11. The method of operating a non-volatile memory device of claim 8, wherein the checking comprises

Comparing whether the access address is the same as the address of the bad block; and

adjusting a level of an operating voltage to be applied to a word line of the memory cell array based on the command and the comparison result.

12. The method of operating a non-volatile memory device of claim 11, wherein the multi-operation is a memory operation performed at an operating voltage level that is higher than an operating voltage level of the single operation by an amount of the plane.

13. A storage device, comprising:

a memory controller configured to receive instructions from a host and output commands, access addresses, and data; and

a non-volatile memory device configured to perform a memory operation based on a command in a memory block corresponding to the access address,

wherein the non-volatile memory device comprises

An array of memory cells comprising a plurality of planes, each plane comprising a plurality of memory blocks,

an address decoder connected to a word line of the memory cell array according to a first control signal and configured to enable a word line address corresponding to the access address,

a voltage generator configured to adjust an operating voltage level according to a second control signal and apply an operating voltage to the address decoder, an

A page buffer circuit including a plurality of page buffers connected to each of the plurality of planes and configured to write the data or read the stored data in the memory block, an

A control unit configured to receive the access address and the command and generate the first control signal and the second control signal,

the control unit is configured to adjust the first control signal to lower the operating voltage level in a case where at least one bad block exists in a memory block corresponding to the access address, and to raise the operating voltage level in a case where the bad block does not exist.

14. The storage device of claim 13, wherein the control unit comprises

A bad block register configured to store an address of the at least one bad block;

an address comparator configured to compare the access address with an address of the at least one bad block;

a command analyzer configured to analyze the command; and

a control signal generator configured to generate the first control signal and the second control signal based on the comparison result from the address comparator and the analyzed command.

15. The memory device of claim 14, wherein the control signal generator generates a third control signal that enables each of the plurality of page buffers based on the comparison result and the analyzed command.

16. The memory device of claim 15, wherein the control unit is configured to sequentially enable the first page buffer according to the third control signal and to sequentially access the memory block to perform memory operations with the word lines enabled according to the first control signal during enabling of the first page buffer, and

when the memory operation is completed, the control unit is configured to enable a next second page buffer according to the third control signal, and is configured to access a memory block connected to the second page buffer to perform the memory operation according to the first control signal.

17. The memory device of claim 15, wherein, when the first control signal is enabled for a first word line, the plurality of page buffers are configured to be sequentially enabled according to the third control signal, and the control unit is configured to access a memory block connected to the enabled page buffers to perform the memory operation, an

When the memory operation is completed, the plurality of page buffers are configured to be sequentially enabled according to the third control signal when the first control signal is enabled for a next second word line, and the control unit is configured to access a memory block connected to the enabled page buffers to perform the memory operation.

18. The memory device of claim 13, wherein, when there is at least one bad block among the memory blocks corresponding to the access address, the control unit is configured to perform the memory operation on each individual memory block, and

when there are no bad blocks, the control unit is configured to perform the memory operation on at least two memory blocks simultaneously.

19. The memory device of claim 18, wherein a first operating voltage level of the memory operations performed on each single memory block is lower than a second operating voltage level of the memory operations performed on the at least two memory blocks simultaneously.

20. The memory device of claim 19, wherein the second operating voltage level is higher than the first operating voltage level to correspond to a number of the memory blocks on which the memory operations are performed simultaneously.

Technical Field

The present inventive concept relates to semiconductor memories, and more particularly, to a nonvolatile memory device and an operating method thereof.

Background

A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can be broadly divided into volatile memory devices and nonvolatile memory devices.

Volatile memory devices are memory devices in which stored data dissipates when power is cut off. Volatile memory devices may include SRAM (static RAM), DRAM (dynamic RAM), SDRAM (synchronous DRAM), and the like. A nonvolatile memory device is a memory device that retains stored data even when power is cut off. The nonvolatile memory device may include a flash memory device, a ROM (read only memory), a PROM (programmable ROM), an EPROM (electrically programmable ROM), an EEPROM (electrically erasable and programmable ROM), a resistive memory device (e.g., PRAM (phase change RAM), FRAM (ferroelectric RAM), and RRAM (resistive RAM)), and the like.

As semiconductor technology develops, a flash memory based memory device is under development. In a single plane structure semiconductor memory, a memory operation is performed only on one block at a time. On the other hand, in the multi-plane structure semiconductor memory, since memory operations can be simultaneously performed on blocks (adjacent blocks) successively arranged in adjacent planes, performance is improved. Accordingly, the multi-plane structure may be used to improve the performance of the semiconductor memory device.

Disclosure of Invention

Aspects of the present inventive concept provide a nonvolatile memory device configured to perform an operation suitable for the number of planes of an actual operation when a bad block is included.

Aspects of the present inventive concept also provide a method of operating a nonvolatile memory device that performs an operation appropriate to the number of actual operation planes when including a bad block.

An aspect of the inventive concept provides a nonvolatile memory device including a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including a page buffer corresponding to each plane, a data input/output circuit connected to the page buffer circuit configured to input and output data, and a control unit configured to control operations of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.

Another aspect of the inventive concept provides a method of operating a nonvolatile memory device including a memory cell array of a multi-plane structure, each plane structure including a plurality of memory blocks, the method including receiving a command, an access address, and data from a memory controller, checking whether a bad block is included in the memory blocks corresponding to the access address, operating in a multi-operation of simultaneously performing a memory operation on at least two or more memory blocks when the bad block is not present in the memory blocks, and operating in a single operation of performing the memory operation on each memory block when the bad block is included in the memory blocks.

Another aspect of the inventive concept provides a memory device including a memory controller configured to receive an instruction from a host and output a command, an access address, and data, and a nonvolatile memory device configured to perform a memory operation based on the command in a memory block corresponding to the access address, wherein the nonvolatile memory device includes: a memory cell array including a plurality of planes, each plane including a plurality of memory blocks; an address decoder connected to a word line of the memory cell array according to a first control signal and configured to enable a word line address corresponding to an access address; a voltage generator configured to adjust an operating voltage level according to a second control signal and apply the operating voltage to the address decoder; a page buffer circuit including a plurality of page buffers connected to each of the plurality of planes and configured to write data to a memory block or read stored data; and a control unit configured to receive an access address and a command and generate first and second control signals, the control unit adjusting the first control signal to lower an operating voltage level in case that at least one bad block exists in a memory block corresponding to the access address, and to raise the operating voltage level in case that there is no bad block.

However, aspects of the present inventive concept are not limited to the aspects set forth herein. The foregoing and other aspects of the present inventive concept will become more apparent to those skilled in the art to which the present inventive concept pertains by referencing the detailed description of the present inventive concept given below.

Drawings

FIG. 1 is a schematic block diagram illustrating a non-volatile memory system in accordance with some example embodiments;

FIG. 2 is a block diagram illustrating the non-volatile memory device shown in FIG. 1, in accordance with some example embodiments;

FIG. 3 is an equivalent circuit diagram illustrating the memory cell array of FIG. 2, in accordance with some example embodiments;

FIG. 4 is a perspective view showing one block of the memory cell array of FIG. 2, according to some example embodiments;

fig. 5 is a block diagram illustrating a configuration of the control unit shown in fig. 2 according to some example embodiments;

FIG. 6 is a block diagram illustrating the storage controller shown in FIG. 1, according to some example embodiments;

fig. 7A through 10 are conceptual diagrams illustrating operational actions in a single-plane structure and a multi-plane structure of a memory cell array according to some example embodiments;

FIG. 11 is a flow chart illustrating a method of operating a non-volatile memory device according to some example embodiments; and

FIG. 12 is a block diagram illustrating an electronic device including a non-volatile memory system, according to some example embodiments.

Detailed Description

FIG. 1 is a schematic block diagram illustrating a non-volatile memory system in accordance with some example embodiments.

Referring to fig. 1, a nonvolatile memory system may include a host 1 and/or a storage device 2. The storage device 2 may include a storage controller 10 and/or at least one non-volatile memory device 100. The host 1 generally controls the operation of the storage device 2. The memory controller 10 may exchange signals such as a command CMD, an address ADDR, DATA, and/or a control signal CTRL with the nonvolatile memory device 100.

The memory controller 10 may program or erase data in the nonvolatile memory device 100, or may read data from the nonvolatile memory device 100 according to a command of the host 1.

Non-volatile memory device 100 may include multiple planes PL0 through PLN-1.

Each of the plurality of planes includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of strings. Each of the plurality of strings includes a plurality of memory cells. Each of the plurality of memory cells is connected to a plurality of word lines. Each of the plurality of memory cells may be provided as a Single Level Cell (SLC) storing 1-bit data or a multi-level cell (MLC) storing at least 2-bit data. The plurality of planes, the plurality of memory blocks, and the plurality of strings will be explained in more detail with reference to fig. 2 to 4.

Fig. 2 is a block diagram illustrating the nonvolatile memory device shown in fig. 1 according to some example embodiments, and fig. 3 is an equivalent circuit diagram illustrating the memory cell array of fig. 2 according to some example embodiments. Fig. 4 is a perspective view illustrating one block of the memory cell array of fig. 2 according to some example embodiments.

Referring to fig. 2, the nonvolatile memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, a page buffer circuit 140, a data input/output circuit 150, and/or a control unit 200.

The memory cell array 110 may include a plurality of memory cells connected to a plurality of word lines WL and a plurality of bit lines BL. In some example embodiments, the memory cell array 110 may include memory cells connected to each word line stacked on the substrate.

The memory cell array 110 may be connected to the address decoder 130 through a string selection line SSL, a plurality of word lines WL, and/or a ground selection line GSL. In addition, the memory cell array 110 may be connected to the page buffer circuit 140 through a plurality of bit lines BL.

The memory cell array 110 includes a plurality of memory blocks (BLK1 to BLKz, z being a natural number of 3 or more). In some example embodiments, memory blocks BLK1 through BLKz are selected by address decoder 130. For example, the address decoder 130 may select a memory block BLK corresponding to the block address among the memory blocks BLK1 through BLKz. The address decoder 130 may select at least one row in the memory block BLK in response to the row address R _ ADDR.

Referring to fig. 3, cell strings CS11 to CS33 are connected between bit lines BL1 to BL3 and a common source line CSL. Each cell string (e.g., CS11) includes a string selection transistor SST, a plurality of memory cells MC1 through MC8, and/or a ground selection transistor GST.

The string selection transistor SST is connected to string selection lines SSL1 to SSL 3. Each of the plurality of memory cells MC1 through MC8 is connected to a corresponding word line WL1 through WL 8. The ground selection transistor GST is connected to a ground selection line GSL. The string selection transistor SST is connected to the bit line BL, and the ground selection transistor GST is connected to the common source line CSL.

Word lines of the same height (e.g., WL1) are typically connected, and string select lines SSL 1-SSL 3 are separated. When programming memory cells (hereinafter, referred to as pages) connected to the first word line WL1 and belonging to the cell strings CS11, CS12, and CS13, the first word line WL1 and the first select line SSL1 are selected.

As an example, one memory block BLK11 of the plurality of memory blocks BLK11 through BLK1n and BLK21 through BLK2n is shown in fig. 4. However, the scope of the inventive concept is not so limited.

Referring to fig. 4, the memory block BLK11 includes a gate layer, an insulating layer, a vertical active pattern, and/or an information storage layer. The memory block BLK1 is formed in a direction perpendicular to the substrate SUB. An n + doped region is formed on the substrate SUB. Gate layers and insulating layers are alternately stacked on the substrate SUB. In addition, a charge storage layer may be formed between the gate electrode layer and the insulating layer.

Vertical patterning of the gate layer and the insulating layer forms a V-shaped pillar. The pillar penetrates the gate layer and the insulating layer and is connected to the substrate SUB. The pillar may be formed externally of the channel semiconductor and internally of an insulating material such as silicon oxide.

Referring to fig. 4, a gate layer of the memory block BLK11 may be connected to a ground selection line GSL, a plurality of word lines WL1 to WL8, and a string selection line SSL. In addition, pillars of the memory block BLK11 may form a plurality of bit lines BL1 to BL 3. Although fig. 4 shows one memory block BLK1 having two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, the number thereof may be greater or less than these numbers in practice.

Referring again to fig. 2, the control unit 200 may receive a command CMD and an address ADDR from the memory controller 10, and may control an erase action, a program action, and a read action of the nonvolatile memory device 100 based on the command CMD and the address ADDR.

For example, the control unit 200 may generate a control signal CTL for controlling the voltage generator 120 based on the command CMD, and may generate a row address R _ ADDR and a column address C _ ADDR based on the address signal ADDR. The control unit 200 may provide a row address R _ ADDR to the address decoder 130 and may provide a column address C _ ADDR to the data input/output circuit 150.

The address decoder 130 may be connected to the memory cell array 110 through a string selection line SSL, a plurality of word lines WL, and/or a ground selection line GSL. The voltage generator 120 may generate a word line voltage VWL required for the operation of the nonvolatile memory device 100 based on a control signal CTL provided from the control unit 200. The word line voltage VWL generated from the voltage generator 120 may be applied to the plurality of word lines WL through the address decoder 130.

According to some example embodiments, the voltage generator 120 may apply a program voltage to a selected word line at the time of a program action, and may apply a program pass voltage to non-selected word lines. According to some example embodiments, the voltage generator 120 may apply a program verify voltage to a selected word line at the time of a program verify action, and may apply a verify pass voltage to non-selected word lines. According to some example embodiments, the voltage generator 120 may apply a read voltage to a selected word line at the time of a read action, and may apply a read pass voltage to non-selected word lines. According to some example embodiments, the voltage generator 120 may apply an erase voltage to a well or a substrate of a memory block and apply a word line erase voltage, i.e., a ground voltage, to a word line of a selected memory block in an erase action. According to some example embodiments, the voltage generator 120 may apply the erase verify voltage to the word lines of the selected block at the time of the erase verify action, or may apply the erase verify voltage in units of word lines.

The page buffer circuit 140 may be connected to the memory cell array 110 through a plurality of bit lines BL. The page buffer circuit 140 may include a plurality of page buffers. According to some example embodiments, the number of page buffers may correspond to the number of planes. The page buffer circuit 140 may temporarily store data to be programmed in a selected page at the time of a programming action, and may temporarily store data to be read from the selected page at the time of a reading action.

The data input/output circuit 150 may be connected to the page buffer circuit 140 through the data line DL. At the time of a program action, the DATA input/output circuit 150 may receive program DATA from the memory controller 10, and may supply the program DATA to the page buffer circuit 140 based on a column address C _ ADDR supplied from the control unit 200. In a read action, the DATA input/output circuit 150 may store the read DATA stored in the page buffer circuit 140 to the memory controller 10 based on the column address C _ ADDR supplied from the control unit 200.

Fig. 5 is a block diagram illustrating a configuration of the control unit illustrated in fig. 2 according to some example embodiments.

In fig. 5, the control unit 200 may include an address comparator 210, an address generator 220, a command analyzer 230, a bad block register 240, and/or a control signal generator 250, according to some example embodiments.

The address generator 220 receives an address ADDR to be accessed from the memory controller 10, generates a row address R _ ADD and a column address C _ ADD of the address ADDR, and transmits them to the corresponding circuits 130, 140, and 150. The row address R _ ADD is transmitted to the address decoder 130, and the column address C _ ADD is transmitted to the page buffer 140 and the data input/output circuit 150.

The command analyzer 230 analyzes the command CMD received from the memory controller 10 and transmits the analyzed command to the control signal generator 250.

Bad block register 240 may store the address of the bad block. The bad block register 240 may include not only the initial bad block address but also a runtime bad block address generated by using the nonvolatile memory device 100. The initial bad block is referred to as a designated bad block before the nonvolatile memory device 10 is used for the first time (i.e., from the time of product shipment).

The address comparator 210 may compare the address of the memory block generated by the address generator 220 with the bad block address stored in the bad block register 240.

When the address of the memory block to be accessed is equal to one of the bad block addresses stored in the bad block register 240, the address comparator 210 transmits a first comparison result signal to the control signal generator 250 so that the nonvolatile memory device 100 operates in a single operation.

If the address of the memory block to be accessed does not correspond to all the bad block addresses stored in the bad block register 240, the address comparator 210 transmits a second comparison result signal to the control signal generator 250 so that the nonvolatile memory device 100 operates in a multi-operation.

The control signal generator 250 may generate control signals Ctrl1 or Ctrl4 for controlling each of the configurations 120, 130, 140, and 150 of the non-volatile memory device 100 according to the analyzed command and the comparison result signal.

According to some example embodiments, the control signal generator 250 transmits the control signal Ctrl1 to the voltage generator 120 so that operation voltages (Verase, Vgpm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl) for performing a program loop, a read action, or an erase loop according to the analyzed command and comparison result signals, or global lines (GSSL, GWL0 to GWLn, and GDSL) may be generated at an appropriate level. Further, the control signal generator 250 outputs a control signal Ctrl3 for controlling the page buffer 140 to perform a program cycle, a read cycle, or an erase cycle. The program loop includes a program action and a program verify action, and the program loop may be performed in an ISPP (incremental step pulse programming) manner. The erase cycle includes an erase action and an erase verification action, and may be performed in an ISPE (incremental step pulse erase) manner.

According to some example embodiments, when the memory block to be accessed corresponds to a bad block, the control signal generator 250 may send the control signal Ctrl1 to be sent to the voltage generator 120 by setting the control signal Ctrl1 in a single operation mode according to the first comparison result signal. According to some example embodiments, when the memory block to be accessed does not correspond to a bad block, the control signal generator 250 transmits the control signal Ctrl1 to be transmitted to the voltage generator 120 by setting the control signal Ctrl1 in the multi-operation mode according to the second comparison result signal.

The single operation and the multiple operation will be described below with reference to fig. 7(a) to 10.

According to some example embodiments, the control signal generator 250 may send control signals Ctrl 2, Ctrl3, and Ctrl4 to each of the configurations 130, 140, and 150 to adjust the timing of the voltage to be applied to each word line, the global line, or the column line differently according to the analyzed command and the comparison result signal.

FIG. 6 is a block diagram illustrating the memory controller shown in FIG. 1, according to some example embodiments.

Referring to fig. 6, a storage controller 10 according to some example embodiments may include a host interface 20, an internal memory 30, a processor 40, and/or a non-volatile memory interface 50.

The storage controller 10 may communicate with the host 1 through a host interface 20. For example, the host interface 20 may be provided as at least one of various interfaces such as USB (universal serial bus), MMC (multimedia card), PCI (peripheral component interconnect), PCI-E (PCI-express), ATA (advanced technology attachment), serial ATA, parallel ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (integrated drive electronics), MIPI (mobile industry processor interface), NVMe (non-volatile memory-express), and UFS (universal flash memory interface).

The internal memory 30 is a non-volatile memory according to some example embodiments, which may store various types of information required for operating the memory controller 10 in the form of firmware. Alternatively, the internal memory 30 is an operation memory according to some example embodiments, and may be a buffer that temporarily stores intermediate data generated during communication between the host 1 and the nonvolatile memory device 100.

According to some example embodiments, the internal memory 30 may include a cache, a ROM (read only memory), a PROM (programmable read only memory), an EPROM (erasable PROM), an EEPROM (electrically erasable programmable read only memory), a PRAM (phase change RAM), a flash memory, an SRAM (static RAM), or a DRAM (dynamic RAM).

The processor 40 may control the overall actions of the other constituent elements 10, 20, 30 and 50 in the memory controller 10 according to the DATA and commands received by the host 1.

The memory controller 10 may communicate with the nonvolatile memory device 100 through the nonvolatile memory interface 50.

Fig. 7(a) to 10 are conceptual diagrams illustrating operation actions in a single-plane structure and a multi-plane structure of a memory cell array according to some example embodiments.

Referring to fig. 7(a), the flash memory is composed of a single plane PLN 0. The plane PLN0 includes a plurality of blocks BLK0 through BLKn-1. Such a structure is referred to as a monoplanar structure. In a single plane architecture, memory operations are performed on only one block at a time. In this specification, performing an operation on one block at a time is referred to as a single operation. In this specification, a flash operation includes program, read, and erase actions, and the like, and is referred to as a memory operation or a memory action. As shown, when there are operation requests for the blocks BLK0 and BLK1 from the storage controller 10, the single flash operation OP2 for the block BLK1 is performed after the single flash operation OP1 for the block BLK0 is completed. Finally, two single flash operations OP1 and OP2 are performed on the two blocks BLK0 and BLK 1.

The flash memory of fig. 7(b) is composed of two planes PLN0 and PLN 1. Each plane includes a plurality of blocks BLK0 through BLKn-1. Such a structure is called a multiplanar structure. Although two planes PLN0 and PLN1 are shown as examples in the present embodiment, the scope of the inventive concept is not limited thereto. For example, the number of planes may be more than two.

In the multi-plane structure semiconductor memory, blocks BLK are distributed and placed on one or more planes, and simultaneous operations may be performed on blocks successively placed on adjacent planes. In other words, in a multi-plane architecture, flash operations may be performed on multiple blocks at a time. Performing operations on multiple blocks at a time will be referred to herein as a multi-operation.

As shown, when there are operation requests from the memory controller 10 to the blocks BLK0 and BLK1, one multi-operation OP1 is performed to the blocks BLK0 and BLK 1. That is, one flash operation OP1 is performed on the two blocks BLK0 and BLK 1.

According to some example embodiments, programming may be simultaneously performed on N pages adjacent to each other in a device equipped with N memory planes (N is a natural number greater than or equal to 2). For example, first, data is loaded into page buffers, each of which is connected to N pages. After all N page buffers are filled, the N pages are programmed simultaneously. Similarly, N pages can be read or erased at the same time. Therefore, the time taken is reduced as compared with the case where the flash operation is performed separately for each page.

In a single operation, the flash operation is performed on only one block at a time. On the other hand, in the multi-operation, since the flash operation can be simultaneously performed on the adjacent blocks arranged consecutively in the adjacent planes, the performance is improved.

Referring to fig. 8 to 10, at least one bad block may be included in a single plane. The bad block may be an initial bad block existing from the time of shipment of the nonvolatile memory device 100, or may be a runtime bad block generated from the use of the nonvolatile memory device 100. In the following, in some example embodiments, it will be assumed that blocks BLK2 and BLK7 are bad blocks.

In fig. 8, if the memory cell array 110 having the multi-plane structure is always operated in the multi-operation, the flash operation OP1 may simultaneously perform the flash operation on BLK0 of the plane PLN0 and BLK1 of the plane PLN 1. At this time, since there is no bad block, the operation can be normally performed.

Flash operation OP2 may perform flash operations on BLK2 of planar PLN0 and BLK3 of planar PLN1 simultaneously. At this time, if the block BLK2 is a bad block, the word line is loaded only into the block BLK 3. Incidentally, in the case of a multi-operation, since a flash operation is simultaneously performed on a plurality of blocks, a larger load is applied as compared with a single operation.

That is, the voltage generator 120 generates a current in the multi-operation action larger than that in the single operation action to perform the program action, the erase action, or the read action. For example, the DC levels of the operating voltages (Verase, Vgpm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl) are the same for the case of the multi-operation and the single operation, but the amount of current to be supplied may be larger for the case of the multi-operation.

Incidentally, when the multiple operation current is concentrated only on the remaining block (block BLK3 in the illustrated example) due to the bad block BLK2, the applied operation voltage has a relatively steep slope compared to the action in the normal block, which may cause an increase in the high-voltage application time. If the high voltage application time is increased, the actual threshold voltage may be higher than the predetermined or alternatively desired threshold voltage, and thus the threshold voltage variation programmed in block BLK3 may be worse or fail than the threshold voltage variation due to normal flash operation.

In order to improve reliability of a multi-plane structured nonvolatile memory cell array including a bad block, the nonvolatile memory device 100 according to some example embodiments may perform a single operation if at least one bad block is included in a plane of an address ADDR to be accessed.

Referring again to fig. 2 to 5, the memory controller 10 transmits an address ADDR to be accessed, and the control unit 200 may compare the address ADDR to be accessed with the information of the bad block stored in the bad block register 240. The control unit 200 reflects the comparison result in the command received from the memory controller 10, determines whether to operate in a single operation or a multi-operation, and outputs control signals Ctrl1 to Ctrl 4.

In fig. 9 to 10, when the memory cell array 110 includes the bad blocks BLK2 and BLK7, the nonvolatile memory device 100 may perform a single operation according to some example embodiments. For convenience of explanation, although it is assumed that the memory cell array includes two planes and each plane includes five blocks, the number of planes and the number of memory blocks belonging to each plane may vary according to some example embodiments.

According to some example embodiments, as shown in fig. 9, the nonvolatile memory device 100 may enable only the page buffer to be accessed, and may access a word line sequential memory block of each enabled plane. That is, the nonvolatile memory device 100 sequentially enables one page buffer of the plurality of page buffers. When the first page buffer is enabled, the nonvolatile memory device 100 accesses the slave memory blocks in word line order to perform the flash memory operation. When the flash operation of the enabled first page buffer is completed, a next second page buffer may be enabled to perform the flash operation on the memory block connected to the second page buffer. In the case shown in fig. 9, BLK0, BLK2, BLK4, BLK6, and BLK8 may be accessed in word line order in plane PLN0 to perform flash operations OP1 to OP5, and BLK1, BLK3, BLK5, BLK7, and BLK9 may be accessed in word line order in plane PLN1 to perform flash operations OP6 to OP 10.

Alternatively, according to some example embodiments as shown in fig. 10, the nonvolatile memory device 100 may sequentially open page buffers in the same word line to access each plane in the same word line. In the case shown in fig. 10, blocks BLK0 and BLK1 of planes PLN0 and PLN1 in the first word line may be accessed to perform flash operations OP1 and OP 2. Blocks BLK2 and BLK3 of planes PLN0 and PLN1 in the second word line may be accessed to perform flash operations OP3 and OP 4. Blocks BLK4 and BLK5 of planes PLN0 and PLN1 in the third word line may be accessed to perform flash operations OP5 and OP 6. Blocks BLK6 and BLK7 of planes PLN0 and PLN1 in the fourth word line may be accessed to perform flash operations OP7 and OP 8. Blocks BLK8 and BLK9 of planes PLN0 and PLN1 in the fifth word line may be sequentially accessed to perform flash operations OP9 and OP 10.

If the nonvolatile memory device 100 according to some example embodiments operates in a single operation or multiple operations depending on whether a bad block is included, the threshold voltage variation may be equivalent to a single operation level and the operation reliability of the memory cell may be improved.

FIG. 11 is a flow chart illustrating a method of operating a non-volatile memory device, according to some example embodiments.

When the nonvolatile memory device according to some example embodiments receives a command and an address from a memory controller (S10), the nonvolatile memory device determines whether to perform a single operation (x1) or a multiple operation (xN) depending on the structure of a memory cell array in order to execute the command (S20). If the memory cell array includes multi-planes and there is no bad block, a multi-operation is determined (S50). However, if the address to be accessed is checked and a bad block is included (S30), it may be determined that the operation is performed in a single operation (S40).

The nonvolatile memory device generates a control signal according to the determined operation and performs a flash operation on a memory block corresponding to the received address (S60). For example, in the case of a single-plane memory cell array, a flash operation is performed in a single operation. In the case of a multi-plane memory cell array, if there is no bad block, a flash operation is performed in a multi-operation, and if there is a bad block, a flash operation is performed in a single operation.

FIG. 12 is a block diagram illustrating an electronic device including a non-volatile memory system, according to some example embodiments.

Referring to fig. 12, the electronic device 1000 includes an application processor 1100, a memory module 1200, a network module 1300, a storage module 1400, and a user interface 1500. For example, the electronic device 1000 may be provided as one of computing systems such as a UMPC (ultra mobile PC), a workstation, a netbook, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a PMP (portable multimedia player), a portable game machine, a navigation device, a black box, a digital camera, a DMB (digital multimedia broadcasting) player, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, and a digital video player.

The application processor 1100 may drive constituent elements included in the electronic device 1000, an OS (operating system), and the like. For example, the application processor 1100 may include a controller that controls constituent elements included in the electronic device 1000, a graphic engine, and various interfaces.

The memory module 1200 may operate as a main memory, an operation memory, a buffer memory, or a cache memory of the electronic device 1000. The memory module 1200 may include volatile random access memory (such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR DRAM, LPDDR2 DRAM, and LPDDR3 DRAM) or non-volatile random access memory (such as PRAM, ReRAM, MRAM, and FRAM).

The network module 1300 may communicate with external devices. For example, the network module 1300 may support wireless communication such as CDMA (code division multiple access), GSM (global system for mobile communications), WCDMA (wideband CDMA), CDMA-2000, TDMA (time division multiple access), LTE (long term evolution), Wimax, WLAN, UWB, bluetooth, and WI-DI.

The memory module 1400 may store data. For example, the storage module 1400 may store data received from the outside. Alternatively, the storage module 1400 may transmit data stored in the storage module 1400 to the application processor 1400. For example, the memory module 1400 may be implemented as a semiconductor memory element such as a PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), NAND flash, NOR flash, and NAND flash in a three-dimensional structure. For example, the memory module 1400 may include a plurality of non-volatile memory devices. The plurality of non-volatile memory devices may be the non-volatile memory devices described with reference to fig. 1 to 11. Alternatively, the memory module 1400 may include the memory controller described with reference to fig. 1 to 11. That is, the memory module 1400 may perform the programming, reading, and erasing actions based on the operation method described with reference to fig. 1 to 11. .

The user interface 1500 may include an interface to input data or commands to the user system 1100 or to output data to an external device. For example, user interface 1500 may include input devices such as cameras, touch screens, motion recognition modules, and microphones, or output devices such as displays, speakers, and touch screens.

Any of the elements disclosed above may be included or implemented in processing circuitry, such as hardware including logic circuitry; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth.

At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred exemplary embodiments without materially departing from the principles of the inventive concept. Accordingly, the disclosed preferred exemplary embodiments of the inventive concepts are used in a generic and descriptive sense only and not for purposes of limitation.