阅读说明：本技术 一种最小化芯片布局面积的自适应选择方法 (Self-adaptive selection method for minimizing chip layout area ) 是由 刘强 李龙 魏丽军 陈新 严都喜 于 2020-08-05 设计创作，主要内容包括：本发明涉及一种最小化芯片布局面积的自适应选择方法,包括如下步骤：步骤一,计算输入矩形电路模块尺寸组合的宽度w<Sub>i</Sub>,形成宽度候选集W；步骤二,调用随机局部搜索算法计算每个宽度w<Sub>i</Sub>对应的初始高度H<Sub>i</Sub>,对W集中的宽度按填充率<Image he="89" wi="249" file="DDA0002618649240000011.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>的大小升序排序,其中totalArea表示所有矩形电路模块的面积；步骤三,W集中随机选择一个宽度且选择第k个宽度的概率为<Image he="95" wi="201" file="DDA0002618649240000012.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>其中|w|为候选宽度集W中候选宽度的个数；对宽度w<Sub>k</Sub>调用随机局部搜索算法计算最小高度H,若H小于宽度w<Sub>k</Sub>的初始高度H<Sub>k</Sub>,则将H<Sub>k</Sub>更新为H,将宽度w<Sub>k</Sub>的填充率fr<Sub>k</Sub>更新为<Image he="97" wi="172" file="DDA0002618649240000013.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>若H大于或等于宽度w<Sub>k</Sub>的初始高度H<Sub>k</Sub>,则更新W集使W集中的宽度按填充率的大小升序排列；步骤四,输出填充率最大的方案。该方法能有效提高材料的利用率。(The invention relates to a self-adaptive selection method for minimizing the layout area of a chip, which comprises the following steps: step one, calculating the width w of the input rectangular circuit module size combination i Forming a width candidate set W; step two, calling a random local search algorithm to calculate each width w i Corresponding initial height H i For width of W concentration according to filling ratio In ascending order of size, wherein totalArea represents the area of all rectangular circuit modules; step three, randomly selecting one width in the W set and selecting the k-th width with the probability of Wherein | W | is the number of candidate widths in the candidate width set W; for width w k A random local search algorithm is called to calculate the minimum height H, if H is less than the width w k Initial height H of k Then H will be k Update to H, update the width w k Filling ratio of fr k Is updated to If H is greater than or equal to the width w k Initial height H of k Updating the W set to enable the widths of the W set to be arranged in an ascending order according to the filling rate; and step four, outputting the scheme with the maximum filling rate. The method can effectively improve the utilization rate of the material.)

1. An adaptive selection method for minimizing chip layout area, comprising the steps of:

inputting the size of a rectangular circuit module;

step two, calculating the width of the input rectangular circuit module size combination to form a width candidate set W; calculating each width w by calling a random local search algorithm_iCorresponding initial height H_iFor width of W concentration according to filling ratioIn ascending order of size, wherein totalArea represents the area of all rectangular circuit modules;

step three, randomly selecting one width in the W set and selecting the k-th width with the probability ofWherein | W | is the number of candidate widths in the candidate width set W; for width w_kA random local search algorithm is called to calculate the minimum height H, if H is less than the width w_kInitial height H of_kThen H will be_kUpdate to H, update the width w_kFilling ratio of fr_kIs updated to

and step four, outputting the scheme with the maximum filling rate.

2. The adaptive selection method for minimizing chip layout area according to claim 1, wherein: the width w of the third middle pair of steps_kThe number of iterations originally set is doubled before the random local search algorithm is invoked.

3. The adaptive selection method for minimizing chip layout area according to claim 2, wherein: setting the maximum value of the iteration times in the third step as n, wherein n is the number of the rectangular circuit modules; and if the iteration times reach the maximum value or the iteration times are finished, performing the step four.

4. The adaptive selection method for minimizing chip layout area according to claim 1, wherein: in the first step, the width candidate set W discards the width not representing the input rectangular circuit module size combination, and only includes the width as the input rectangular circuit module size combination.

5. The adaptive selection method for minimizing chip layout area according to claim 1, wherein: setting the iteration times to be 1 in the step two, and calling a random local search algorithm to calculate each width w_iCorresponding initial height H_i。

6. The adaptive selection method for minimizing chip layout area according to claim 1, wherein: the random algorithm is a heuristic search algorithm based on skylines, and comprises the following steps:

a: giving a rectangular circuit module sequence R, the width W of a chip and the iteration number iter;

b: let srk be the sort rule set on width set W, the sort rule set includes four sort rules of descending sort according to area, descending sort according to height, descending sort according to width and random sort;

c: by probability

d: sequencing the sequence R according to the selected sequencing rule;

e: selecting a proper circuit module R from the sequence R to be placed at a candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each rectangular circuit module R is placed until all the rectangular circuit modules in the sequence R are placed, and returning to the original height h used in one skyline;

f: iteration is carried out until the iteration number iter is reached;

g: randomly exchanging two rectangular circuit modules to generate a sequence R1 from the sequence R;

h: selecting a proper circuit module R from the sequence R1 to be placed at the candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each placement of one rectangular circuit module R until all the rectangular circuit modules in the sequence R1 are placed, and returning to the used height h1 in one skyline;

i: h-h 1 if h1< h, R-R1;

j: and finally returning the found minimum height.

Technical Field

The invention relates to the technical field of chip layout, in particular to a self-adaptive selection method for minimizing the layout area of a chip.

Background

Minimizing the chip layout area problem is an important step in VLSI (large scale integration) chip design. In VLSI (large scale integration) chip design, n width and height of any given rectangular circuit modules are known, and how to determine a rectangular chip with variable size, so that all the rectangular circuit modules can be legally placed therein, and the rectangular chip is required to have as small an area as possible. Legal means that the chip does not exceed the boundary of the rectangular chip after being put into any rectangular circuit module, the edge of the circuit module is parallel to the edge of the rectangular chip, and every two circuit modules are not overlapped with each other. In the field of large-scale integrated chip design, it is usually necessary to place a set of rectangular modules on a rectangular chip, and these modules need to be connected by wires, with the goal to be considered to minimize the area of the rectangular chip and minimize the total length of the wires. The layout of each small rectangular circuit module in the large-scale integrated chip design can affect the performance of the integrated chip, and meanwhile, the area of the rectangular chip is not optimal due to improper layout of the small rectangular circuit modules, so that the waste of materials used for producing the rectangular chip is caused. On the other hand, the material for producing the chip is very expensive, so the material saving has important influence on reducing the manufacturing cost, and especially in mass production, the improvement of the utilization rate of the chip material can bring remarkable economic benefit.

Current solution to minimize chipThe layout area problem is commonly solved by converting the minimized chip layout area problem into a two-dimensional strip packing problem (2DSP) by fixing the width of a rectangular chip, and then converting the two-dimensional strip packing problem into a two-dimensional rectangular packing problem (2DRP) by fixing the height. Since each combination of input rectangular circuit block sizes may be a candidate width for 2 DSPs, there are typically too many possible candidate widths, resulting in too much time spent resolving 2 DSPs on each width; thus, a key component of this approach is how to select the most promising candidate widths; one of the most common methods of selecting candidate widths at present is to consider only a given range [ W ]_min，W_max]Inner width. W_minIs the maximum of the smaller dimensions of all rectangles, W_maxIs set to be alpha area (R)^1/2Where area (R) is the area of all rectangles in R and α is a parameter slightly larger than 1. From [ W ]_min，W_max]The desired width w is selected by its frequency f (w), which is defined as the number of combinations of dimensions of the width w, the combinations of dimensions of w being defined as the sum of the dimensions w of a set of rectangular dimensions. For n rectangles, there are

A different combination of sizes. For example, assuming there are 2 rectangles of sizes 1 × 2 and 3 × 4, respectively, there areThe size combinations are {1}, {2}, {3}, {4}, {1, 3}, {1, 4}, {2, 3} and {2, 4}, respectively. The sum of these 8 sets of dimensions is 1,2,3,4,4,5,5 and 6, respectively. Therefore, the frequencies of 1,2,3,4, 5, and 6 are 1,2, and 1, respectively, so that the sum of the sizes (4 and 5) where the frequencies are high is selected as the candidate width. The disadvantages of this method are: the frequency f (w) becomes an increasing function of the width w as the number of rectangles increases, resulting in a bias towards choosing a candidate width with a larger value of w, but the candidate width resulting in the optimal solution is not necessarily the larger value of width.

Disclosure of Invention

The invention aims to provide a simple and easy-to-implement adaptive selection method for minimizing the chip layout area aiming at the defects in the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

an adaptive selection method for minimizing chip layout area, comprising the steps of:

inputting the size of a rectangular circuit module;

step two, calculating the width of the input rectangular circuit module size combination to form a width candidate set W; calculating each width w by calling a random local search algorithm_iCorresponding initial height H_iFor width of W concentration according to filling ratio

In ascending order of size, wherein totalArea represents the area of all rectangular circuit modules;

step three, randomly selecting one width in the W set and selecting the k-th width with the probability of

Wherein | W | is the number of candidate widths in the candidate width set W; for width w_kA random local search algorithm is called to calculate the minimum height H, if H is less than the width w_kInitial height H of_kThen H will be_kUpdate to H, update the width w_kFilling ratio of fr_kIs updated toIf H is greater than or equal to the width w_kInitial height H of_kUpdating the W set to enable the widths of the W set to be arranged in an ascending order according to the filling rate;

and step four, outputting the scheme with the maximum filling rate.

In a further description, the width w in the third step_kThe number of iterations originally set is doubled before the random local search algorithm is invoked.

More specifically, the maximum value of the number of iterations in step three is set to n, where n is the number of rectangular circuit modules; and if the iteration times reach the maximum value or the iteration times are finished, performing the step four.

To be more specific, in the first step, the width candidate set W discards the width that does not represent the input rectangular circuit block size combination, and only includes the width that is used as the input rectangular circuit block size combination.

To be further explained, in the second step, the number of iterations is set to 1, and a random local search algorithm is called to calculate each width w_iCorresponding initial height H_i。

To be further described, the stochastic algorithm is a heuristic search algorithm based on skylines, which includes the following steps:

a: giving a rectangular circuit module sequence R, the width W of a chip and the iteration number iter;

b: let srk be the sort rule set on width set W, the sort rule set includes four sort rules of descending sort according to area, descending sort according to height, descending sort according to width and random sort;

c: randomly selecting the ith ordering rule according to the probability;

d: sequencing the sequence R according to the selected sequencing rule;

e: selecting a proper circuit module R from the sequence R to be placed at a candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each rectangular circuit module R is placed until all the rectangular circuit modules in the sequence R are placed, and returning to the original height h used in one skyline;

f: iteration is carried out until the iteration number iter is reached;

g: randomly exchanging two rectangular circuit modules to generate a sequence R1 from the sequence R;

h: selecting a proper circuit module R from the sequence R1 to be placed at the candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each placement of one rectangular circuit module R until all the rectangular circuit modules in the sequence R1 are placed, and returning to the used height h1 in one skyline;

i: h-h 1 if h1< h, R-R1;

j: and finally returning the found minimum height.

The invention has the beneficial effects that: the invention provides a self-adaptive selection method aiming at the problem of minimizing the chip layout area, which can reasonably arrange each rectangular circuit module in the large-scale integrated chip design to furthest improve the performance of the integrated chip, simultaneously minimize the area of the rectangular chip to furthest save the material for producing the rectangular chip and improve the utilization rate of the material, thereby bringing remarkable economic benefit to enterprises in mass production.

Drawings

The invention is further illustrated with reference to the following figures and examples.

FIG. 1 is a flow chart of one embodiment of the present invention.

Detailed Description

The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.

As shown in fig. 1, an adaptive selection method for minimizing chip layout area includes the following steps:

inputting the size of a rectangular circuit module;

step two, calculating the width of the input rectangular circuit module size combination to form a width candidate set W; calculating each width w by calling a random local search algorithm_iCorresponding initial height H_iFor width of W concentration according to filling ratioIn ascending order of size, wherein totalArea represents the area of all rectangular circuit modules;

step three, randomly selecting one width in the W set and selecting the k-th width with the probability ofWherein | W | is the number of candidate widths in the candidate width set W; for width w_kA random local search algorithm is called to calculate the minimum height H, if H is less than the widthDegree w_kInitial height H of_kThen H will be_kUpdate to H, update the width w_kFilling ratio of fr_kIs updated toIf H is greater than or equal to the width w_kInitial height H of_kUpdating the W set to enable the widths of the W set to be arranged in an ascending order according to the filling rate;

and step four, outputting the scheme with the maximum filling rate.

The invention discards the width which does not represent the size combination of the input rectangular circuit modules, and W is only contained as the width of the size combination of the input rectangular circuit modules. The probability of selecting the kth width is

The widths of the W sets are sorted according to the ascending order of the filling rate, so that the widths with higher filling rate can obtain higher probability, the performance of the integrated chip can be improved to the maximum extent by reasonably distributing each rectangular circuit module in the large-scale integrated chip design, meanwhile, the area of the rectangular chip is minimized, the material for producing the rectangular chip is saved to the maximum extent, the utilization rate of the material is improved, and therefore, the obvious economic benefit is brought to enterprises in mass production.

In a further description, the number of iterations originally set is doubled before the random local search algorithm is invoked for the width in step three.

The reason for doubling the number of iterations and then calling the random local search algorithm is to ensure that more effort is spent than before on the same width, thereby improving the calculation efficiency.

More specifically, the maximum value of the number of iterations in step three is set to n, where n is the number of rectangular circuit modules; and if the iteration times reach the maximum value or the iteration times are finished, performing the step four.

The maximum value of the number of iterations is set to n (the number of rectangular circuit blocks) in order to avoid multiple iterations occurring at one time of the invoked random local search algorithm.

To be more specific, in the first step, the width candidate set W discards the width that does not represent the input rectangular circuit block size combination, and only includes the width that is used as the input rectangular circuit block size combination.

Given n rectangle sizes, each candidate width w_iAt least the sum of n combinations of rectangular dimensions. For example: candidate widths are [2, 3,4, 5, 6, 7, 8, 9 ]]The input rectangle size is 3x4, 2x5, and the combination of sizes is {3}, {4}, {2}, {5}, {2, 3}, {2, 4}, {3, 5}, {4, 5} since the width that can represent the combination of rectangle sizes is only 2,3,4, 5, 6, 8, 9, 7 is left out since it does not represent the input rectangle size combination. This reduces the range of the width candidate set W and improves the calculation speed.

Further, in the second step, the number of iterations is set to 1, and a random local search algorithm is invoked to calculate an initial height corresponding to each width.

And (4) iterating for 1 time to calculate the initial height, and successively correcting through multiple iterations in subsequent steps, thereby finally finding the optimal layout scheme.

To be further described, the stochastic algorithm is a heuristic search algorithm based on skylines, which includes the following steps:

a: giving a rectangular circuit module sequence R, the width W of a chip and the iteration number iter;

b: let srk be the sort rule set on width set W, the sort rule set includes four sort rules of descending sort according to area, descending sort according to height, descending sort according to width and random sort;

c: by probabilityRandomly selecting an ith sorting rule;

d: sequencing the sequence R according to the selected sequencing rule;

e: selecting a proper circuit module R from the sequence R to be placed at a candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each rectangular circuit module R is placed until all the rectangular circuit modules in the sequence R are placed, and returning to the original height h used in one skyline;

f: iteration is carried out until the iteration number iter is reached;

g: randomly exchanging two rectangular circuit modules to generate a sequence R1 from the sequence R;

h: selecting a proper circuit module R from the sequence R1 to be placed at the candidate line segment s at the lower left corner of the skyline, updating the candidate line segment s of the skyline after each placement of one rectangular circuit module R until all the rectangular circuit modules in the sequence R1 are placed, and returning to the used height h1 in one skyline;

i: h-h 1 if h1< h, R-R1;

j: and finally returning the found minimum height.

The method has low complexity and quick convergence.

The above description is only a preferred embodiment of the present invention, and for those skilled in the art, the present invention should not be limited by the description of the present invention, which should be interpreted as a limitation.