阅读说明：本技术 可折叠显示面板 (Foldable display panel ) 是由 林明纬 黄宝玉 李文晖 于 2020-06-29 设计创作，主要内容包括：本发明公开了一种可折叠显示面板,包括基板及像素阵列。基板具有表面及位于表面上的显示区及周边区,周边区位于显示区的至少一侧,周边区具有至少一第一外接电路区及至少一第二外接电路区,第一及第二外接电路区分别位于周边区的相对的第一边及第二边,第一及第二外接电路区沿着第一方向间隔第一距离,且基板具有通过显示区的中心的可折叠线,可折叠线位于第一及第二外接电路区之间且平行于第一方向,第一边及第二边分别位于可折叠线的二侧。像素阵列位于显示区且重叠于可折叠线。像素阵列位于第一边及第二边之间且包括呈阵列排列的多个子像素单元。(The invention discloses a foldable display panel, which comprises a substrate and a pixel array. The substrate is provided with a surface, a display area and a peripheral area, the display area and the peripheral area are arranged on the surface, the peripheral area is arranged on at least one side of the display area, the peripheral area is provided with at least one first external circuit area and at least one second external circuit area, the first external circuit area and the second external circuit area are respectively arranged on a first side and a second side opposite to the peripheral area, the first external circuit area and the second external circuit area are separated by a first distance along a first direction, the substrate is provided with a folding line passing through the center of the display area, the folding line is arranged between the first external circuit area and the second external circuit area and is parallel to the first direction, and the first side and the second side are respectively arranged. The pixel array is located in the display area and overlaps the foldable line. The pixel array is located between the first edge and the second edge and comprises a plurality of sub-pixel units which are arranged in an array.)

1. A foldable display panel, comprising:

a substrate having a surface, a display area and a peripheral area on the surface, wherein the peripheral area is located on at least one side of the display area, the peripheral area has at least a first external circuit area and at least a second external circuit area, the first external circuit area and the second external circuit area are respectively located on a first side and a second side of the peripheral area, which are opposite to each other, the first external circuit area and the second external circuit area are spaced apart by a first distance along a first direction, the substrate has a foldable line passing through the center of the display area, the foldable line is located between the first external circuit area and the second external circuit area and parallel to the first direction, and the first side and the second side are respectively located on both sides of the foldable line; and

and the pixel array is positioned in the display area and overlapped with the foldable line, wherein the pixel array is positioned between the first edge and the second edge, the pixel array comprises a plurality of sub-pixel units, and the sub-pixel units are arranged in an array.

2. The foldable display panel of claim 1, further comprising:

a plurality of first pads disposed on the first external circuit region;

a plurality of first signal lines connected between the first pads and a part of the sub-pixel units;

a plurality of second pads disposed on the second external circuit region; and

and a plurality of second signal lines connected between the second pads and the other part of the sub-pixel units.

3. The foldable display panel of claim 1, wherein the peripheral region has a third edge and a fourth edge opposite to each other, the third edge and the fourth edge are located between the first edge and the second edge, and a sum of a shortest distance between the first external circuit region and the third edge and a length of the first external circuit region along the first direction is smaller than a shortest distance between the second external circuit region and the third edge.

4. The foldable display panel of claim 3, wherein the number of the first external circuit regions is plural, and the first external circuit regions are arranged at intervals along the first direction at a first pitch, and a sum of a shortest distance between the first external circuit regions and the third side, a length of the first external circuit region along the first direction and the first pitch is larger than a sum of a shortest distance between the second external circuit regions and the third side and a length of the second external circuit region along the first direction.

5. The foldable display panel of claim 3, wherein the first external circuit regions are plural in number and are arranged at intervals at a first pitch along the first direction, the second external circuit regions are plural in number and are arranged at intervals at a second pitch along the first direction, a sum of a shortest distance between the first external circuit regions and the third side, twice a length of the first external circuit regions along the first direction, and the first pitch is smaller than a sum of a shortest distance between the second external circuit regions and the third side, a length of the second external circuit regions along the first direction, and the second pitch.

6. The foldable display panel of claim 1, wherein a shortest distance between the second external circuit area and the third side is greater than a length of the first external circuit area along the first direction.

7. The foldable display panel of claim 3, wherein a shortest distance between the first external circuit area and the fourth side is greater than a sum of a shortest distance between the second external circuit area and the fourth side and a length of the second external circuit area along the first direction.

8. The foldable display panel of claim 3, further comprising:

at least one driving chip disposed on the first external circuit region and electrically connected to the first pads.

9. The foldable display panel of claim 8, further comprising:

and the anisotropic conductive adhesive is arranged on the first external circuit area and is positioned between the driving chip and the first connecting pads.

10. The foldable display panel of claim 1, further comprising:

a plurality of scanning lines configured in the display area; and

and a plurality of data lines arranged in the display area, wherein each sub-pixel unit is electrically connected with one of the scanning lines and one of the data lines, each sub-pixel unit comprises at least one thin film transistor and an organic light emitting diode, and the organic light emitting diode is electrically connected with the thin film transistor.

Technical Field

The invention relates to a foldable display panel.

Background

The development of displays has a tendency to have a large screen, but as the screen size becomes larger, the portability decreases. The foldable display can meet the two requirements, can provide a large screen when the full screen is unfolded, and can be conveniently carried by a user when the size of the foldable display is reduced. The peripheral region of the display panel is generally provided with a circuit for driving a pixel matrix located in the middle for displaying a picture. However, when the display panel is folded to be closed, the circuits on the opposite sides may collide with each other and be damaged. Therefore, a solution to the above-mentioned problems is needed.

Disclosure of Invention

The invention provides a foldable display panel, wherein a first external circuit area and a second external circuit area are separated by a first distance along a first direction, a substrate is provided with a foldable line passing through the center of the display area, the foldable display panel is folded along the foldable line, and the first external circuit area can be prevented from contacting the second external circuit area.

The foldable display panel comprises a substrate and a pixel array. The substrate is provided with a surface, a display area and a peripheral area, wherein the display area and the peripheral area are arranged on the surface, the peripheral area is arranged on at least one side of the display area, the peripheral area is provided with at least one first external circuit area and at least one second external circuit area, the first external circuit area and the second external circuit area are respectively arranged on a first side and a second side of the peripheral area, which are opposite, the first external circuit area and the second external circuit area are separated by a first distance along a first direction, the substrate is provided with a foldable line passing through the center of the display area, and the foldable line is arranged between the first external circuit area and the second external circuit area and is parallel to the first direction. The pixel array is located in the display area and overlapped with the foldable line, and the first edge and the second edge are respectively located at two sides of the foldable line. The pixel array is located between the first edge and the second edge, the pixel array comprises a plurality of sub-pixel units, and the sub-pixel units are arranged in an array.

In an embodiment of the invention, the foldable display panel further includes a plurality of first pads, a plurality of first signal lines, a plurality of second pads, and a plurality of second signal lines. The first connecting pad is arranged on the first external circuit area, and the first signal line is connected between the first connecting pad and a part of the sub-pixel units. The second connecting pad is arranged on the second external circuit area, and the second signal line is connected between the second connecting pad and the other part of the sub-pixel units.

In an embodiment of the invention, the peripheral region has a third edge and a fourth edge opposite to each other, the third edge and the fourth edge are located between the first edge and the second edge, and a sum of a shortest distance between the first external circuit region and the third edge and a length of the first external circuit region along the first direction is smaller than a shortest distance between the second external circuit region and the third edge.

In an embodiment of the invention, the number of the first external circuit regions is multiple, and the first external circuit regions are arranged at intervals along the first direction at a first pitch, and a sum of a shortest distance between the first external circuit regions and the third side, a length of the first external circuit regions along the first direction, and the first pitch is greater than a sum of a shortest distance between the second external circuit regions and the third side, and a length of the second external circuit regions along the first direction.

In an embodiment of the invention, the number of the first external circuit regions is plural, the first external circuit regions are arranged at intervals along the first direction at a first pitch, the number of the second external circuit regions is plural, the second external circuit regions are arranged at intervals along the first direction at a second pitch, and a sum of a shortest distance between the first external circuit regions and the third side and twice a length of the first external circuit regions along the first direction and the first pitch is smaller than a sum of a shortest distance between the second external circuit regions and the third side and a length of the second external circuit regions along the first direction and the second pitch.

In an embodiment of the invention, a shortest distance between the second external circuit region and the third side is greater than a length of the first external circuit region along the first direction.

In an embodiment of the invention, a shortest distance between the first external circuit region and the fourth side is greater than a sum of a shortest distance between the second external circuit region and the fourth side and a length of the second external circuit region along the first direction.

In an embodiment of the invention, the foldable display panel further includes at least one driving chip, and the driving chip is disposed on the first external circuit region and electrically connected to the first pad.

In an embodiment of the invention, the foldable display panel further includes an anisotropic conductive adhesive disposed on the first external circuit region, and the anisotropic conductive adhesive is located between the driving chip and the first pad.

In an embodiment of the invention, the foldable display panel further includes a plurality of scan lines and a plurality of data lines. The scanning lines are arranged in the display area, the data lines are arranged in the display area, each sub-pixel unit is electrically connected with one of the scanning lines and one of the data lines, each sub-pixel unit comprises a thin film transistor and an organic light emitting diode, and the organic light emitting diode is electrically connected with the thin film transistor.

In view of the above, in the foldable display panel of the present invention, the foldable display panel has at least one first external circuit area and at least one second external circuit area, the first external circuit area and the second external circuit area are respectively located on the first side and the second side of the peripheral area, the first external circuit area and the second external circuit area are separated by a first distance along the first direction, the substrate has a foldable line passing through the center of the display area, the foldable line is located between the first external circuit area and the second external circuit area and is parallel to the first direction, and the first side and the second side are respectively located on both sides of the foldable line. Therefore, after the foldable display panel is folded along the foldable line so that the first edge and the second edge of the substrate are overlapped with each other, the first external circuit area is not overlapped with the second external circuit area, in other words, the first external circuit area can be prevented from contacting the second external circuit area, so that the first connecting pad arranged on the first external circuit area and the second connecting pad arranged on the second external circuit area can be prevented from being damaged due to mutual impact, and the first printed circuit board arranged on the first external circuit area and the second printed circuit board arranged on the second external circuit area can be prevented from being damaged due to mutual impact.

Drawings

Various aspects of the disclosure may be understood by reading the following detailed description in conjunction with the accompanying drawings. It is noted that the various features of the drawings are not to scale in accordance with standard practice in the art. In fact, the dimensions of the features described may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic top view of a foldable display panel according to an embodiment of the invention.

Fig. 2 is an enlarged schematic view of the region R of fig. 1.

Fig. 3 is a schematic cross-sectional view of the cross-section line I-I' in fig. 2.

Fig. 4 is a schematic top view of fig. 1 after being folded along the folding line.

Fig. 5 is a schematic cross-sectional view of the cross-section line II-II' in fig. 2.

Fig. 6 is a schematic top view of a foldable display panel according to another embodiment of the invention.

Fig. 7 is a schematic top view of a foldable display panel according to another embodiment of the invention.

Fig. 8 is a schematic cross-sectional view of the section line III-III' in fig. 7.

Fig. 9 is a schematic perspective view of a foldable display device according to an embodiment of the present invention.

Fig. 10 is an exploded perspective view of the foldable display device of fig. 9.

Wherein, the reference numbers:

100,100a,100b foldable display panel

102 substrate

102A surface

104 buffer layer

106 switching semiconductor layer

108 insulating layer of switch

110 driving semiconductor layer

110a channel region

110b source region

110c drain region

112 drive insulating layer

114 organic light emitting diode

116 common electrode

118 encapsulation layer

120, upper electrode

122 interlayer insulating layer

123 protective layer

124 lower electrode

126A first side

126B second side

128 driving circuit

130A the third side

130B fourth side

132 foldable wire

134 first connecting pad

136 the second pad

138 first printed circuit board

140 second printed circuit board

142 flexible substrate

144 line layer

146,146b drive wafer

147,147b drive wafer

148,148b anisotropic conductive paste

200 foldable display device

202 foldable display panel

202A first planar area

202B second planar area

202C foldable area

204 first shell

204A the first frame part

204B first bottom

206 second shell

206A second frame part

206B second bottom

208 hinge member

210 first support

212 second support

216 first hinge

218 second hinge

220 planar portion

221 planar portion

222 first bending part

224 second bend

226 curved protrusion

228 curved protrusions

230 side mounting part

AA display area

AR pixel array

a1, a1', a1 ″: length

a2, a2', a2 ″: length

BA1 first external circuit region

BA2 second external circuit area

b1, b1', b1 ″ (spacing)

b2, b2', b2 ″ (spacing)

C1 capacitor

c1, c1', c1' minimum distance

c2, c2', c2' minimum distance

CT center

D1 first direction

D2 second direction

d1' shortest distance

d2' shortest distance

DE1 switching drain

DE2 drive drain

DL data line

EL organic light emitting layer

FL1 first signal line

FL2 second signal line

FL3 third signal line

GE1 switching grid

GE2 Driving Gate

GI gate insulation layer

GL gate line

I-I' cutting line

II-II' cutting line

III-III' cutting line

NA peripheral area

PE pixel electrode

PL common Power line

PX sub-pixel unit

R is a region

S1 first distance

SE1 switching source

SE2 Driving Source

T1 switching thin film transistor

T2 Driving thin film transistor

TH contact hole

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Fig. 1 is a schematic top view of a foldable display panel 100 according to an embodiment of the invention, the foldable display panel 100 includes a substrate 102 and a pixel array AR, the substrate 102 has a surface 102A, and a display area AA and a peripheral area NA on the surface 102A, and the pixel array AR is located in the display area AA. The peripheral area NA is located on at least one side of the display area AA. For example, the peripheral area NA may surround the display area AA. For convenience of illustration, fig. 1 shows the first direction D1 and the second direction D2, and the first direction D1 is different from the second direction D2, for example, the first direction D1 and the second direction D2 are the longitudinal direction and the transverse direction of fig. 1, respectively, and are orthogonal to each other.

The pixel array AR includes a plurality of sub-pixel units PX, and each sub-pixel unit PX is arranged in an array. Fig. 2 is an enlarged view of a region R of fig. 1, and fig. 3 is a cross-sectional view of a cross-sectional line I-I' of fig. 2. the foldable display panel 100 is not limited to the following structure and may be formed of an organic light emitting diode or a flexible Liquid Crystal Display (LCD) having different structures. Referring to fig. 2 and 3, the sub-pixel unit PX includes a switching thin-film transistor T1, a driving thin-film transistor T2, and a capacitor C1, and the foldable display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of common power lines PL, each of which intersects with the gate lines GL. For example, the data lines DL and the common power lines PL are parallel to the first direction D1, and the gate lines GL are parallel to the second direction D2. In the present embodiment, the sub-pixel unit PX has a structure of a two-transistor one-capacitor (2T1C), but the present invention is not limited thereto. In this embodiment, the foldable display panel 100 further includes a buffer layer 104 and a gate insulating layer GI (see fig. 3), the buffer layer 104 is disposed between the substrate 102 and the switching semiconductor layer 106 (not shown in fig. 3) and the driving semiconductor layer 110, the gate insulating layer GI is disposed on the switching semiconductor layer 106 (not shown in fig. 3) and the driving semiconductor layer 110, and the switching gate GE1 and the driving gate GE2 are disposed on the gate insulating layer GI. However, the present invention is not limited thereto. In other embodiments of the present invention, the buffer layer 104 may not be included. The material of the gate insulating layer GI may comprise an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof).

The switching thin film transistor T1 includes a switching gate electrode GE1, a switching semiconductor layer 106, a switching insulating layer 108, a switching source electrode SE1, and a switching drain electrode DE 1. The driving thin film transistor T2 includes a driving gate electrode GE2, a driving semiconductor layer 110, a driving insulating layer 112, a driving source electrode SE2, and a driving drain electrode DE 2. The switch semiconductor layer 106 and the driving semiconductor layer 110 may be formed of polysilicon or oxide semiconductor, in this embodiment, the materials of the switch semiconductor layer 106 and the driving semiconductor layer 110 may include polysilicon, that is, the switch Thin Film Transistor T1 and the driving Thin Film Transistor T2 may be low temperature polysilicon Thin Film transistors (LTPS TFTs). However, the present invention is not limited to the types of the switching thin film transistor T1 and the driving thin film transistor T2. In other embodiments, the material of the switching semiconductor layer 106 and the driving semiconductor layer 110 may include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, single crystal silicon, organic semiconductor material, metal oxide semiconductor material, carbon nanotubes/rods, perovskite, or other suitable materials.

The switching semiconductor layer 106 includes a channel region (not shown) (not doped with impurities), a source region (not shown), and a drain region (not shown). The driving semiconductor layer 110 includes a channel region 110a (not doped with impurities), a source region 110b, and a drain region 110 c. The source region 110b and the drain region 110c are formed at both sides of the channel region 110a, respectively, and are doped with impurities. Here, the impurity used depends on the type of the thin film transistor, and may include an N-type impurity or a P-type impurity.

In the present embodiment, the foldable display panel 100 further includes a passivation layer 123, and the passivation layer 123 is disposed on the switching thin film transistor T1 (not shown in fig. 3), the driving thin film transistor T2 and the capacitor C1. The material of the passivation layer 123 may be an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials, an organic material, or a combination thereof. The organic material is a polymer material such as polyimide resin, epoxy resin, or acryl resin.

The sub-pixel unit PX further includes an organic light emitting diode 114, where the organic light emitting diode 114 includes a pixel electrode PE, an organic light emitting layer EL, a common electrode 116, and an encapsulation layer 118, one of the pixel electrode PE and the common electrode 116 is a hole injection electrode, and the other is an electron injection electrode. Electrons and holes are injected from the pixel electrode PE and the common electrode 116 into the organic light emitting layer EL, and the holes and electrons are recombined with each other to emit light. The pixel electrode PE is formed of a metal having a high reflectivity, the common electrode 116 is formed of a transparent conductive layer, and light generated from the organic light emitting layer EL is reflected by the pixel electrode PE and emitted to the outside through the common electrode 116 and the encapsulation layer 118. In the present embodiment, the encapsulation layer 118 covers the organic light emitting diode 114 for isolating moisture, humidity, and the like. The material of the encapsulation layer 118 may include, but is not limited to, silicon nitride, aluminum oxide, or silicon oxynitride.

The capacitor C1 includes an upper electrode 120, an interlayer insulating layer 122, and a lower electrode 124, wherein the interlayer insulating layer 122 is disposed between the upper electrode 120 and the lower electrode 124 and includes a dielectric material. The switching thin film transistor T1 functions as a switch to select the sub-pixel unit PX for emitting light. The switching gate GE1 is connected to the gate line GL, the switching source SE1 is connected to the data line DL, and the switching drain DE1 is connected to the upper electrode 120 of the capacitor C1. The driving thin film transistor T2 applies driving power to the pixel electrode PE of the selected sub-pixel unit PX to cause the organic light emitting layer EL to emit light. The driving gate GE2 is connected to the upper electrode 120, and the upper electrode 120 is connected to the switching drain DE 1. The driving source SE2 and the lower electrode 124 are connected to a common power line PL1, and the driving drain DE2 is connected to the pixel electrode PE of the organic light emitting diode 114 through a contact hole TH.

The switching thin film transistor T1 is driven by a gate voltage applied to the gate line GL to transmit a data voltage applied to the data line DL to the driving thin film transistor T2. A voltage corresponding to a voltage difference between the common voltage applied from the common power line PL to the driving thin film transistor T2 and the data voltage transmitted from the switching thin film transistor T1 is stored in the capacitor C1, and a current corresponding to the voltage stored in the capacitor C1 is retained in the organic light emitting diode 114 via the driving thin film transistor T2, causing the organic light emitting layer EL to emit light.

The organic light emitting layer EL is formed of a polymer organic material. The organic light emitting layer EL may be a multi-layer (multi-layer) and includes at least one of a light emitting layer, a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). When the organic light emitting layer EL includes a light emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer are sequentially stacked on the pixel electrode PE from bottom to top.

In the present embodiment, the organic light emitting layer EL may be any light emitting layer used in a display panel, which is well known to those skilled in the art. The organic light emitting layer EL may be a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, an organic light emitting layer of another color, or a combination thereof.

The peripheral area NA has a first side 126A and a second side 126B opposite to each other, and the pixel array AR is located between the first side 126A and the second side 126B. In the present embodiment, the peripheral area NA has at least one first external circuit area BA1 and at least one second external circuit area BA 2. For example, the first external circuit area BA1 and the second external circuit area BA2 are respectively located on the first side 126A and the second side 126B of the peripheral area NA.

The base plate 102 has a foldable line 132 passing through the center CT of the display area AA, and the first edge 126A and the second edge 126B are respectively located at two sides of the foldable line 132. The foldable line 132 is located between the first external circuit area BA1 and the second external circuit area BA2 and is parallel to the first direction D1, and the pixel array AR overlaps the foldable line 132. The foldable display panel 100 further includes a plurality of first signal lines FL1 and a plurality of first pads 134, the first pads 134 are disposed on the first external circuit area BA1, and each of the first pads 134 is located at one end of each of the first signal lines FL 1. The other end of the first signal line FL1 is connected to the data line DL, so that the first signal line FL1 is electrically connected to the first pad 134 and can electrically connect a portion of the sub-pixel unit PX through the data line DL. The foldable display panel 100 further includes a plurality of second signal lines FL2 and a plurality of second pads 136, the second pads 136 are disposed on the second external circuit block BA2, each of the second pads 136 is located at one end of each of the second signal lines FL2, and the other end of the second signal lines FL2 is connected to the data line DL (not shown), such that the second signal lines FL2 are electrically connected to the second pads 136 and can be electrically connected to another portion of the sub-pixel units PX through the data line DL.

The foldable display panel 100 further includes a driving circuit 128 and a plurality of third signal lines FL3, and the driving circuit 128 is located at one side of the peripheral area NA. For example, the peripheral area NA further has a third side 130A and a fourth side 130B opposite to each other, and the third side 130A, the fourth side 130B, the first side 126A and the second side 126B together form the outside of the peripheral area NA. The foldable line 132 passes through the third side 130A and the fourth side 130B. The driving circuit 128 is located between the third side 130A of the peripheral area NA and the pixel array AR, the driving circuit 128 is located between the first external circuit area BA1 and the second external circuit area BA2, and the third signal line FL3 is located between the driving circuit 128 and the pixel array AR. The driving circuit 128 is, for example, an integrated gate driver array (GOA), that is, an active device (not shown) of the driving circuit 128 is fabricated together with the switching thin film transistor T1 and the driving thin film transistor T2 of the sub-pixel unit PX, but the invention is not limited thereto. The pixel array AR is electrically connected to the driving circuit 128 through the third signal line FL 3. In the present embodiment, the first side 126A and the second side 126B are parallel to the first direction D1, and the third side 130A and the fourth side 130B are parallel to the second direction D2.

In the embodiment, the foldable display panel 100 further includes a first printed circuit board 138 and a second printed circuit board 140, the first printed circuit board 138 is disposed on the first external circuit area BA1, the first pads 134 are electrically connected to the first printed circuit board 138, the second printed circuit board 140 is disposed on the second external circuit area BA2, and the second pads 136 are electrically connected to the second printed circuit board 140.

Fig. 4 is a schematic top view of fig. 1 after being folded along the foldable line 132, and referring to fig. 1 and fig. 4 together, in the present embodiment, the first and second external circuit areas BA1 and BA2 are spaced apart by a first distance S1 along the first direction D1, thus, after the foldable display panel 100 is folded along the foldable line 132, such that the first edge 126A and the second edge 126B of the substrate 102 overlap each other, the first external circuit area BA1 does not overlap the second external circuit area BA2, in other words, the first external circuit area BA1 may not contact the second external circuit area BA2, whereby, the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 can be prevented from being damaged due to collision, and the first pcb 138 disposed in the first external circuit area BA1 and the second pcb 140 disposed in the second external circuit area BA2 are prevented from being damaged by mutual impact.

The sum of the shortest distance c1 between the first external circuit area BA1 and the third side 130A and the length a1 of the first external circuit area BA1 in the first direction D1 is less than the shortest distance c2 between the second external circuit area BA2 and the third side 130A. For example, the shortest distance c1 between the first external circuit area BA1 and the third side 130A is 3 mm to 7 mm, the length a1 of the first external circuit area BA1 along the first direction D1 is 26 mm to 31 mm, and the shortest distance c2 between the second external circuit area BA2 and the third side 130A is 39 mm to 43 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

In the present embodiment, the number of the first external circuit areas BA1 is plural, and the first external circuit areas BA1 are arranged at intervals along the first direction D1 with the pitch b 1. The sum of the shortest distance c1 between the first external circuit area BA1 and the third side 130A, the length a1 of the first external circuit area BA1 in the first direction D1, and the interval b1 between the first external circuit area BA1 is greater than the sum of the shortest distance c2 between the second external circuit area BA2 and the third side 130A, and the length a2 of the second external circuit area BA2 in the first direction D1. For example, the shortest distance c1 between the first external circuit area BA1 and the third side 130A is 3 mm to 7 mm, the length a1 of each first external circuit area BA1 along the first direction D1 is 26 mm to 31 mm, the distance b1 between each first external circuit area BA1 is 40 mm to 45 mm, the shortest distance c2 between the second external circuit area BA2 and the third side 130A is 39 mm to 43 mm, and the length a2 of the second external circuit area BA2 along the first direction D1 is 26 mm to 31 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

In the present embodiment, the number of the second external circuit areas BA2 is plural, and the second external circuit areas BA2 are arranged at intervals of the interval b2 along the first direction D1. The sum of the shortest distance c1 between the first external circuit area BA1 and the third side 130A, the double length a1 of the first external circuit area BA1 along the first direction D1, and the interval b1 between the first external circuit area BA1 is smaller than the sum of the shortest distance c2 between the second external circuit area BA2 and the third side 130A, the length a2 of the second external circuit area BA2 along the first direction D1, and the interval b2 between the second external circuit area BA 2. For example, the shortest distance c1 between the first external circuit area BA1 and the third side 130A is 3 mm to 7 mm, the length of each first external circuit area BA1 along the first direction D1 is 26 mm to 31 mm, the distance b1 between the first external circuit areas BA1 is 40 mm to 45 mm, the shortest distance c2 between the second external circuit area BA2 and the third side 130A is 39 mm to 43 mm, the length a2 of the second external circuit area BA2 along the first direction D1 is 26 mm to 31 mm, and the distance b2 between the second external circuit areas BA2 is 40 mm to 45 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

Fig. 5 is a cross-sectional view of a cross-sectional line II-II' in fig. 2, and referring to fig. 1, fig. 2 and fig. 5, the first printed circuit board 138 includes a flexible substrate 142 and a circuit layer 144 disposed on the flexible substrate 142, that is, the first printed circuit board 138 is a flexible printed circuit board (FPC). In the present embodiment, the foldable display panel 100 further includes a driving Chip 146 disposed On the circuit layer 144, and the driving Chip 146 is a Chip On Film (COF) structure. For example, the driving chip 146 may be electrically connected to the circuit layer 144 by using a flip-chip bonding technique. In other embodiments, the driver chip 146 may be electrically connected to the circuit layer 144 by other techniques, such as Tape Automated Bonding (TAB) technique.

The foldable display panel 100 further includes an anisotropic conductive adhesive 148, and the circuit layer 144 of the first printed circuit board 138 is electrically connected to the first pads 134 through the anisotropic conductive adhesive 148. The anisotropic conductive adhesive 148 is disposed between the first pads 134 and the circuit layer 144 of the first printed circuit board 138. In this embodiment, the foldable display panel 100 further includes a driving wafer 147, and the driving wafer 147 is disposed on the second printed circuit board 140. The structure of the second printed circuit board 140 and the configuration relationship between the second printed circuit board 140 and the second pads 136 are similar to the structure of the first printed circuit board 138 and the configuration relationship between the first pads 134, and the configuration relationship between the driver chip 147 and the second printed circuit board 140 is similar to the configuration relationship between the driver chip 146 and the first printed circuit board 138, so the description thereof is omitted.

Fig. 6 is a schematic top view of a foldable display panel 100a according to another embodiment of the invention, please refer to fig. 6, the foldable display panel 100a of fig. 6 is similar to the foldable display panel 100 of fig. 1, only the differences between the two will be discussed, and the same or similar parts will not be repeated. The sum of the shortest distance c1' between the first external circuit area BA1 and the third side 130A and the length a1' of the first external circuit area BA1 in the first direction D1 is less than the shortest distance c2' between the second external circuit area BA2 and the third side 130A. For example, the shortest distance c1' between the first external circuit area BA1 and the third side 130A is 1 mm to 5 mm, the length a1' of the first external circuit area BA1 along the first direction D1 is 50 mm to 55 mm, and the shortest distance c2' between the second external circuit area BA2 and the third side 130A is 68 mm to 72 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

In the present embodiment, the shortest distance D1' between the first external circuit area BA1 and the fourth side 130B is greater than the sum of the shortest distance D2' between the second external circuit area BA2 and the fourth side 130B and the length a2' of the second external circuit area BA2 along the first direction D1. For example, the shortest distance D1' between the first external circuit area BA1 and the fourth side 130B is 68 mm to 72 mm, the shortest distance D2' between the second external circuit area BA2 and the fourth side 130B is 1 mm to 5 mm, and the length a2' of the second external circuit area BA2 along the first direction D1 is 50 mm to 55 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

Fig. 7 is a schematic top view of a foldable display panel 100b according to another embodiment of the invention, fig. 8 is a schematic cross-sectional view of a cross-sectional line III-III' in fig. 7, the foldable display panel 100b in fig. 7 is similar to the foldable display panel 100 in fig. 1, and only differences between the two are discussed below, and the same or similar parts are not repeated. Referring to fig. 7 and 8, the driving chip 146b is disposed on the substrate 102 by a Chip On Glass (COG) package, the foldable display panel 100b further includes an anisotropic conductive adhesive 148b between the driving chip 146b and the first pads 134, and the driving chip 146b is fixed on the first pads 134 by the anisotropic conductive adhesive 148 b. The first printed circuit board 138b is located between the first external circuit area BA1 and the first side 126A, and the foldable display panel 100b can be connected to the first printed circuit board 138b by pins (not shown) disposed on the peripheral area NA of the substrate 102. The second pcb 140B is disposed between the second external circuit area BA2 and the second side 126B, and the foldable display panel 100B can be connected to the second pcb 140B by pins (not shown) disposed on the peripheral area NA of the substrate 102.

The structure of the second printed circuit board 140b and the configuration relationship between the second printed circuit board 140b and the second pads 136b are similar to the structure of the first printed circuit board 138b and the configuration relationship between the first pads 134b, and the configuration relationship between the driving chip 147b and the second printed circuit board 140b is similar to the configuration relationship between the driving chip 146b and the first printed circuit board 138b, so the description thereof is omitted.

The sum of the shortest distance c1' between the first external circuit area BA1 and the third side 130A and the length a1 ″ of the first external circuit area BA1 in the first direction D1 is less than the shortest distance c2 ″ between the second external circuit area BA2 and the third side 130A. For example, the shortest distance c1 ″ between the first external circuit area BA1 and the third side 130A is 7 mm to 10 mm, the length of the first external circuit area BA1 along the first direction D1 is 18 mm to 22 mm, and the shortest distance c2 ″ between the second external circuit area BA2 and the third side 130A is 34 mm to 38 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first side 126A and the second side 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first printed circuit board 138B disposed between the first external circuit area BA1 and the first side 126A and the second printed circuit board 140 disposed between the second external circuit area BA2 and the second side 126B from being damaged due to mutual impact.

In the present embodiment, the number of the first external circuit areas BA1 is plural, and the first external circuit areas BA1 are arranged at intervals along the first direction D1 with the pitch b1 ″. The sum of the shortest distance c1 "between the first external circuit area BA1 and the third side 130A, the length a 1" of the first external circuit area BA1 in the first direction D1, and the interval b1 "between the first external circuit area BA1 is greater than the sum of the shortest distance c 2" between the second external circuit area BA2 and the third side 130A, and the length a2 "of the second external circuit area BA2 in the first direction D1. For example, the shortest distance c1 "between the first external circuit area BA1 and the third side 130A is 7 mm to 10 mm, the length a 1" of each first external circuit area BA1 along the first direction D1 is 18 mm to 22 mm, the distance b1 "between each first external circuit area BA1 is 32 mm to 36 mm, the shortest distance c 2" between the second external circuit area BA2 and the third side 130A is 34 mm to 38 mm, and the length a2 "of the second external circuit area BA2 along the first direction D1 is 18 mm to 22 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

In the present embodiment, the number of the second external circuit areas BA2 is plural, and the second external circuit areas BA2 are arranged at intervals along the first direction D1. The sum of the shortest distance c1 "between the first external circuit area BA1 and the third side 130A, the length a 1" of the doubled first external circuit area BA1 along the first direction D1, and the interval b1 "between the first external circuit areas BA1 is smaller than the sum of the shortest distance c 2" between the second external circuit area BA2 and the third side 130A, the length a2 "of the second external circuit area BA2 along the first direction D1, and the interval b 2" between the second external circuit areas BA 2. For example, the shortest distance c1 "between the first external circuit area BA1 and the third side 130A is 7 mm to 10 mm, the length a 1" of each first external circuit area BA1 along the first direction D1 is 18 mm to 22 mm, the distance b1 "between each first external circuit area BA1 is 32 mm to 36 mm, the shortest distance c 2" between the second external circuit area BA2 and the third side 130A is 34 mm to 38 mm, the length a2 "of the second external circuit area BA2 along the first direction D1 is 18 mm to 22 mm, and the distance b 2" between each second external circuit area BA2 is 32 mm to 36 mm. In this way, after the foldable display panel 100 is folded along the foldable line 132 such that the first edge 126A and the second edge 126B of the substrate 102 are overlapped with each other, the first external circuit area BA1 is not overlapped with the second external circuit area BA2, in other words, the first external circuit area BA1 is prevented from contacting the second external circuit area BA2, so as to prevent the first pads 134 disposed on the first external circuit area BA1 and the second pads 136 disposed on the second external circuit area BA2 from being damaged due to mutual impact, and prevent the first pcb 138 disposed on the first external circuit area BA1 and the second pcb 140 disposed on the second external circuit area BA2 from being damaged due to mutual impact.

The number of the first external circuit regions BA1 is the same as that of the second external circuit regions BA2 as illustrated in fig. 1, 6 and 7, but the present invention is not limited thereto. In other embodiments, the number of the first external circuit areas BA1 may be different from the number of the second external circuit areas BA 2.

Fig. 9 is a perspective view of a foldable display device 200 according to an embodiment of the invention, fig. 10 is an exploded perspective view of the foldable display device 200 of fig. 9, and referring to fig. 9 and 10 together, the foldable display device 200 includes a foldable display panel 202, a first housing 204, a second housing 206, a hinge member 208, a first support 210, and a second support 212. The foldable display device 200 may further include a touch panel (not shown) and a protection layer (not shown) sequentially disposed on the foldable display panel 202. The touch panel can be used for sensing touch operation of a user. The protection layer is made of a transparent hard material, and is used for transmitting the display image of the foldable display panel 202 and protecting the foldable display panel 202 from external impact.

The foldable display panel 202 includes a first planar area 202A, a second planar area 202B and a foldable area 202C, the first planar area 202A and the second planar area 202B are respectively located at two sides of the foldable area 202C, a first housing 204 and a second housing 206 are coupled to the foldable area 202C and are used for accommodating the foldable display panel 202, and the foldable line 132 passes through a center CT of the foldable area 202C. The rotation points of the first housing 204 and the second housing 206 are connected to each other by a hinge member 208 in the foldable area 202C. The hinge member 208 is used to connect the first housing 204 and the second housing 206.

The first housing 204 includes a first frame portion 204A and a first bottom portion 204B, the first frame portion 204A is configured to surround a periphery of the first planar area 202A of the foldable display panel 202, and the first bottom portion 204B is configured to accommodate the first planar area 202A of the foldable display panel 202. The second housing 206 includes a second frame portion 206A and a second bottom portion 206B, the second frame portion 206A is configured to surround a periphery of the second planar area 202B of the foldable display panel 202, and the second bottom portion 206B is configured to accommodate the second planar area 202B of the foldable display panel 202. The first frame portion 204A and the second frame portion 206A further include a curved protrusion 226 and a curved protrusion 228, respectively, the curved protrusion 226 being formed to protrude from the first frame portion 204A, and the curved protrusion 228 being formed to protrude from an end portion of the second frame portion 206A.

The first support 210 and the second support 212 are used for supporting the foldable display panel 202 in a folded or unfolded state. For example, the first supporting member 210 is located between the foldable display panel 202 and the first bottom portion 204B of the first casing 204, and is rotatably mounted to the first frame portion 204A of the first casing 204 by a first hinge 216. The second support 212 is located between the foldable display panel 202 and the second bottom 206B of the second housing 206, and is rotatably mounted to the second frame portion 206A of the second housing 206 by a second hinge 218. Accordingly, when the foldable display device 200 is unfolded, the first support 210 and the second support 212 support the foldable display panel 202 while rotating with respect to the first hinge 216 and the second hinge 218, respectively.

In some embodiments, the foldable display device 200 further includes a side mounting portion 230, the side mounting portion 230 is disposed corresponding to a side of the foldable area 202C of the foldable display panel 202, and the side mounting portion 230 of one side is mounted to the first bottom portion 204B and the second bottom portion 206B, and the side mounting portion 230 of the other side is connected to respective rotation points of the first frame portion 204A and the second frame portion 206A.

The first bottom portion 204B includes a planar portion 220 and a first curved portion 222, the second bottom portion 206B includes a planar portion 221 and a second curved portion 224, and the first curved portion 222 and the second curved portion 224 are used for connecting the planar portion 220 and the planar portion 221. The first and second curved portions 222 and 224 are connected to each other by the hinge member 208. When the foldable display device 200 is in the unfolded state, the first planar area 202A and the second planar area 202B of the foldable display panel 202 are supported by the first bottom 204B of the first housing 204 and the second bottom 206B of the second housing 206, respectively, and the foldable area 202C is supported by the hinge member 208.

In summary, the foldable display panel according to at least one embodiment of the invention includes at least one first external circuit area and at least one second external circuit area, the first external circuit area and the second external circuit area are respectively located on a first side and a second side of the peripheral area, the first external circuit area and the second external circuit area are separated by a first distance along a first direction, the substrate has a foldable line passing through a center of the display area, and the foldable line is located between the first external circuit area and the second external circuit area and is parallel to the first direction. Therefore, after the foldable display panel is folded along the foldable line so that the first edge and the second edge of the substrate are overlapped with each other, the first external circuit area is not overlapped with the second external circuit area, in other words, the first external circuit area can be prevented from contacting the second external circuit area, so that the first connecting pad arranged on the first external circuit area and the second connecting pad arranged on the second external circuit area can be prevented from being damaged due to mutual impact, and the first printed circuit board arranged on the first external circuit area and the second printed circuit board arranged on the second external circuit area can be prevented from being damaged due to mutual impact.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.