阅读说明：本技术 开关元件、存储装置和存储器系统 (Switching element, memory device, and memory system ) 是由 清宏彰 大场和博 保田周一郎 于 2019-01-31 设计创作，主要内容包括：根据本公开的一个实施例的开关元件设置有：第一电极；第二电极,被布置为面对所述第一电极；和开关层,布置在所述第一电极和所述第二电极之间,并且包含选择硒(Se)、锗(Ge)和硅(Si)中的至少一种元素,同时包含硼(B)、碳(C)、镓(Ga)和砷(As)。(A switching element according to one embodiment of the present disclosure is provided with: a first electrode; a second electrode arranged to face the first electrode; and a switching layer disposed between the first electrode and the second electrode and including at least one element selected from selenium (Se), germanium (Ge), and silicon (Si) while including boron (B), carbon (C), gallium (Ga), and arsenic (As).)

1. A switching element, comprising:

a first electrode;

a second electrode disposed opposite to the first electrode; and

a switching layer including selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As), at least one of germanium (Ge) and silicon (Si), and disposed between the first electrode and the second electrode.

2. The switching element of claim 1, wherein

The switching layer includes carbon (C), boron (B), germanium (Ge) and silicon (Si), the carbon (C), boron (B) and germanium (Ge) or silicon (Si) or both of germanium (Ge) and silicon (Si) are in a range of 15 at% or more and 35 at% or less, the combination of carbon (C) and boron (B) is in a range of 5 at% or more and 20 at% or less, and the ratio of carbon (C) to the total amount of carbon (C) and boron (B) is in a range of 0 at% or more and 0.2 or less,

gallium (Ge) is included in a range of 2 atomic% or more and 10 atomic% or less, and

the switching element includes arsenic (As) and selenium (Se), the arsenic (As) and selenium (Se) being in a range of 60 at% or more and 80 at% or less, the arsenic (As) being in a range of 20 at% or more and 40 at% or less, and the selenium (Se) being in a range of 30 at% or more and 50 at% or less.

3. The switching element of claim 1, wherein the switching layer further comprises nitrogen (N).

4. The switching element according to claim 3, wherein the nitrogen (N) is included in a range of 30 atomic% or less of all elements included in the switching layer.

5. The switching element according to claim 1, wherein a film thickness of the switching layer is 3nm or more and 30nm or less.

6. The switching element according to claim 1, wherein a film thickness of the switching layer is 10nm or more and 20nm or less.

7. The switching element according to claim 1, wherein a layer composed of carbon (C) or a layer including carbon (C) is provided between the switching layer and at least one of the first electrode and the second electrode.

8. The switching element according to claim 1, wherein the switching layer changes to a low resistance state by increasing an applied voltage above a predetermined threshold voltage and changes to a high resistance state by decreasing the applied voltage to a voltage lower than the threshold voltage in the absence of a phase transition between an amorphous phase and a crystalline phase.

9. A memory device provided with one or more memory cells, each of the memory cells including a memory element and a switching element directly coupled to the memory element, the switching element comprising:

a first electrode;

a second electrode disposed opposite to the first electrode; and

a switching layer including selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As), at least one of germanium (Ge) and silicon (Si), and disposed between the first electrode and the second electrode.

10. The memory device according to claim 9, wherein the one or more memory cells are arranged along one or more first wirings extending in one direction, one or more second wirings extending in another direction and intersecting the first wirings, and at intersections of the first wirings and the second wirings.

11. The memory device according to claim 9, wherein the memory element is any one of a phase change memory element, a resistance change memory element, and a magnetoresistive memory element.

12. The memory device of claim 9, wherein two or more of the plurality of memory cells are stacked.

13. A memory system provided with a host computer, a memory, and a memory controller, the host computer including a processor, the memory including a memory cell array including a plurality of memory cells, the memory controller performing control of a request for the memory in accordance with a command from the host computer, each of the plurality of memory cells including a memory element and a switching element directly coupled to the memory element, the switching element comprising:

a first electrode;

a second electrode disposed opposite to the first electrode; and

a switching layer including selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As), at least one of germanium (Ge) and silicon (Si), and disposed between the first electrode and the second electrode.

Technical Field

The present disclosure relates to a switching element including a chalcogenide layer between electrodes, and to a memory device and a memory system each including the switching element.

Background

In recent years, the capacity of data storage nonvolatile memories represented by resistance change type memories such as ReRAM (resistance random access memory) and PRAM (phase change random access memory) (registered trademark) is required to increase. However, in the conventional resistance change memory devices each using an access transistor, the occupied area per unit cell is large. Therefore, even if miniaturization is performed under the same design rule, an increase in capacity is not easy as compared with, for example, a flash memory such as a NAND-type flash memory. In contrast, in the case of using a so-called cross-point array structure in which memory elements are arranged at intersections (cross points) of wirings that intersect with each other, the footprint per unit cell is reduced, which makes it possible to achieve an increase in capacity.

In the cross-point memory cell, a selection element (switching element) for cell selection is provided in addition to the memory element. Examples of the switching element include a switching element configured using, for example, a PN diode, an avalanche diode, or a metal oxide (for example, refer to non-patent documents 1 and 2). In addition, examples of the switching element also include a switching element (an Ovonic Threshold Switch (OTS) element) using, for example, a chalcogenide material (for example, refer to patent documents 1 and 2 and non-patent document 3).

CITATION LIST

Patent document

Patent document 1: japanese unexamined patent application publication No.2006-86526

Patent document 2: japanese unexamined patent application publication No.2010-157316

Non-patent document

Non-patent document 1: 2011IEEE IEDM11-733 to 736 by Jiun-Jia Huang et al

Non-patent document 2: 2012IEEE VLSI Technology symposium of Wootea Lee et al, pages 37 to 38

Non-patent document 3: 2012IEEE IEDM2.6.1 to 2.6.4 of Myoung-Jae Lee et al

Disclosure of Invention

Incidentally, the switching element using selenium (Se) is expected to achieve improvement in heat resistance while having an advantage of low leakage current, as compared with the case where the switching element uses any other chalcogen element such as Te.

It is desirable to provide a switching element that makes it possible to improve heat resistance, and a memory device and a memory system each including the switching element.

A switching element according to an embodiment of the present disclosure includes: a first electrode; a second electrode disposed opposite to the first electrode; and a switching layer including selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As), and disposed between the first electrode and the second electrode.

A memory device according to an embodiment of the present disclosure includes a plurality of memory cells, and each memory cell includes a memory element and the above-described switching element according to an embodiment of the present disclosure directly coupled to the memory element.

A memory system according to an embodiment of the present disclosure includes: a host computer including a processor; a memory including a memory cell array including a plurality of memory cells; and a memory controller that performs control of a request for the memory in accordance with a command from the host computer; and each of the plurality of memory cells includes a memory element and the above-described switching element according to an embodiment of the present disclosure directly coupled to the memory element.

In the switching element according to the embodiment of the present disclosure, the memory device according to the embodiment of the present disclosure, and the memory system according to the embodiment of the present disclosure, the switching layer includes at least one of germanium (Ge) and silicon (Si), selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As). This makes it possible to reduce deterioration (alteration) of the switching layer caused by a thermal load in the manufacturing process.

According to the switching element according to the embodiment of the present disclosure, the memory device according to the embodiment of the present disclosure, and the memory system according to the embodiment of the present disclosure, the switching layer is formed using selenium (Se), boron (B), carbon (C), gallium (Ga), and arsenic (As), which reduce deterioration of the switching layer caused by a thermal load in a manufacturing process. This makes it possible to improve the heat resistance of the switching element using selenium (Se).

It is to be noted that the effects described herein are not limited and may include any of the effects described in the present disclosure.

Drawings

Fig. 1 is a sectional view of an example of a configuration of a switching element according to an embodiment of the present disclosure.

Fig. 2 is a sectional view of another example of a configuration of a switching element according to an embodiment of the present disclosure.

Fig. 3 is a cross-sectional view of another example of a switching element according to an embodiment of the present disclosure.

Fig. 4 is a sectional view of another example of a configuration of a switching element according to an embodiment of the present disclosure.

Fig. 5 shows an example of a schematic configuration of a memory cell array according to an embodiment of the present disclosure.

Fig. 6 is a sectional view of an example of the configuration of the memory cell shown in fig. 5.

Fig. 7 is a cross-sectional view of another example of the configuration of the memory cell shown in fig. 5.

Fig. 8 is a sectional view of another example of the configuration of the memory cell shown in fig. 5.

Fig. 9 shows a schematic configuration of a memory cell array according to modified example 1 of the present disclosure.

Fig. 10 shows an example of a schematic configuration of a memory cell array according to modified example 2 of the present disclosure.

Fig. 11 shows another example of a schematic configuration of a memory cell array according to modified example 2 of the present disclosure.

Fig. 12 shows another example of a schematic configuration of a memory cell array according to modified example 2 of the present disclosure.

Fig. 13 shows another example of a schematic configuration of a memory cell array according to modified example 2 of the present disclosure.

Fig. 14 is a block diagram showing the configuration of a data storage system including the memory system of the present disclosure.

FIG. 15 is an IV characteristic diagram after heat treatment at 320 ℃ for 2 hours in Experimental example 1-1.

FIG. 16 is an IV characteristic diagram after heat treatment at 400 ℃ for 1 hour in Experimental example 1-1.

Fig. 17 is an IV characteristic diagram in experimental examples 1 to 8.

Fig. 18 is a graph of IV characteristics in experimental examples 1 to 9.

Fig. 19 is a characteristic diagram showing an operation example under positive voltage and negative voltage in experimental examples 1 to 4.

Fig. 20 shows the composition range of elements included in the switching layer.

Detailed Description

Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following description gives specific examples of the present disclosure, and the present disclosure is not limited to the following embodiments. Also, the present disclosure is not limited to the positions, sizes, size ratios, and the like of the respective components shown in the respective drawings. Note that the description is given in the following order.