阅读说明：本技术 半导体设备与成像设备 (Semiconductor device and imaging device ) 是由 横山孝司 冈干生 神田泰夫 于 2019-02-07 设计创作，主要内容包括：提供一种适合于高度集成的结构的半导体设备。该半导体设备具有：晶体管,具有栅极部、第一扩散层、以及第二扩散层；第一导电部；第二导电部,与第一导电部电绝缘；第一存储器元件,位于第一扩散层与第一导电部之间并且电连接至第一扩散层和第一导电部；以及第二存储器元件,位于第二扩散层与第二导电部之间并且电连接至第二扩散层和第二导电部。(A semiconductor device suitable for a highly integrated structure is provided. The semiconductor device has: a transistor having a gate portion, a first diffusion layer, and a second diffusion layer; a first conductive portion; a second conductive portion electrically insulated from the first conductive portion; a first memory element located between the first diffusion layer and the first conductive portion and electrically connected to the first diffusion layer and the first conductive portion; and a second memory element located between the second diffusion layer and the second conductive portion and electrically connected to the second diffusion layer and the second conductive portion.)

1. A semiconductor device, comprising:

a transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

a first conductive portion;

a second conductive portion electrically insulated from the first conductive portion;

a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion.

2. The semiconductor device of claim 1, further comprising:

a third conductive portion that is disposed opposite to the first storage element and electrically coupled to the first diffusion layer, as viewed from the first diffusion layer; and

a fourth conductive portion that is disposed opposite to the second storage element and electrically coupled to the second diffusion layer, as viewed from the second diffusion layer.

3. The semiconductor device of claim 1, wherein the gate portion, the first conductive portion, and the second conductive portion all extend along a first direction.

4. The semiconductor device of claim 2, wherein the gate portion and the first through fourth conductive portions all extend along a first direction.

5. The semiconductor device according to claim 1, further comprising a semiconductor substrate having a first surface on which the gate portion is provided and a second surface positioned opposite to the first surface, wherein,

the first diffusion layer constitutes a portion of the semiconductor substrate near the first surface; and is

The second diffusion layer constitutes another portion of the semiconductor substrate near the first surface.

6. The semiconductor device of claim 5, further comprising:

a first insulating layer covering the second surface of the semiconductor substrate; and

a first connection portion and a second connection portion each penetrating the first insulating layer; wherein the content of the first and second substances,

the first storage element and the second storage element are each disposed opposite to the second surface, as viewed from the first insulating layer;

the first storage element is electrically coupled to the first diffusion layer through the first connection portion; and is

The second memory element is electrically coupled to the second diffusion layer through the second connection portion.

7. The semiconductor device of claim 6, further comprising:

a second insulating layer covering the first surface of the semiconductor substrate;

a third conductive portion and a fourth conductive portion each disposed opposite to the second surface as viewed from the second insulating layer;

a third connection portion penetrating the second insulating layer and electrically coupling the first diffusion layer and the third conductive portion to each other; and

a fourth connection portion penetrating the second insulating layer and electrically coupling the second diffusion layer and the fourth conductive portion to each other.

8. The semiconductor device according to claim 7, further comprising a controller that performs the following control:

setting an electric potential of the first conductive portion to a first electric potential, setting an electric potential of the fourth conductive portion to a second electric potential higher than the first electric potential, setting an electric potential of the gate portion to the second electric potential, and setting an electric potential of the second conductive portion and an electric potential of the third conductive portion to a third electric potential that is independent of all of the electric potential of the first conductive portion, the electric potential of the fourth conductive portion, and the electric potential of the gate portion, thereby writing first information in the first memory element; and is

Setting the potential of the first conductive portion to the second potential, setting the potential of the fourth conductive portion to the first potential, setting the potential of the gate portion to the second potential, and setting the potentials of the second conductive portion and the third conductive portion to the third potential, thereby writing second information in the first memory element.

9. The semiconductor device according to claim 8, wherein the controller comprises a potential control circuit capable of keeping the potential of the second conductive portion and the potential of the third conductive portion at the third potential.

10. The semiconductor device according to claim 7, further comprising a controller that performs the following control:

setting the potential of the second conductive portion to a first potential, setting the potential of the third conductive portion to a second potential higher than the first potential, setting the potential of the gate portion to the second potential, and setting the potential of the first conductive portion and the potential of the fourth conductive portion to a fourth potential that is independent of all of the potential of the second conductive portion, the potential of the third conductive portion, and the potential of the gate portion, thereby writing first information into the second memory element; and is

Setting the potential of the second conductive portion to the second potential, setting the potential of the third conductive portion to the first potential, setting the potential of the gate portion to the second potential, and setting the potential of the first conductive portion and the potential of the fourth conductive portion to the fourth potential, thereby writing second information in the second memory element.

11. The semiconductor device according to claim 10, wherein the controller comprises a potential control circuit capable of keeping the potential of the first conductive portion and the potential of the fourth conductive portion at the fourth potential.

12. The semiconductor device of claim 5, further comprising:

a first insulating layer covering the first surface of the semiconductor substrate;

a first connection portion and a second connection portion each penetrating the first insulating layer;

a third conductive portion that is provided opposite to the first surface as viewed from the first insulating layer and is electrically coupled to the first diffusion layer through the first connection portion; and

a fourth conductive portion that is disposed opposite to the first surface and electrically coupled to the second diffusion layer through the second connection portion, as viewed from the first insulating layer.

13. The semiconductor device of claim 12, further comprising:

a second insulating layer covering the second surface of the semiconductor substrate; and

a third connection portion and a fourth connection portion each penetrating the second insulating layer; wherein the content of the first and second substances,

the first conductive portion is disposed opposite to the second insulating layer and electrically coupled to the first diffusion layer through the third connection portion, as viewed from the first memory element; and is

The second conductive portion is disposed opposite to the second insulating layer and electrically coupled to the second diffusion layer through the fourth connection portion, as viewed from the second memory element.

14. The semiconductor device of claim 1, further comprising a fin comprising semiconductor material and extending in a second direction that intersects the first direction, wherein,

the first storage element and the second storage element are each coupled to a back side of the fin; and is

The gate portion, the first diffusion layer, and the second diffusion layer extend in the first direction and cover surfaces other than the back surface of the fin portion.

15. An image forming apparatus comprising:

a semiconductor device; and

an imaging element stacked on the semiconductor device;

the semiconductor device includes:

a transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

a first conductive portion;

a second conductive portion electrically insulated from the first conductive portion;

a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion.

Technical Field

The present disclosure relates to a semiconductor device including a transistor and a memory element, and an imaging device including the semiconductor device.

Background

For a semiconductor integrated circuit including CMOS (complementary metal oxide semiconductor) transistors, higher integration and higher operation speed thereof have been studied. In recent years, switching from a volatile memory to a nonvolatile memory has been studied from the viewpoint of low power consumption, and for example, development of MRAM (magnetoresistive random access memory) has been proposed (for example, see PTL 1).

Reference list

Patent document

PTL 1: international publication No. WO 2007/066407

Disclosure of Invention

Incidentally, a semiconductor device including the semiconductor integrated circuit is expected to be more highly integrated. Accordingly, it is desirable to provide a semiconductor device having a structure suitable for higher integration, and an imaging device including the semiconductor device.

A semiconductor device as an embodiment of the present disclosure includes: a transistor including a gate portion, a source portion, and a drain portion; a first conductive portion; a second conductive portion electrically insulated from the first conductive portion; a first memory element located between the source portion and the first conductive portion and electrically coupled to each of the source portion and the first conductive portion; and a second memory element located between the drain portion and the second conductive portion and electrically coupled to each of the drain portion and the second conductive portion. Further, an imaging apparatus as an embodiment of the present disclosure includes the semiconductor apparatus described above.

In the semiconductor device and the imaging device as the embodiments of the present disclosure, the first storage element is coupled to a source portion of the transistor, and the second storage element is coupled to a drain portion of the transistor. Thus, for example, the overall footprint is smaller than if the first and second storage elements were coupled to the source portion.

The semiconductor device and the imaging device as embodiments of the present disclosure are suitable for higher integration. It should be noted that the effect of the present disclosure is not limited to this, and may be any effect described below.

Drawings

Fig. 1A is a cross-sectional view showing a configuration example of a semiconductor apparatus according to a first embodiment of the present disclosure.

Fig. 1B is a plan view showing a configuration example of the semiconductor apparatus shown in fig. 1A.

Fig. 1C is another plan view showing a configuration example of the semiconductor apparatus shown in fig. 1A.

Fig. 1D is a circuit diagram of the semiconductor apparatus shown in fig. 1A.

Fig. 2 is a cross-sectional view showing an example of the configuration of a memory portion of the memory element shown in fig. 1A.

Fig. 3 is a cross-sectional view showing an example of a configuration of each layer of the memory part shown in fig. 2.

Fig. 4A is an explanatory diagram for describing a method of writing first information into the first memory element of the semiconductor apparatus shown in fig. 1A.

Fig. 4B is an explanatory diagram for describing a method of writing second information into the first memory element of the semiconductor apparatus shown in fig. 1A.

Fig. 4C is an explanatory diagram for describing a method of writing first information into the second memory element of the semiconductor apparatus shown in fig. 1A.

Fig. 4D is an explanatory diagram for describing a method of writing second information into the second memory element of the semiconductor apparatus shown in fig. 1A.

Fig. 5A is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment of the present disclosure.

Fig. 5B is a plan view showing a configuration example of the semiconductor apparatus shown in fig. 5A.

Fig. 5C is another plan view showing a configuration example of the semiconductor apparatus shown in fig. 5A.

Fig. 6A is a perspective view showing a configuration example of a semiconductor device according to a third embodiment of the present disclosure.

Fig. 6B is a cross-sectional view showing a configuration example of the semiconductor device shown in fig. 6A.

Fig. 6C is a cross-sectional view showing a modification of the semiconductor apparatus shown in fig. 6A.

Fig. 7A is a perspective view schematically showing an imaging apparatus as an application example of a semiconductor apparatus including the present disclosure.

Fig. 7B is a cross-sectional view showing a configuration example of the image forming apparatus shown in fig. 7A.

Fig. 8A is a cross-sectional view showing a configuration example of a semiconductor device as a reference example.

Fig. 8B is a plan view showing a semiconductor apparatus as a reference example shown in fig. 8A.

Fig. 9A is an explanatory diagram describing a method of writing second information into a first memory element of a semiconductor device as another modification of the present disclosure.

Fig. 9B is an explanatory diagram describing a method of writing first information into a first memory element of a semiconductor device as another modification of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the description is given in the following order.

1. First embodiment (semiconductor device including two memory elements on the back surface side of semiconductor substrate)

2. Second embodiment (semiconductor device including two memory elements on front surface side of semiconductor substrate)

3. Third embodiment (semiconductor device including two memory elements on the back surface side of fin-shaped semiconductor layer)

4. Application example (imaging device including semiconductor device and sensor device bonded together)

5. Other modifications

<1 > first embodiment >

[ configuration of semiconductor device 1 ]

Fig. 1A shows a cross-sectional configuration of a semiconductor device 1 as a first embodiment of the present disclosure. Further, fig. 1B and 1C show a planar configuration of the semiconductor apparatus 1. Note that fig. 1B shows a planar configuration of the semiconductor device 1 when viewed from a main surface 10A side of the semiconductor substrate 10 described later, and fig. 1C shows a planar configuration of the semiconductor device 1 when viewed from a rear surface 10B side of the semiconductor substrate 10 described later. Fig. 1A corresponds to a cross-sectional view along a section line IA-IA shown in each of fig. 1B and 1C, viewed from the direction of the arrows. Fig. 1D is a circuit diagram of the semiconductor apparatus 1.

As illustrated in fig. 1A to 1D, the semiconductor device 1 includes a transistor 20, a bit line BL1 as a first conductive part, a bit line BL2 as a second conductive part electrically insulated from the bit line BL1, a memory element 30A as a first memory element, and a memory element 30B as a second memory element. The transistor 20 includes a gate electrode 21 as a gate portion, a diffusion layer 22S as a source portion, and a diffusion layer 22D as a drain portion. The storage element 30A is located between the diffusion layer 22S and the bit line BL1 and is electrically coupled to each of the diffusion layer 22S and the bit line BL 1. The storage element 30B is located between the diffusion layer 22D and the bit line BL2, and is electrically coupled to each of the diffusion layer 22D and the bit line BL 2. Further, for example, the gate electrode 21, the bit line BL1, and the bit line BL2 each include a highly conductive material such as copper (Cu) and extend in the Y-axis direction (see fig. 1B).

The semiconductor device 1 further includes a select line SL2 as a third conductive part and a select line SL1 as a fourth conductive part. The selection line SL2 is disposed opposite the memory element 30A as viewed from the diffusion layer 22S and is electrically coupled to the diffusion layer 22S. The select line SL1 is disposed opposite the memory element 30B as viewed from the diffusion layer 22D and is electrically coupled to the diffusion layer 22D. Further, for example, like the gate electrode 21, the bit line BL1, and the bit line BL2, the select line SL2 and the select line SL1 further include a high conductive material such as copper (Cu) and extend in the Y-axis direction (see fig. 1C).

For example, the semiconductor device 1 is a device in which a multilayer wiring forming portion 40, an interlayer insulating layer 27, an interlayer insulating layer 26, a semiconductor substrate 10, and an insulating layer 60 are stacked in this order on a support substrate 50. The transistor 20 is disposed close to the main surface (front surface) 10A of the semiconductor substrate 10. The memory element 30A and the memory element 30B are provided on the back surface 10B of the semiconductor substrate 10 with the insulating layer 60 interposed between the semiconductor substrate 10 and the memory elements 30A and 30B. It should be noted that the number of transistors 20 provided on the semiconductor substrate 10 is not particularly limited. The number of the transistors 20 may be one, or may be two or more.

The semiconductor substrate 10 includes an element region R1 in which a part of the transistor 20 is disposed and an isolation region R2 surrounding the element region R1. In the isolation region R2 of the semiconductor substrate 10, for example, an element isolation layer 11 formed of STI (shallow trench isolation) is provided. For example, the element isolation layer 11 is a layer including a silicon oxide film (SiO)₂) And one surface thereof is exposed in the main surface 10A of the semiconductor substrate 10.

For example, a portion of the semiconductor substrate 10 occupying the element region R1 includes single crystal silicon having a channel region and a pair of diffusion layers 22S and 22D constituting a portion of the transistor 20 formed thereon.

The rear surface 10B of the semiconductor substrate 10 is covered with an insulating layer 60. The memory elements 30A and 30B are provided on the surface of the insulating layer 60 opposite to the surface thereof in contact with the back surface 10B, that is, on the upper surface 60S of the insulating layer 60.

The element region R1 is further provided with a contact plug P1 as a first connection portion and a contact plug P2 as a second connection portion, the contact plug P1 and the contact plug P2 each extending to penetrate the insulating layer 60. For example, the contact plugs P1 and P2 include a material mainly containing a low-resistance metal such as Cu (copper), W (tungsten), or aluminum (Al). Further, around the low-resistance metal, a barrier metal layer including a single substance of Ti (titanium) or Ta (tantalum) or an alloy thereof may be provided. The contact plug P1 and the contact plug P2 are each surrounded by the insulating layer 60 and are electrically isolated from each other. The lower end of the contact plug P1 is in contact with a later-described silicide region 25S, and the upper end of the contact plug P1 is in contact with the memory element 30A. The lower end of the contact plug P2 is in contact with a later-described silicide region 25D, and the upper end of the contact plug P2 is in contact with the memory element 30B. Thus, memory element 30A is electrically coupled to the silicide region 25S of the source region by contact plug P1, and memory element 30B is electrically coupled to the silicide region 25D of the drain region by contact plug P2. Note that, for example, the contact plugs P1 and P2 are shaped to become gradually larger in the occupied area from the silicide regions 25S and 25D toward the memory elements 30A and 30B.

For example, the transistor 20 is a transistor that selects between the memory elements 30A and 30B and is a planar transistor including a gate electrode 21 and a pair of diffusion layers 22S and 22D serving as a source region and a drain region. The gate electrode 21 is coupled to the word line WL of the memory elements 30A and 30B.

Gate electrode 21 is provided on main surface 10A of semiconductor substrate 10. However, a gate insulating film 23 including a silicon oxide film or the like is provided between the gate electrode 21 and the semiconductor substrate 10. For example, the sidewall 24 of the stacked film including the silicon oxide film 24A and the silicon nitride film 24B is provided on the side surface of the gate electrode 21.

For example, the pair of diffusion layers 22S and 22D includes silicon having impurities diffused therein. Specifically, the diffusion layer 22S corresponds to the source region, and the diffusion layer 22D corresponds to the drain region. The pair of diffusion layers 22S and 22D are provided across the channel region of the semiconductor substrate 10 opposite to the gate electrode 21. Respective portions of the diffusion layers 22S and 22D are provided with silicide regions 25S and 25D including metal silicide such as NiSi (nickel silicide) or CoSi (cobalt silicide). The silicide regions 25S and 25D reduce contact resistance between later-described connection layers 28A to 28D and diffusion layers 22S and 22D. One surface of each of the silicide regions 25S and 25D is exposed in the main surface 10A of the semiconductor substrate 10, and the other surface thereof opposite to the one surface is covered with an insulating layer 60. Further, it is desirable that the diffusion layers 22S and 22D and the silicide regions 25S and 25D are all smaller in thickness than the element isolation layer 11.

The word lines WL and the select lines SL1 and SL2 are embedded in the interlayer insulating layer 27. Further, the connection layers 28A to 28C are provided so as to penetrate the interlayer insulation layers 26 and 27. Here, the gate electrode 21 is coupled to the word line WL via the connection layer 28C. The silicide region 25S of the diffusion layer 22S serving as a source region is coupled to the select line SL2 via the connection layer 28A serving as a source electrode. Further, the silicide region 25D of the diffusion layer 22D serving as a drain region is coupled to the select line SL1 via the connection layer 28B serving as a drain electrode. The connection layer 28A is a specific example corresponding to the "third connection portion" of the present disclosure, and the connection layer 28B is a specific example corresponding to the "fourth connection portion" of the present disclosure. Note that the selection line SL2 is coupled to a via V1 of the later-described wiring line group 40A, and the selection line SL1 is coupled to a via V1 of the later-described wiring line group 40B.

For example, the multilayer wiring forming part 40 includes a stack of an interlayer insulating layer 41, an interlayer insulating layer 42, an interlayer insulating layer 43, and an interlayer insulating layer 44 in ascending order of distance from the transistor 20 in such a manner that the wiring line groups 40A and 40B are disposed therein. The wiring line groups 40A and 40B have a structure in which a metal layer M1, a metal layer M2, a metal layer M3, and a metal layer M4 are stacked. Here, the metal layer M1 is embedded in the interlayer insulating layer 41, the metal layer M2 is embedded in the interlayer insulating layer 42, the metal layer M3 is embedded in the interlayer insulating layer 43, and the metal layer M4 is embedded in the interlayer insulating layer 44. Routing line groups 40A and 40B further include vias V1 through V4. The metal layer M1 and the metal layer M2 are coupled to each other by a via V2 penetrating the interlayer insulating layer 42. Also, the metal layer M2 and the metal layer M3 are coupled to each other through a via V3 penetrating the interlayer insulating layer 43, and the metal layer M3 and the metal layer M4 are coupled to each other through a via V4 penetrating the interlayer insulating layer 44. As described above, the wiring line group 40A is coupled to the silicide region 25S of the diffusion layer 22S serving as the source region through the via V1, the select line SL2, and the connection layer 28A. Further, the wiring line group 40B is coupled to the silicide region 25D of the diffusion layer 22D serving as the drain region through the via V1, the select line SL1, and the connection layer 28B. It should be noted that the configuration of the multilayer wiring forming part 40 shown in fig. 1A is an embodiment and is not limited.

The multilayer wiring forming section 40 is bonded to the support substrate 50. The support substrate 50 is, for example, a substrate including single crystal silicon. Note that the material of the support substrate 50 is not particularly limited. Instead of single crystal silicon, the support substrate 50 may include, for example, SiO₂Or another material such as glass.

As described above, the insulating layer 60 is provided to cover the semiconductor substrate 10. The insulating layer 60 may have a stacked structure of a first layer including, for example, a high-K (high dielectric constant) film capable of being formed at a low temperature, i.e., Hf oxide, Al, and a third layer₂O₃Ru (ruthenium) oxide, Ta oxide, oxide containing Al, Ru, Ta, or Hf, and Si, nitride containing Al, Ru, Ta, or Hf, and Si, oxynitride containing Al, Ru, Ta, or Hf, and Si, etc., and the second layer comprises, for example, SiO₂And the third layer comprises a dielectric constant (low-K) lower than that of SiO₂The material of (1).

The memory element 30A and the memory element 30B have a stacked structure in which, for example, a conductive layer 31 as a lower electrode, a memory portion 32, and a conductive layer 33 as an upper electrode are stacked in this order. The conductive layer 31 of the memory element 30A is coupled to the silicide region 25S through a contact plug P1. The conductive layer 31 of the memory element 30B is coupled to the silicide region 25D by a contact plug P2.

The backside interlayer film 71 is provided around the memory element 30A and the memory element 30B. Examples of the material of the backside interlayer film 71 include SiO₂low-K (low dielectric constant) films, and the like. The upper surface of the conductive layer 33 in the memory element 30A is in contact with the lower surface of the bit line BL1, and the upper surface of the conductive layer 33 in the memory element 30B is in contact with the lower surface of the bit line BL 2. The insulating layer 72 fills the peripheries of the bit line BL1 and the bit line BL 2.

For example, the storage section 32 in the storage element 30 is preferably a spin-injection magnetization-reversal storage element (STT-MTJ: spin transfer torque-magnetic tunnel junction) that stores information by reversing the magnetization direction of a storage layer described later by spin injection. STT-MTJs enable high speed reading and writing and are thus promising as non-volatile memories in place of volatile memories.

For example, the conductive layer 31 and the conductive layer 33 include a metal material such as Cu, Ti, W, or Ru. The conductive layer 31 and the conductive layer 33 preferably mainly include Cu, Al, or W, i.e., a metal other than the constituent material of the underlayer 32A or the capping layer 32E described later. Further, it is also possible to make the conductive layer 31 and the conductive layer 33 include Ti, TiN (titanium nitride), Ta, TaN (tantalum nitride), W, Cu, or Al, or a stacked structure thereof.

Fig. 2 shows an example of the configuration of the storage section 32. The memory section 32 has a configuration in which, for example, there are a bottom layer 32A, a magnetization fixed layer 32B, an insulating layer 32C, a memory layer 32D, and a cap layer 32E stacked in ascending order of distance from the conductive layer 31. That is, the memory element 30 has a bottom fixed structure including the magnetization fixed layer 32B, the insulating layer 32C, and the memory layer 32D in order from bottom to top in the stacking direction. Information is stored by changing the orientation of the magnetization M32D of the storage layer 32D using uniaxial anisotropy. The information "0" or "1" is defined by the relative angle (parallel or antiparallel) between the magnetization M32D of the storage layer 32D and the magnetization M32B of the magnetization fixed layer 32B.

The underlayer 32A and the capping layer 32E include a metal film such as Ta or Ru, or a stacked film thereof.

The magnetization pinned layer 32B is a reference layer serving as a reference (magnetization direction) of stored information of the storage layer 32D, and includes a ferromagnetic substance having a magnetic moment that fixes the direction of the magnetization M32B in a direction perpendicular to the film surface. For example, the magnetization pinned layer 32B includes Co-Fe-B.

It is desirable to change the direction of the magnetization M32B of the magnetization pinned layer 32B by reading and writing, however, it is not always necessary to be pinned in a specified direction. One of the reasons for this is that the direction of the magnetization M32B of the magnetization pinned layer 32B needs to be changed only less likely than the direction of the magnetization M32D of the storage layer 32D. For example, the magnetization pinned layer 32B only needs to have a higher coercive force and a larger magnetic film thickness or have a larger magnetic damping constant than the memory layer 32D. In order to fix the direction of the magnetization M32B, for example, it is sufficient to dispose an antiferromagnetic substance such as PtMn or IrMn in contact with the magnetization fixing layer 32B. Alternatively, the direction of the magnetization M32B may be directly fixed by magnetically coupling a magnetic substance in contact with the antiferromagnetic substance and the magnetization fixed layer 32B through a nonmagnetic substance such as Ru.

The insulating layer 32C is an intermediate layer serving as a tunnel barrier layer (tunnel insulating layer) and includes, for example, alumina or magnesium oxide (MgO). Among them, the insulating layer 32C preferably includes magnesium oxide. This enables the magnetoresistance change rate (MR ratio) to be increased and the efficiency of spin injection to be improved, thereby making it possible to reduce the current density for reversing the orientation of the magnetization M32D of the storage layer 32D.

The storage layer 32D includes a ferromagnetic substance having a magnetic moment that allows the direction of the magnetization M32D to be freely changed to a direction perpendicular to the film surface. For example, the storage layer 32D includes Co-Fe-B.

Fig. 3 shows an example of the configuration of the respective layers in the storage section 32 in more detail. The underlayer 32A has a configuration in which, for example, there are a Ta layer having a thickness of 3nm and a Ru film having a thickness of 25nm stacked in ascending order of distance from the conductive layer 31. The magnetization pinned layer 32B has a configuration in which, for example, there are a Pt layer having a thickness of 5nm, a Co layer having a thickness of 1.1nm, a Ru layer having a thickness of 0.8nm, and a (Co20Fe80)80B20 layer having a thickness of 1nm stacked in ascending order of distance from the conductive layer 31. The insulating layer 32C has a configuration in which, for example, there are a Mg layer having a thickness of 0.15nm, a MgO layer having a thickness of 1nm, and a Mg layer having a thickness of 0.15nm stacked in ascending order of distance from the conductive layer 31. For example, the memory layer 32D has a thickness t of 1.2 to 1.7nm and includes a (Co20Fe80)80B20 layer. The cap layer 32E has a configuration in which, for example, there are a Ta layer having a thickness of 1nm, a Ru layer having a thickness of 5nm, and a Ta layer having a thickness of 3nm stacked in ascending order of distance from the conductive layer 31.

The semiconductor device 1 further comprises a controller CTRL (fig. 3). The controller CTRL controls the potentials of each of the select line SL1, the select line SL2, the bit line BL1, the bit line BL2, and the word line WL.

[ operation of semiconductor device 1 ]

In the semiconductor apparatus 1, information is written in the storage layer 32D of the storage element 30A and the storage layer 32D of the storage element 30B in accordance with the order of magnitude relationship among the respective potentials of the select line SL1, the select line SL2, the bit line BL1, the bit line BL2, and the word line WL. The potentials of the respective lines of the select line SL1, the select line SL2, the bit line BL1, the bit line BL2, and the word line WL are controlled by the controller CTRL (fig. 3).

Specifically, for example, as shown in fig. 4A, the controller CTRL sets the potential of the bit line BL1 to a first potential (e.g., low), and sets the potential of the select line SL1 to a second potential (high) higher than the first potential. This makes the electron e^-Flows in the direction of the arrow, and thereby writes the first information "1" in the storage layer 32D of the storage element 30A. At this time, the controller CTRL sets the potential of the gate potential 21 (i.e., the word line WL) to the second potential, and keeps the potential of the bit line BL2 and the potential of the select line SL2 at the third potential irrespective of the potential of the bit line BL1, the potential of the select line SL1, and the potential of the word line WL. That is, the controller CTRL brings the potential of the bit line BL2 and the potential of the select line SL2 into a floating state. The controller CTRL may cause a high-impedance circuit (Hi-Z circuit) included therein to apply a potential to the bit line BL2 and select the lineThe potential of SL2 performs floating control.

For example, as shown in fig. 4B, the controller CTRL sets the potential of the bit line BL1 to the second potential and the potential of the select line SL1 to the first potential. This makes the electron e^-Flows in the direction of the arrow, and thereby writes the second information "0" in the storage layer 32D of the storage element 30A. Further, in this case, the controller CTRL sets the potential of the gate electrode 21 (i.e., the word line WL) to the second potential, and maintains the potential of the bit line BL2 and the potential of the select line SL2 at the third potential irrespective of the potential of the bit line BL1, the potential of the select line SL1, and the potential of the word line WL. That is, the controller CTRL causes the potential of the bit line BL2 and the potential of the select line SL2 to enter a floating state.

For example, as shown in fig. 4C, the controller CTRL sets the potential of the bit line BL2 to a first potential and sets the potential of the select line SL2 to a second potential. This makes the electron e^-Flows in the direction of the arrow, and thereby first information "1" is written in the storage layer 32D of the storage element 30B. In this case, the potential of the gate potential 21 (i.e., the word line WL) is set to the second potential, and the potential of the bit line BL1 and the potential of the select line SL1 are held at the fourth potential irrespective of the potential of the bit line BL2, the potential of the select line SL2, and the potential of the word line WL. That is, the controller CTRL maintains the potential of the bit line BL1 and the potential of the select line SL1 in a floating state.

For example, as shown in fig. 4D, the controller CTRL sets the potential of the bit line BL2 to the second potential, and sets the potential of the select line SL2 to the first potential. This makes the electron e^-Flows in the arrow direction, and thereby second information "0" is written in the storage layer 32D of the storage element 30B. Further, in this case, the potential of the gate electrode 21 (i.e., the word line WL) is set to the second potential, and the potential of the bit line BL1 and the potential of the select line SL1 are held at the fourth potential. That is, the controller CTRL maintains the potential of the bit line BL1 and the potential of the select line SL1 in a floating state.

Depending on the order of magnitude relationship among the respective potentials of the select line SL1, the select line SL2, the bit line BL1, the bit line BL2, and the word line WL, a current is applied in a direction perpendicular to the film surface of the memory section 32, which causes the spin torque magnetization to be inverted. Thus, writing of information is performed by making the orientation of the magnetization M32D of the storage layer 32D parallel or antiparallel to the magnetization M32B of the magnetization fixed layer 32B and thereby changing the resistance value of the storage section 32 to be high or low.

Meanwhile, providing a magnetic layer (not shown) serving as an information reference on the storage layer 32D with a thin insulating film interposed therebetween and using a ferromagnetic tunnel current flowing via the insulating layer 32C makes it possible to read out information stored in the storage portion 32. Further, reading can also be performed by using the magnetoresistance effect.

[ action and Effect of semiconductor device 1 ]

In the semiconductor device 1, the storage element 30A is coupled to the source region of the transistor 20, and the storage element 30B is coupled to the drain region of the transistor 20. Thus, the area occupied by the entire semiconductor device 1 is smaller than in the case where the storage element 30A and the storage element 30B are coupled to, for example, the source region. For example, in the semiconductor device 1001 as a reference example shown in fig. 8A and 8B, two storage elements 1030A and 1030B located at the same level are coupled to a source region. In this case, a larger element region R1001 is required. Note that fig. 8A is a cross-sectional view showing a configuration example of a semiconductor device 1001 as a reference example. And fig. 8B shows a planar configuration example of the semiconductor device 1001. Fig. 8A corresponds to a cross section along section lines VIIIA-VIIIA shown in fig. 8B, as viewed from the direction of the arrows.

In contrast, according to the semiconductor device 1 of this embodiment mode, the transistor 20 and the memory elements 30A and 30B can be compactly provided in the narrow element region R1. This makes it possible to accommodate more transistors 20 and more memory elements 30A and 30B in a limited area of the semiconductor device 1 as a whole, thereby achieving higher integration. Further, it becomes possible to achieve redundancy if, for example, reading and writing are performed using the storage element 30A at a normal time, and reading and writing are performed using the storage element 30B in the event of any abnormality of the storage element 30A. That is, the operational reliability of the semiconductor apparatus 1 can be improved. Moreover, in the semiconductor apparatus 1 of the present embodiment, the memory elements 30A and 30B are provided on the back surface 10B side of the semiconductor substrate 10, and therefore it is possible to prevent the memory elements 30A and 30B from being affected by heat generated in the process of producing the transistor 20 or the wiring layer, for example.

<2 > second embodiment

[ configuration of semiconductor device 2]

Fig. 5A shows a cross-sectional configuration of a semiconductor device 2 as a second embodiment of the present disclosure. Further, fig. 5B and 5C show a planar configuration of the semiconductor device 2. Note that fig. 5B shows a planar configuration of the semiconductor device 2 viewed from the main surface 10A side of the semiconductor substrate 10, and fig. 5C shows a planar configuration of the semiconductor device 2 viewed from the back surface 10B side of the semiconductor substrate 10. Fig. 5A corresponds to a cross-sectional view along the sectional line VA-VA shown in fig. 5B and 5C, as viewed from the arrow direction.

In the semiconductor device 1 of the first embodiment described above, the memory element 30A and the memory element 30B are provided on the back surface 10B side of the semiconductor device 10 opposite to the main surface 10A on which the transistor 20 is provided, with the insulating layer 60 interposed between the semiconductor substrate 10 and the memory elements 30A and 30B. In contrast, in the semiconductor device 2 according to the present embodiment, the memory element 30A and the memory element 30B are provided on the side of the main surface 10A of the semiconductor substrate 10 on which the transistor 20 is provided. In the following description and fig. 5, parts corresponding to those of the semiconductor apparatus 1 according to the above-described first embodiment will be denoted by the same reference numerals.

In comparison with the semiconductor device 1, in the semiconductor device 2 of the present embodiment, the respective positions where the memory element 30A and the select line SL2 are provided are interchanged, and the respective positions where the memory element 30B and the select line SL1 are provided are interchanged. Specifically, the selection line SL2 and the selection line SL1 are disposed on the upper surface 60S of the insulating layer 60, the lower surface of the selection line SL2 is in contact with the contact plug P1, and the lower surface of the selection line SL1 is in contact with the contact plug P2. Meanwhile, the memory element 30A and the memory element 30B are embedded in the interlayer insulating layer 27, the memory element 30A is in contact with the lower surface of the connection layer 28A, and the memory element 30B is in contact with the lower surface of the connection layer 28B. Further, in the semiconductor device 2, the bit line BL1 is provided in the wiring line group 40A of the semiconductor device 1 in place of the metal layer M4, and the bit line BL2 is provided in the wiring line group 40B of the semiconductor device 1 in place of the metal layer M4. That is, the bit line BL1 and the bit line BL2 are provided on the support substrate 50, and the upper surfaces thereof are in contact with the lower surface of the via V4 and embedded in the interlayer insulating layer 44.

[ action and Effect of semiconductor device 2]

Further, in this semiconductor device 2, effects similar to those of the semiconductor device 1 according to the first embodiment described above are obtained. That is, in the semiconductor device 2, the storage element 30A is coupled to the source region of the transistor 20, and the storage element 30B is coupled to the drain region of the transistor 20. Thus, for example, the area occupied by the entire semiconductor device 2 is smaller than in the case where the storage element 30A and the storage element 30B are coupled to the source region, which makes it possible to accommodate more transistors 20 and more storage elements 30A and 30B in a narrower region, thereby enabling higher integration. Further, in the semiconductor device 2, the memory element 30A and the memory element 30B are disposed on the side of the main surface 10A on which the transistor 20 is disposed, and therefore, it is sufficient that only the contact plugs P1 and P2 and wiring lines such as the selection lines SL1 and SL2 are disposed on the rear surface 10B side. That is, the forming process on the back surface 10B side can be simplified. Further, in the semiconductor device 2, the memory element 30A and the memory element 30B are embedded in the interlayer insulating layer 27 provided with the transistor 20; therefore, as compared with the semiconductor device 1 of the first embodiment described above, it is easier to reduce the overall thickness.

<3 > third embodiment

[ configuration of semiconductor device 3]

Fig. 6A is a perspective view showing the configuration of a semiconductor device 3 as a third embodiment of the present disclosure. Fig. 6B shows the configuration of the semiconductor device 3, and corresponds to a cross section along a section line VIB-VIB shown in fig. 6A, as viewed from the direction of the arrows. The semiconductor device 3 has a similar configuration to the semiconductor device 1, but the semiconductor device 3 includes a transistor 80 instead of the transistor 20. The transistor 80 is embedded in an element formation layer 80A provided between the support substrate 50 and the semiconductor substrate 13 including, for example, silicon. The semiconductor substrate 13 has a front surface 13A facing the element formation layer 80A and a back surface 13B positioned opposite to the front surface 13A. The transistor 80 is provided on the front surface 13A side of the semiconductor substrate 13. The memory elements 30A and 30B are disposed on the back surface 13B side. In the present embodiment, for the sake of description, components similar to those of the semiconductor apparatus 1 according to the first embodiment described above are denoted by the same reference numerals.

For example, the transistor 80 is a fin field effect transistor (fin FET) including: a fin 81 including Si; a gate electrode 82G and a source electrode 82S; and a drain electrode 82D. By using the fin FET, it becomes possible to suppress short channel characteristics as compared with a planar transistor on a bulk substrate. The gate electrode 82G also serves as a word line WL for the storage element 30A and the storage element 30B.

The fin 81 has a flat plate shape and includes a plurality of fins provided standing on a semiconductor substrate 13 including, for example, silicon. For example, the plurality of fins 81 extend in the X-axis direction and are arranged in the Y-axis direction. Note that fig. 6A and 6B show only a single fin 81. For example, a cross section of the fin portion 81 perpendicular to the X-axis direction (i.e., YZ section) has a trapezoidal shape. The gate electrode 82G, the source electrode 82S, and the drain electrode 82D each extend across the fin 81 in the Y-axis direction intersecting the extending direction of the fin 81. The gate electrode 82G, the source electrode 82S, and the drain electrode 82D each cover the surface of the fin 81 except the back surface, that is, the surface of the fin 81 in contact with the semiconductor substrate 13. Here, the upper end of the source electrode 82S is coupled to the select line SL2, and the upper end of the drain electrode 82D is coupled to the select line SL 1. Note that in fig. 6A, illustration of the select line SL1 and the select line SL2 is omitted to prevent complication of the drawings.

Further, the fin 81 includes impurity diffusion regions 83S and 83D serving as a source region and a drain region near the back surface thereof. The impurity diffusion region 83S is coupled to the memory element 30A through the contact plug P1, and the impurity diffusion region 83D is coupled to the memory element 30B through the contact plug P2.

[ action and Effect of semiconductor device 3]

Further, in this semiconductor device 3, effects similar to those of the semiconductor device 1 of the first embodiment described above can be expected.

Further, in the present embodiment, the transistor 80, that is, the fin FET having high current driving capability is mounted, and the transistor 80 is used as a transistor for selecting between the storage element 30A and the storage element 30B. This enables high-speed reading and writing of information.

[ configuration of semiconductor device 3A as a modification ]

Fig. 6C is a cross-sectional view showing the configuration of a semiconductor device 3A as a modification of the present embodiment and corresponds to fig. 6B. In the semiconductor device 3 as the third embodiment shown in fig. 6A and 6B, the memory element 30A and the memory element 30B are provided on the back surface 13B side of the semiconductor substrate 13. In contrast, in the semiconductor device 3A as the present modification example, the memory elements 30A and 30B are provided on the front surface 13A side of the semiconductor substrate 13. Further, in this semiconductor device 3A, effects similar to those of the semiconductor device 3 of the third embodiment described above can be expected.

<4. application example >

Fig. 7A shows a schematic configuration of the imaging apparatus 101 in which the sensor apparatus 100 and the semiconductor apparatus 200 are bonded together. As the semiconductor device 200, the semiconductor devices 1 to 3 of the first to third embodiments described above can be used.

For example, the imaging device 101 is a stacked image sensor device in which the sensor device 100 is stacked on the semiconductor device 200. The pixel portion 110 is formed in the sensor device 100. The semiconductor device 200 is provided with a logic circuit 210 and a memory section 220.

In the pixel section 110 of the sensor device 100, the unit pixels are two-dimensionally arranged and provided with, for example, a backside-illuminated imaging element (imaging element 110S, see fig. 2), a transfer transistor that transfers electric charges obtained by photoelectric conversion of the imaging element 110S to a Floating Diffusion (FD) section, a reset transistor that resets the potential of the FD section, an amplification transistor that outputs a signal corresponding to the potential of the FD section, and the like.

The semiconductor device 200 is provided with a logic circuit 210 such as a control circuit that controls the operation of the imaging element 110S, and nonvolatile memory elements ( memory elements 30A and 30B) included in the memory section 220. It is to be noted that, for example, the semiconductor device 200 may be provided with a circuit having an image processing function, an ADC (analog-digital converter) circuit that converts an analog signal output from a unit pixel provided from a pixel section into a digital signal and outputs the digital signal, or the like, in addition to the logic circuit 210 and the storage section 220.

Fig. 7B illustrates an embodiment of a specific cross-sectional configuration of the imaging apparatus 101 illustrated in fig. 7A. The sensor device 100 in the imaging device 101 is provided with the above-described imaging element 110S. The imaging element 110S is, for example, an element in which a planarization layer 114, a color filter 115, and a microlens 116 are stacked on a semiconductor substrate 113 in this order in such a manner that a photodiode 113A and a transistor 113B are embedded therein. In the sensor apparatus 100, a protective layer 117 is provided on the microlenses 116 of the imaging elements 110S, and a glass substrate 118 is provided on the protective layer 117. Further, the sensor device 100 includes a conductive film 111 containing Cu in the lowermost layer thereof (which faces the surface of the semiconductor device 200), and an insulating layer 112 occupying the periphery of the conductive film 111. The lower surface of the conductive film 111 is coupled to the connection layer P3 provided in the uppermost layer of the semiconductor apparatus 200. For example, the connection layer P3 includes copper or the like, and the insulating layer 73 occupies its periphery.

The imaging device 101 shown in fig. 7A and 7B makes it possible to achieve higher integration because any of the semiconductor devices 1 to 3 of the above-described first to third embodiments is applied as the semiconductor device 200.

The present disclosure has been described above with reference to the embodiments and the like; however, the present disclosure is not limited to the above-described embodiments and may be modified in various ways.

For example, the above embodiments have been described with reference to specific configurations of the transistors 20 and 80 and the memory elements 30A and 30B; however, it need not include all of the components, and may further include other components.

Further, the above-described first embodiment has been described with reference to an example in which the transistor 20 is an NMOS transistor; however, the present disclosure is not limited thereto and, for example, a PMOS transistor is applied. For example, the semiconductor device 1A shown in fig. 9A and 9B includes a PMOS transistor 20A. In this case, for example, as shown in fig. 9A, the potential of the bit line BL1 is set to a first potential (e.g., low), and the potential of the select line SL1 is set to a second potential (high) higher than the first potential. This makes the electron e^-Flows in the direction of the arrow, and second information "0" is written in the storage layer 32D of the storage element 30A. Meanwhile, as shown in fig. 9B, if the potential of the bit line BL1 is set to the second potential and the potential of the select line SL1 is set to the first potential, the electron e^-Flows in the direction of the arrow, and the first information "1" is written in the storage layer 32D of the storage element 30A.

Also, in the above-described embodiments and the like, the memory element having the bottom fixing structure is described; however, the present technology may employ a memory element having a top fixed structure. As used herein, the top fixed structure refers to a structure in which a memory layer, an insulating layer, and a magnetization fixed layer are stacked in this order from bottom to top in the stacking direction. It should be noted that in the case of a storage element having a top fixed structure, its behavior is opposite to that in the case where the storage element has a bottom fixed structure (high and low inversions written into the storage element).

It should be noted that the effects described herein are merely examples and the description thereof is non-limiting. Any other effect can also be achieved. Further, the present technology may have the following configuration.

(1) A semiconductor device, comprising:

a transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

a first conductive portion;

a second conductive portion electrically insulated from the first conductive portion;

a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion.

(2) The semiconductor device according to (1), further comprising:

a third conductive portion, viewed from the first diffusion layer, disposed opposite the first storage element and electrically coupled to the first diffusion layer; and

the fourth conductive portion, viewed from the second diffusion layer, is disposed opposite the second storage element and is electrically coupled to the second diffusion layer.

(3) The semiconductor device according to (1) or (2), wherein the gate portion, the first conductive portion, and the second conductive portion all extend along the first direction.

(4) The semiconductor device according to (2), wherein the gate portion and the first to fourth conductive portions all extend in the first direction.

(5) The semiconductor device according to any one of (1) to (4), further comprising a semiconductor substrate having a first surface on which the gate portion is provided and a second surface positioned opposite to the first surface, wherein,

the first diffusion layer constitutes a portion of the semiconductor substrate near the first surface; and is

The second diffusion layer constitutes another portion of the semiconductor substrate near the first surface.

(6) The semiconductor device according to (5), further comprising:

a first insulating layer covering the second surface of the semiconductor substrate; and

a first connection portion and a second connection portion each penetrating the first insulating layer; wherein the content of the first and second substances,

the first storage element and the second storage element are each disposed opposite to the second surface, as viewed from the first insulating layer;

the first memory element is electrically coupled to the first diffusion layer through the first connection portion; and is

The second memory element is electrically coupled to the second diffusion layer through a second connection portion.

(7) The semiconductor device according to (6), further comprising:

a second insulating layer covering the first surface of the semiconductor substrate;

a third conductive portion and a fourth conductive portion each disposed opposite to the second surface as viewed from the second insulating layer;

a third connection portion penetrating the second insulating layer and electrically coupling the first diffusion layer and the third conductive portion to each other; and

a fourth connection portion penetrating the second insulating layer and electrically coupling the second diffusion layer and the fourth conductive portion to each other.

(8) The semiconductor device according to (7), further comprising a controller that performs the following control:

setting an electric potential of the first conductive portion to a first electric potential, setting an electric potential of the fourth conductive portion to a second electric potential higher than the first electric potential, setting an electric potential of the gate portion to the second electric potential, and setting an electric potential of the second conductive portion and an electric potential of the third conductive portion to a third electric potential independent of all of the electric potential of the first conductive portion, the electric potential of the fourth conductive portion, and the electric potential of the gate portion, thereby writing first information in the first memory element; and is

The potential of the first conductive portion is set to a second potential, the potential of the fourth conductive portion is set to a first potential, the potential of the gate portion is set to a second potential, and the potential of the second conductive portion and the potential of the third conductive portion are set to a third potential, thereby writing second information in the first memory element.

(9) The semiconductor device according to (8), wherein the controller includes a potential control circuit capable of maintaining the potential of the second conductive part and the potential of the third conductive part at a third potential.

(10) The semiconductor device according to (7), further comprising a controller that performs the following control:

setting an electric potential of the second conductive portion to a first electric potential, setting an electric potential of the third conductive portion to a second electric potential higher than the first electric potential, setting an electric potential of the gate portion to the second electric potential, and setting an electric potential of the first conductive portion and an electric potential of the fourth conductive portion to a fourth electric potential independent of all of the electric potential of the second conductive portion, the electric potential of the third conductive portion, and the electric potential of the gate portion, thereby writing first information in the second memory element; and is

Setting the potential of the second conductive portion to a second potential, setting the potential of the third conductive portion to a first potential, setting the potential of the gate portion to a second potential, and setting the potential of the first conductive portion and the potential of the fourth conductive portion to a fourth potential, thereby writing second information in the second memory element.

(11) The semiconductor device according to (10), wherein the controller includes a potential control circuit capable of maintaining the potential of the first conductive part and the potential of the fourth conductive part at a fourth potential.

(12) The semiconductor device according to any one of (5) to (11), further comprising:

a first insulating layer covering the first surface of the semiconductor substrate;

a first connection portion and a second connection portion each penetrating the first insulating layer;

a third conductive portion that is provided opposite to the first surface as viewed from the first insulating layer and is electrically coupled to the first diffusion layer through the first connection portion; and

a fourth conductive portion, viewed from the first insulating layer, disposed opposite the first surface and electrically coupled to the second diffusion layer through the second connection portion.

(13) The semiconductor device according to (12), further comprising:

a second insulating layer covering the second surface of the semiconductor substrate; and

a third connection portion and a fourth connection portion each penetrating the second insulating layer; wherein the content of the first and second substances,

a first conductive portion provided opposite to the second insulating layer and electrically coupled to the first diffusion layer through a third connection portion, as viewed from the first memory element; and is

The second conductive portion is disposed opposite to the second insulating layer and electrically coupled to the second diffusion layer through a fourth connection portion, as viewed from the second memory element.

(14) The semiconductor device of (1), further comprising a fin comprising a semiconductor material and extending in a second direction that intersects the first direction, wherein,

the first storage element and the second storage element are each coupled to the back surface of the fin; and is

The gate portion, the first diffusion layer, and the second diffusion layer extend in the first direction and cover surfaces other than the back surface of the fin portion.

(15) An image forming apparatus comprising:

a semiconductor device; and

an imaging element stacked on the semiconductor device;

the semiconductor device includes:

a transistor including a gate portion, a first diffusion layer, and a second diffusion layer;

a first conductive portion;

a second conductive portion electrically insulated from the first conductive portion;

a first storage element located between the first diffusion layer and the first conductive portion and electrically coupled to each of the first diffusion layer and the first conductive portion; and

a second storage element located between the second diffusion layer and the second conductive portion and electrically coupled to each of the second diffusion layer and the second conductive portion.

The present application claims priority from japanese patent application JP2018-39217, filed on 6.3.2018 to the japanese patent office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various alterations, combinations, sub-combinations, and modifications may be made according to design requirements and other factors insofar as they come within the scope of the appended claims or the equivalents thereof.