Three-dimensional memory device
阅读说明：本技术 三维存储器器件 (Three-dimensional memory device ) 是由 F·D·菲什伯恩 C·L·英戈尔斯 于 2019-02-22 设计创作，主要内容包括：使用三维存储器器件的系统和方法可用于各种应用中,所述三维存储器器件具有垂直地设置在沿水平方向布置的多个柱中的多个存储器单元。在各种实施例中,存储器单元的柱可设置在分别耦合到不同的读出放大器的下数字线与上数字线之间,以提供读取/写入操作和刷新操作。在各种实施例中,具有垂直地布置在柱中的存储器单元的阵列的三维存储器器件可包含读出放大器和具有静态随机存取存储器高速缓存的数字线,其中静态随机存取存储器高速缓存设置在同一管芯中的存储器单元的阵列下方。公开了附加的设备、系统和方法。(Systems and methods using a three-dimensional memory device having a plurality of memory cells vertically disposed in a plurality of pillars arranged in a horizontal direction may be used in various applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digit lines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and a digit line having a static random access memory cache disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.)
1. A memory device, comprising:
an array of memory cells, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked therein, a plurality of the pillars being arranged in a horizontal direction;
a first digit line disposed below the array, the first digit line coupled to each of the pillars in the horizontal direction through a respective first select device;
a second digit line over the array, the second digit line coupled to each of the pillars in the horizontal direction through a respective second select device;
a first sense amplifier coupled to the first digit line;
a second sense amplifier coupled to the second digit line; and
an input/output circuit coupled to the first sense amplifier or the second sense amplifier.
2. The memory device of claim 1, wherein the memory device includes control circuitry to access a first memory cell in one of the pillars in the horizontal direction via an access line coupled to the first memory cell and via one of the first digit line or the second digit line coupled to the one pillar, and to access a second memory cell in another of the pillars in the horizontal direction via an access line coupled to the second memory cell and via the other of the first digit line or the second digit line.
3. The memory device of claim 2, wherein the control circuitry is operable to control access to the first memory cell and access to the second memory cell in overlapping time intervals.
4. The memory device of claim 1, wherein each of the memory cells in each pillar is a dynamic random access memory cell coupled to a pillar digit line of the respective pillar, the pillar digit line coupled to the respective first select device and the respective second select device of the respective pillar.
5. The memory device of claim 1, wherein the memory device includes a static random access memory configured to store bits of memory cells from each of a selected number of the pillars along the horizontal direction, the static random access memory integrated in a die with the array of memory cells.
6. The memory device of claim 5, wherein the static random access memory is configured to be located below the array of memory cells.
7. The memory device of claim 6, wherein the memory device includes a processor disposed in the die below the array of memory cells to control the static random access memory.
8. The memory device of claim 1, wherein the memory device includes a second input/output circuit coupled to the first sense amplifier or the second sense amplifier not coupled to the input/output circuit.
9. A memory device, comprising:
an array of memory cells in a die, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked therein, a plurality of the pillars being arranged in a horizontal direction;
a digit line disposed below or above the array, the digit line coupled to each of the pillars in the horizontal direction by a respective select device coupled to a pillar word line of a respective pillar;
a static random access memory cache integrated in the die with and disposed below the array of memory cells;
a sense amplifier coupled to the digit line; and
an input/output circuit coupled to the sense amplifier.
10. The memory device of claim 9, wherein the memory device is arranged to read data from the array into the sram cache and write the data back to the array.
11. The memory device of claim 10, wherein the memory device reads the data from the array into the static random access memory cache at a rate of approximately 10 gigabits/second and writes the data back to the array at intervals of about 5 gigabits/second to about 10 gigabits/second.
12. The memory device of claim 9, wherein the array shares the digit line and the sense amplifier with the sram cache.
13. The memory device of claim 9, wherein the memory device includes a processor disposed in the die below the array of memory cells to control the static random access memory.
14. A method, comprising:
writing data to or reading data from memory cells in an array of memory cells using a first digit line coupled to a first sense amplifier, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked in a respective pillar, a plurality of the pillars being arranged in a horizontal direction; and
refreshing memory cells in a different pillar than a pillar containing memory cells to write or read data using a second digit line coupled to a second sense amplifier, wherein one of the first digit line and the second digit line is disposed below the array and the other of the first digit line and the second digit line is disposed above the array.
15. The method of claim 14, wherein the method includes continuously refreshing memory cells in a pillar that is different from a pillar in which data is being read from or written to memory cells.
16. The method of claim 14, wherein writing or reading data comprises reading one or more bits from one or more pillars of the array into a static random access memory disposed below the array of memory cells.
17. The method of claim 14, wherein the method includes storing a new cache page into a static random access memory cache disposed below the array of memory cells and storing an existing page stored in the static random access memory cache back to the array prior to loading the new page into the static random access memory cache.
18. A method, comprising:
writing or reading data into a static random access memory cache integrated with and disposed below an array of memory cells in a die of a memory device, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked in the pillar, a plurality of the pillars being arranged in a horizontal direction, wherein the static random access memory cache shares a digit line with the array and a sense amplifier coupled to the digit line for a storage operation.
19. The method of claim 18, wherein the method includes outputting data from the sram cache through the sense amplifier to input/output circuitry to transfer the data out of the memory device.
20. The method of claim 18, wherein the method includes storing a new cache page into the static random access memory cache and storing an existing page stored in the static random access memory cache back to the array prior to loading the new page into the static random access memory cache.
Background
The electronics industry is constantly under pressure to reduce component size and power requirements, and the market needs to improve the operation of memory devices. One approach to reducing component size is to fabricate the device in a three-dimensional (3D) configuration. 3D memory technology using pillar access devices and other methods is being developed in the memory industry. The use of 3D technology enables higher density of memory array cores of memory devices having vertically arranged memory cells. For example, memory devices such as Dynamic Random Access Memories (DRAMs) may be arranged as vertically stacked memory cells on a substrate. Since the memory array cores of the DRAM are arranged in a vertical stack for die size scaling and cost savings, the number of sense amps (sense amps) is not increased. This lack of sense amplifiers for the vertical arrangement will impair the refresh performance of the memory cells of the memory array. Access to the vertical array core is limited because standard sense amplifiers serve multiple vertical array cores. In essence, the sense amplifiers of the DRAM are being weakened. Improvements to 3D memory can be addressed by advances in memory device design.
Drawings
Figure 1 is an illustration of features of an exemplary three-dimensional dynamic random access memory including an array of memory cells arranged in a plurality of vertical pillars in a horizontal direction, in accordance with various embodiments.
Figure 2 is an illustration of features of an example three-dimensional dynamic random access memory including an array of memory cells arranged in a plurality of vertical pillars in a horizontal direction, in accordance with various embodiments.
Figure 3 is an illustration of features of an example three-dimensional dynamic random access memory including an array of memory cells arranged in a plurality of vertical pillars in a horizontal direction, in accordance with various embodiments.
Figure 4 is an illustration of features of an example three-dimensional dynamic random access memory including an array of memory cells arranged in a plurality of vertical pillars in a horizontal direction, in accordance with various embodiments.
Figure 5 is an illustration of features of an example three-dimensional dynamic random access memory including an array of memory cells arranged in a plurality of vertical pillars in a horizontal direction, in accordance with various embodiments.
FIG. 6A is a schematic diagram of an exemplary two-dimensional portion of a three-dimensional dynamic random access memory, in accordance with various embodiments.
FIG. 6B is a circuit diagram of an exemplary three-dimensional dynamic random access memory, in accordance with various embodiments.
FIG. 6C illustrates an example of memory operations of an exemplary three-dimensional dynamic random access memory, in accordance with various embodiments.
Fig. 7 is an illustration of features of an example three-dimensional dynamic random access memory arranged in multiple horizontal levels along a vertical direction, in accordance with various embodiments.
FIG. 8 is a flow diagram of an exemplary method of accessing a memory cell of a memory device, in accordance with various embodiments.
Fig. 9 is a flow diagram of an exemplary method of operating a three-dimensional memory device, in accordance with various embodiments.
Figure 10 is a block diagram of features of a dynamic random access memory in which a three-dimensional structure and associated structures of pillars of memory cells may be constructed, in accordance with various embodiments.
Figure 11 illustrates an example of a wafer arranged to provide a plurality of electronic components including a memory device having a three-dimensional architecture, in accordance with various embodiments.
FIG. 12 illustrates a block diagram of a system including a memory configured as a three-dimensional memory device, in accordance with various embodiments.
Detailed Description
The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments of the present invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized and structural, logical, mechanical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.
In various embodiments, additional sets of sense amplifiers may be implemented in the 3D DRAM to service the increase in vertical array stacks relative to conventional architectures. Constructing additional sets of sense amplifiers with their own stack array core access paths can solve the problem of weakened sense amplifiers and improve array performance. The first set of sense amplifiers may service customer requirements regarding access to memory cells of the memory array for read and write operations, and the second set may service refresh parameters of the memory cells. As the design of DRAM array stacks increases, the importance of additional sense amplifiers will also increase. In such an architecture, while serving the DRAM stack internally, a user, such as an external processor, may access the DRAM stack or refresh other vertical DRAM stacks, as taught herein.
In addition to adding a second set of sense amplifiers, a multiplexing (mux) device may be implemented to select which set of sense amplifiers to use for each array core level. For a multiplexing device, ping-pong logic may be used. In ping-pong logic techniques, a second sense amplifier may prefetch data while a first sense amplifier is driving out the data. Thus, once the first sense amplifier finishes driving out the data, it can jump to the second sense amplifier, which will start sending out the data, and the first sense amplifier can start reloading. Thus, in essence, the process jumps between the two sense amplifiers as a ping-pong ball. In addition to the first set of sense amplifiers coupled to input/output (I/O) interfaces, the second set of sense amplifiers may also have a different I/O interface associated with the second set. As taught herein, a structure with a second set of sense amplifiers may increase array accessibility and refresh performance, as well as reduce refresh time intervals. Two sense amplifiers, each of which may be connected to a different segment in the memory array hierarchy, may be implemented to enable simultaneous access to different portions of the memory array.
For a first set of sense amplifiers in a DRAM architecture, a first set of select devices may be coupled to a lower digit line connected to the first set of sense amplifiers. The digit lines may also be referred to as data lines. An example of a data line in a memory device is a bit line. For a second set of sense amplifiers in the DRAM architecture, a second set of select devices may be coupled to the upper digit lines connected to the second set of sense amplifiers. The vertical digital line segments may be connected to the first sense amplifier from the bottom of the vertical pillars and/or to the second sense amplifier from the top of the dummy pillars. The first and second sets of select devices are Isolation (ISO) devices that may isolate the vertical digit line segments from the lower and upper digit lines, respectively.
To achieve lower cost, higher density and scalable 3D DRAM, thin film access devices may be used. The leakage of such devices may be 10 to 100 times that of single crystal silicon (Si). Frequent refreshes may be used and this may affect the overhead of outputting data. Furthermore, in a hierarchical digitline with 16K bits per sense amplifier, this arrangement may further increase the overhead of refreshing the memory array. For the second set of digit lines/sense amplifiers, the memory cells of the die may be refreshed continuously, if appropriate, while other memory cells of the die may be used for reading/writing. This refreshing may be 50 times higher than currently practiced in conventional systems having main memory with 16 kbits per sense amplifier, and one hundred times higher than the frequency of 8 kbits per sense amplifier, and so on. The arrangement with the second set of digit lines/sense amplifiers may also be used for independent data streams with the second set of I/os and data paths.
In various embodiments, the 3D DRAM may include a hierarchical data line architecture with a built-in Static Random Access Memory (SRAM) cache under the memory array of the 3D DRAM. A built-in SRAM cache may be implemented to achieve high bandwidth, eliminating the need for on-chip process-level (L3) cache. The L3 cache is a cache that works with level one (L1) cache and level two (L2) cache to improve performance by preventing bottlenecks due to too long fetch and execution cycles. The L3 cache feeds information into the L2 cache, the L2 cache then forwards the information to the L1 cache. In general, the memory performance of the L3 cache is slower than the L2 cache, but still faster than main memory (RAM).
In various embodiments, data may be read from the 3D DRAM into the underlying SRAM in the same die, and data may be written back to the 3D DRAM. For example, data may be read from 3D DRAM to the underlying SRAM at a speed of 10 gbits/sec, data may be written back to 3D DRAM at a speed of 5-10 gbits/sec, with a read period of 20ns and a write period of 40 ns. SRAM data may be output through the sense amplifiers and I/0 interface of the 3D DRAM. The underlying SRAM may be implemented under the memory array of the 3D DRAM in "free" space in the die under the memory array. The DRAM and associated SRAM may share data lines and sense amplifiers.
FIG. 1 is a graphical representation of features of an embodiment of an exemplary three-dimensional DRAM100, the three-dimensional DRAM100 comprising an array 103 of memory cells arranged in a horizontal direction in a plurality of vertical pillars 115-0, 115-1, 115-2, 115-3 … … 115, 115-127, 115-125, 115-126, and 115-127. Memory cells are vertically stacked in each of these pillars, with each memory cell (such as a DRAM cell) in a respective pillar coupled to a pillar number word line in the respective pillar. A pillar digit line is a digit line in and extending along a pillar of a DRAM cell coupled with the corresponding pillar. Although in fig. 1 128 columns are indicated in the horizontal direction x, more or less than 128 columns may be implemented. Although eleven DRAM cells are shown in each column in the vertical direction z, more or less than eleven DRAM cells may be implemented. For example, DRAM100 may include, but is not limited to, 128 DRAM cells in each of 128 pillars per digit line in the horizontal direction. The DRAM cells at each vertical level in the pillar are part of a layer, with a DRAM having 128 DRAM cells in each pillar having 128 layers. Along the y-direction, the pillars of stacked memory cells may be configured along the x-direction.
DRAM100 may include a first digit line 110-1, first digit line 110-1 being a conductive structure disposed in the x-direction below array 103 with respect to the z-direction. The first digit line 110-1 may be coupled to each of the pillars 115-0, 115-1, 115-2, 115-3 … … 115, 115-126, and 115-127 in the horizontal direction through first select devices 125-1-0, 125-1-1, 125-1-2, 125-1-3 … … 125-1-124, 125-1-125, 125-1-126, and 125-1-127, respectively. These select devices are lower select devices in the z-direction of the 3D structure and may be implemented by transistors. The DRAM100 may include a second digit line 110-2, the second digit line 110-2 being a conductive structure disposed in the x-direction over the array 103 relative to the z-direction. The second digit line 110-2 may be coupled to each of the pillars 115-0, 115-1, 115-2, 115-3 … … 115-2-124, 115-125, 115-126, and 115-127 in the horizontal direction through the second select devices 125-2-0, 125-2-1, 125-2-2, 125-2-3 … … 125-2-124, 125-2-125, 125-2-126, and 125-2-127, respectively. These select devices are the upper select devices in the z-direction of the 3D structure and may be implemented by transistors.
The first sense amplifier 105-1 may be coupled to the first digit line 110-1 through a via 127-1. The second sense amplifier 105-2 may be coupled to the second digit line 110-2 through a via 127-2. Although an I/O circuit is shown in FIG. 1 coupled to the first sense amplifier 105-1, an I/O circuit 120 is coupled to either the first sense amplifier 105-1 or the second sense amplifier 105-2. I/O circuitry 120 may be coupled to provide data to data out path 129 using via 128. In an embodiment, a first sense amplifier 105-1 coupled to I/O120 (which is coupled to data out path 129) may be used for read and write operations to array 103 with respect to a host device such as a host processor, and a second sense amplifier 105-2 may be used with internal control circuitry to refresh memory cells of array 103. In this arrangement, the host processor may operate with little or no refresh impact. Control circuitry separate from the host processor may be operated to control the refresh of the memory cells so that host operations on memory cells that are not refreshed may be performed within a time interval that overlaps with the refresh, which may reduce overhead. In addition, cells in different pillars can be refreshed in parallel by the two sets of select devices, two digit lines, and two sense amplifiers.
Consider the following non-limiting example in which DRAM cell 117 in column 132 of DRAM cells in column 115-3 may be selected to read from or write to DRAM cell 117. The DRAM cells in column 134 of DRAM cells in columns 115 and 125 may be selected to be refreshed. Upper select devices 125-2-124 may be selected for refresh and lower select devices 125-1-3 may be selected for read or write operations. Selection of upper select device 125-2-124 causes sequential row addressing in column 134 for refresh (e.g., vertically down as indicated by the arrow) to connect to second sense amplifier 105-2 through digital line 120-2 and via 127-2. Selection of lower select device 125-1-3 enables reading from or writing to memory cell 117 from sense amplifier 105-1 using via 127-1 and digit line 110-1.
With the upper select device and the second digit line 110-2 on top of the array 103 coupled to the second sense amplifier 105-2, the cells on different pillars can be refreshed in parallel. Considering 2.5 mus to extract bits from the pillars is a limit on how long it will take to refresh the entire array 103 of memory dies. It is assumed that in the worst case, an external user (e.g., a host processor) can only access several columns in succession. In the 128-pillar example, it would take 2.5 μ s x 128 pillars 0.32ms to refresh all bits on all 128 pillars. For a DRAM cell, a 0.3V drop may take.3 milliseconds with a cell capacitance of 5fF and an access device leakage of less than 25 pA. Since the refresh is one hundred times worse, the array 103 can still remain refreshed, transparent to the operation of the die. Refresh may not be a problem because all bits on a column may be refreshed within 2.5 microseconds, otherwise the digital line segment (column digital line) is in an equilibrium state (EQ). Since 128 pillars are coupled to the sense amplifiers by digit lines and 128 bits per pillar, there may be 128 pillars x 128 bits per pillar — 16K bits per sense amplifier. For two sense amplifiers and two digit lines, each sense amplifier has 8K bits. At this level, the digit line capacitance of such 3D DRAMs is about 1/2 for planar DRAMs.
FIG. 2 is an illustration of features of an embodiment of an exemplary three-
The first sense amplifier 205-1 may be coupled to the first digit line 210-1 through a via 227-1. The second sense amplifier 205-2 may be coupled to the second digit line 210-2 through a via 227-2. Both the first sense amplifier 205-1 and the second sense amplifier 205-2 may be coupled to a multiplexer (mux)222, the
The
FIG. 3 is an illustration of features of an embodiment of an exemplary three-dimensional DRAM 300, the three-dimensional DRAM 300 comprising an array 303 of memory cells arranged in a horizontal direction in a plurality of vertical pillars 315-0, 315-1, 315-2, 315-3 … … 315, 126, and 315, 127. Memory cells are vertically stacked in each of these pillars, with each memory cell (such as a DRAM cell) in a respective pillar coupled to a pillar number word line in the respective pillar. Although 128 columns are indicated in the horizontal direction x, more or less than 128 columns may be implemented. Although eleven DRAM cells are shown in each column in the vertical direction z, more or less than eleven DRAM cells may be implemented. For example, DRAM 300 may include, but is not limited to, 128 DRAM cells in each of 128 pillars per digit line in the horizontal direction, which provides a DRAM having 128 layers. Along the y-direction, the pillars of stacked memory cells may be configured along the x-direction. Various features of DRAM 300 may be implemented similar to features of DRAM100 of figure 1 and/or
DRAM 300 may include a first digit line 310-1, first digit line 310-1 being a conductive structure disposed in the x-direction below array 303 with respect to the z-direction. The first digit line 310-1 may be coupled in a horizontal direction to each of the pillars 315-0, 315-1, 315-2, 315-3 … … 315, 315-125, 315-126, 315-127 through the first select devices 325-1-0, 325-1-2, 325-1-3 … … 325-1-124, 325-1-125, 325-1-126, and 325-1-127, respectively. These select devices are lower select devices in the z-direction of the 3D structure and may be implemented by transistors. The DRAM 300 may include a second digit line 310-2, the second digit line 310-2 being a conductive structure disposed in the z-direction above the array 303 in the x-direction. The second digit line 310-2 may be coupled to each of the pillars 315-0, 315-1, 315-2, 315-3 … … 315, 315-125, 315-126, 315-127, through the second select devices 325-2-0, 325-2-1, 325-2-2, 325-2-3 … … 325-2-124, 325-2-125, 325-2-126, and 325-2-127, respectively, in the horizontal direction. These select devices are the upper select devices in the z-direction of the 3D structure and may be implemented by transistors.
First sense amplifier 305-1 may be coupled to first digit line 310-1 through via 327-1. A first sense amplifier 305-1 may be coupled to I/O circuit 320-1 to provide data to data output path 329-1, I/O circuit 320-1 being coupled to via 328-1. The second sense amplifier 305-2 may be coupled to the second digit line 310-2 through a via 327-2. A second sense amplifier 305-2 may be coupled to the I/O circuit 320-2 to provide data to the data output path 329-2, the I/O circuit 320-2 being coupled to the via 328-2. Both the first sense amplifier 305-1 and the second sense amplifier 305-2 may be coupled to the control circuit 323, which allows both the first sense amplifier 305-1 and the second sense amplifier 305-2 to be used to access memory cells of the array 303 for read or write operations, and to refresh memory cells of the array 303. Although the control circuit 323 is shown in FIG. 3 as being located between the first sense amplifier 305-1 and the second sense amplifier 305-2, other arrangements of the control circuit 323, the first sense amplifier 305-1, and the second sense amplifier 305-2 may be implemented. For example, the control circuit 323 may be located in another portion of the die on which the first and second sense amplifiers 305-1 and 305-2 and the array 303 are constructed, or alternatively, outside the die with control lines routed to the first and second sense amplifiers 305-1 and 305-2.
Control circuitry 323 may be configured to select either the first sense amplifier 305-1 to provide data to the I/O circuitry 320-1 to output data on the data output path 329-1 using via 328-1 coupling the I/O circuitry 320-1 to the data output path 329-1, or the second sense amplifier 305-2 to provide data to the I/O circuitry 320-2 to output data on the data output path 329-2 using via 328-2 coupling the I/O circuitry 320-2 to the data output path 329-2. The data output path 329-1 and the data output path 329-2 may be routed to a common data output node of the DRAM 300, wherein the control circuit 323 regulates which of the data output path 329-1 or the data output path 329-2 provides data to the data output node by controlling the outputs of the first sense amplifier 305-1 and the second sense amplifier 305-2, or alternatively, the outputs of the I/O circuit 320-1 and the I/O circuit 320-2. By selecting either the first sense amplifier 305-1 or the second sense amplifier 305-2, one of the first selection devices 325-1-0, 325-1-2, 325-1-3 … … 325-1-124, 325-1-125, 325-1-126, and 325-1-127 and/or the second selection device 325-2-0, one of 325-2-1, 325-2-2, 325-2-3 … … 325-2-124, 325-2-125, 325-2-126, and 325-2-127 may be used to select either digit line 310-1 (lower path) or digit line 310-2 (upper path) to function in a read/write operation or a refresh operation of the host processor. Control circuit 323 is operable to vary the function of first sense amplifier 305-1 and digit line 310-1 and the function of second sense amplifier 327-2 and digit line 310-2 at different times, effectively as a function of time. In this arrangement, the host processor may operate with little or no refresh impact. Control circuitry separate from the host processor may be operated to control the refresh of the memory cells so that host operations on memory cells that are not refreshed may be performed within a time interval that overlaps with the refresh, which may reduce overhead. In addition, cells in different pillars can be refreshed in parallel by the two sets of select devices, two digit lines, and two sense amplifiers.
FIG. 4 is a graphical representation of features of an embodiment of an exemplary three-dimensional DRAM 400, the DRAM 400 comprising an array 403 of memory cells arranged in a horizontal direction in a plurality of vertical pillars 415-0, 415-1, 415-2, 415-3 … … 415 & 124, 415 & 125, 415 & 127. Memory cells are vertically stacked in each of these pillars, with each memory cell (such as a DRAM cell) in a respective pillar coupled to a pillar number word line in the respective pillar. Although 128 columns are indicated in the horizontal direction x, more or less than 128 columns may be implemented. Although eleven DRAM cells are shown in each column in the vertical direction z, more or less than eleven DRAM cells may be implemented. For example, DRAM 400 may include, but is not limited to, 128 DRAM cells in each of 128 pillars per digit line in the horizontal direction, which provides a DRAM with 128 layers. Along the y-direction, the pillars of stacked memory cells may be configured along the x-direction. Various features of DRAM 400 may be implemented similar to features of DRAM100 of figure 1,
DRAM 400 may include a first digit line 410-1, first digit line 410-1 being a conductive structure disposed in the x-direction below array 403 with respect to the z-direction. The first digit line 410-1 may be coupled in a horizontal direction to each of the pillars 415-0, 415-1, 415-2, 415-3 … … 415, 415-124, 415-125, 415-1-126, and 425-1-127 by first selection devices 425-1-0, 425-1-2, 425-1-3 … … 425, 425-1-125, 425-1-126, and 425-1-127, respectively. These select devices are lower select devices in the z-direction of the 3D structure and may be implemented by transistors. DRAM 400 may include a second digit line 410-2, second digit line 410-2 being a conductive structure disposed in the z-direction in the x-direction over array 403. The second digit line 410-2 may be coupled to each of the pillars 415-0, 415-1, 415-2, 415-3 … … 415, 415-125, 415-126, 415-127 through the second selection devices 425-2-0, 425-2-1, 425-2-2, 425-2-3 … … 425-2-124, 425-2-125, 425-2-126, and 425-2-127, respectively, in the horizontal direction. These select devices are the upper select devices in the z-direction of the 3D structure and may be implemented by transistors.
The first sense amplifier 405-1 may be coupled to the first digit line 410-1 through a via 427-1. A first sense amplifier 405-1 may be coupled to I/O circuit 420-1 to provide data to data output path 429, with I/O circuit 420-1 coupled to via 428. First sense amplifier 405-1, in conjunction with digit line 410-1 and selection of first selection devices 425-1-0, 425-1-2, 425-1-3 … … 425-1-124, 425-1-125, 425-1-126, and 425-1-127 may be used for read/write operations to array 403. The second sense amplifier 405-2 may be coupled to the second digit line 410-2 through a via 427-2 and may be implemented to perform a refresh operation of the array 403 using the second digit line 410-2.
The DRAM 400 may include a Static Random Access Memory (SRAM)430, the SRAM 430 configured to store bits from DRAM cells of the array 403, wherein the SRAM 430 is integrated with the array 403 in a die. The SRAM 430 may be configured to be positioned under the array 403. The SRAM 430 may be configured as an SRAM cache that may store N bits of DRAM cells from the array 403, Error Correction Code (ECC) data, or other data. The DRAM 400 may also include a processor 435 disposed in the die below the array 403 to control the SRAM 430. In addition to or in lieu of processor 435 disposed in a die below array 403, DRAM 400 may include Complementary Metal Oxide Semiconductor (CMOS) circuitry below array 403, control circuitry below array 403, logic circuitry below array 403, or other circuitry below array 403 integrated in the same die as array 403.
In operation, each row of array 403 may be sequentially addressed with a select device of the upper select devices 425-2-0, 425-2-1, 425-2-2, 425-2-3 … … 425-2-124, 425-2-125, 425-2-126, and 425-2-127 activated to couple the stub word line of the respective stub to the second sense amplifier 405-2 via the upper digit line 410-2 for refresh and via 427-2. The select devices of the lower select devices 425-1-0, 425-1-1, 425-1-2, 425-1-3 … … 425-1-124, 425-1-125, 425-1-126, and 425-1-127 may be activated to couple the stub word line of the corresponding stub to the first sense amplifier 405-1 via the lower digit line 410-1 and via 427-1 for read/write operations. Other variations coupled to sense amplifier 405-1 and/or sense amplifier 405-2 may be implemented.
The bits on the pillars (data line segments) may be read into the SRAM 430, or the data in the SRAM 430 may be output to the I/O420 through the sense amplifier 405-1. In addition, since the SRAM 430 serves as a cache in read/write operations of the memory array 403 of the DRAM 400, old pages in the SRAM 430 may be stored back to the array 403 of the DRAM 400 before new cache pages are loaded into the SRAM 430. The SRAM 430 may be implemented in a read-modify-write operation with a DRAM or other DRAM access-only operation. A read-modify-write operation is an operation that reads a memory location and simultaneously writes a new value thereto.
The 360nm × 360nm cell pillar footprint of 3D DRAM will allow one SRAM cell per 2 pillars in 45nm logic, for example, in a DRAM with 128 layersWhere there are 128 pillars or 64 layers per digit line, and where there are 64 pillars per digit line, means that there is sufficient SRAM capacity beneath the array 403 to store any one pillar per sense amplifier in the SRAM 430. For a 16Gb DRAM with 256Mb SRAM or a 32Gb DRAM with 512Mb SRAM, the SRAM cache 430 can be loaded in 64 or 128 cycles, 20ns each. This means that each sense amplifier 32 or 64 bits (128 Mb or 256Mb on die) can be buffered while refreshing 64 or 128 bits within 2.5 mus. For 10+14The bps maximum, assuming a 32Mb SRAM cache, may be greater than 10 gigabits/second.
The processor-in-memory (PIM) architecture may be implemented in an integrated 3D DRAM topology, as shown in fig. 4. The space in the die under array 403 would provide a mechanism for building a processor in a memory die. This may result in high performance system memory. Other circuitry may be located beneath array 403 integrated in the same die of DRAM 400.
FIG. 5 is an illustration of features of an embodiment of an exemplary three-dimensional DRAM500, the DRAM500 comprising an array 503 of memory cells arranged in a horizontal direction in a plurality of vertical pillars 515-0, 515-1, 515-2, 515-3 … … 515, 515-. Memory cells are vertically stacked in each of these pillars, with each memory cell (such as a DRAM cell) in a respective pillar coupled to a pillar number word line in the respective pillar. Although 128 columns are indicated in the horizontal direction x, more or less than 128 columns may be implemented. Although eleven DRAM cells are shown in each column in the vertical direction z, more or less than eleven DRAM cells may be implemented. For example, DRAM500 may include, but is not limited to, 128 DRAM cells in each of 128 pillars per digit line in the horizontal direction, which provides a DRAM with 128 layers. Along the y-direction, the pillars of stacked memory cells may be configured along the x-direction. Various features of DRAM500 may be implemented similar to features of DRAM100 of figure 1,
DRAM500 may include a first digit line 510-1, first digit line 510-1 being a conductive structure disposed in the x-direction below array 503 with respect to the z-direction. The first digit line 510-1 may be coupled to each of the pillars 515-0, 515-1, 515-2, 515-3 … … 515-124, 515-125, 515-126, and 515-127 in the horizontal direction by first selection devices 525-1-0, 525-1-2, 525-1-124, 525-1-125, 525-1-126, and 525-1-127, respectively. These select devices are lower select devices in the z-direction of the 3D structure and may be implemented by transistors. The DRAM500 may include a second digit line 510-2, the second digit line 510-2 being a conductive structure disposed in the z-direction above the array 503 in the x-direction. The second digit line 510-2 may be coupled to each of the pillars 515-0, 515-1, 515-2, 515-3 … … 515-124, 515-125, 515-126, and 515-127 in the horizontal direction through the second selection devices 525-2-0, 525-2-1, 525-2-2, 525-2-3 … … 525-2-124, 525-2-125, 525-2-126, and 525-2-127, respectively. These select devices are the upper select devices in the z-direction of the 3D structure and may be implemented by transistors. The second digit line 510-2 may be coupled to other control circuitry of the DRAM 500.
Sense amplifier 505 may be coupled to first digit line 510-1 through via 527-1. Sense amplifier 505 may be coupled to I/O circuitry 520 to provide data to data output path 529, I/O circuitry 520 being coupled to via 528. Sense amplifier 505, in conjunction with digit line 510-1 and selecting the appropriate ones of first select devices 525-1-0, 525-1-2, 525-1-3 … … 525-1-124, 525-1-125, 525-1-126, and 525-1-127 and the appropriate ones of second select devices 525-2-0, 525-2-1, 525-2-2, 525-2-3 … … 525-2-124, 525-2-125, 525-2-126, and 525-2-127 may be used for read/write operations to array 503.
The DRAM500 may include a Static Random Access Memory (SRAM)530, the SRAM530 configured to store bits from DRAM cells of the array 503, wherein the SRAM530 is integrated with the array 503 in a die. SRAM530 may be configured to be located under array 503. The SRAM530 may be configured as an SRAM cache that may store N bits of DRAM cells from the array 503, Error Correction Code (ECC) data, or other data. The SRAM530 may be arranged as an SRAM cache that shares the digit lines 510-1 and sense amplifiers 505 with the array 503. The DRAM500 may also include a processor 535 disposed in the die below the array 503 to control the SRAM 530. In addition to or in lieu of processor 535 disposed in a die below array 503, DRAM500 may include Complementary Metal Oxide Semiconductor (CMOS) circuitry below array 503, control circuitry below array 503, logic circuitry below array 503, or other circuitry below array 503 integrated in the same die as array 503.
In operation, a row of the array 503 may be addressed by an access line coupled to the corresponding row, with select devices of the upper select devices 525-2-0, 525-2-1, 525-2-2, 525-2-3 … … 525-2-124, 525-2-125, 525-2-126, and 525-2-127 activated to the upper digit line 510-2. The select devices of lower select devices 525-1-0, 525-1-1, 525-1-2, 525-1-3 … … 525-1-124, 525-1-125, 525-1-126, and 525-1-127 may be activated to couple the column number line for the corresponding column to sense amplifier 505 via lower digit line 510-1 for read/write operations and via 527-1.
The bits on the pillars (data line segments) may be read into the SRAM530, or the data in the SRAM530 may be output to the I/O520 through the sense amplifier 505. Additionally, because SRAM530 is used as a cache in read/write operations of memory array 503 of DRAM500, old pages in SRAM530 may be stored back to array 503 of DRAM500 before new cache pages are loaded into SRAM 530. DRAM500 may be arranged to read data from array 503 into SRAM cache 530 and write data back to array 503. DRAM500 may read data from array 503 to SRAM cache 530 at a rate of approximately 10 gbits/sec and write data back to the array at intervals of about 5 gbits/sec to about 10 gbits/sec. The SRAM530 may be implemented in a read-modify-write operation with a DRAM or other DRAM-only access operation.
The processor-in-memory (PIM) architecture may be implemented in an integrated 3D DRAM topology, as shown in fig. 5. The space in the die under the array 503 would provide a mechanism for building a processor in a memory die. This may result in high performance system memory. Other circuitry may be located beneath array 503 integrated in the same die of DRAM 500.
Fig. 6A is a schematic diagram of an embodiment of an exemplary 2D portion 600 of a 3D DRAM. Shown in FIG. 6 are access lines WL-1, WL-2 … … WL-N, representing a 3D DRAM, where N is equal to the number of layers of the 3D DRAM. The access lines WL-1, WL-2 … … WL-N may be considered to be in
Each DRAM cell may include an access transistor coupled to a capacitor. The access transistor may be implemented by a Metal Oxide Semiconductor (MOS) transistor. The capacitor is used to store charge representing data, and the transistor coupled to the capacitor provides effective coupling to a corresponding stub word line 612-i as a conductive structure for reading and writing data with respect to the capacitor. DRAM cells are not limited to MOS transistor-capacitor arrangements, but may be implemented by active devices that control access to the memory device that can be maintained at an appropriate refresh rate and change states representing data under appropriate actuation.
For i-1 to 4, each group of DRAM cells 604-i-1, 604-i-2 … … 604-i-N may be coupled to an access line WL-1, WL-2 … … WL-N, respectively, that provides a control line to the access devices of the respective DRAM cells. For example, access lines WL-1, WL-2 … … WL-N may be word lines. Pillar digit lines 612-1, 612-2, 612-3, and 612-4, which extend vertically along their respective pillars, may be coupled to lower digit line 610-1 by select ISO transistors 625-1-1, 625-1-2, 625-1-3, and 625-1-4, respectively, and to upper digit line 610-2 by select ISO transistors 625-2-1, 625-2-2, 625-2-3, and 625-2-4, respectively, for reading or writing to selected DRAM cells. Lower digit line 610-1 is coupled to sense amplifier SA1 and is vertically displaced from upper digit line 610-2 coupled to sense amplifier SA 2. The control signals for access lines WL-1, WL-2 … … WL-N and select transistors 625-1-i and 625-2-i for
This architecture may allow the DRAM to have 128 pillars or other numbers of pillars along the direction of the digit lines 610-1 and 610-2, which digit lines 610-1 and 610-2 may be metal lines. This architecture can reduce the total number and area of sense amplifiers by enabling refreshing in parallel with array accesses. Within a single WL group that is part of the memory array, while reading DRAM cells, other rows within the same WL group cannot be refreshed because they contain DRAM cells on the same pillar in the single WL group and share a common IOS device coupled to the first set of
Fig. 6B is a circuit diagram of an embodiment of an exemplary 3D-
For example, in a read sequence, selected access lines in WL-1 … … WL-N in a selected WL group are activated by the ACT command. Information of the plurality of memory cells connected to the selected access line is simultaneously transferred to the respective digit lines. Then, the sense amplifiers connected to the digit lines (such as the first group SA) are simultaneously activated by the row control signal. Then, for example, in response to a read command, one of the activated sense amplifiers is selected and data in the selected sense amplifier is transferred to the data amplifier by a column selection signal and a column control signal.
In a refresh sequence, in response to a refresh command, a selected access line in a selected group of WLs is activated to transfer information stored in the memory cell to a corresponding digit line. The information on the digit lines is then amplified by a plurality of sense amplifiers respectively connected to the digit lines (such as the second set of SAs). Then, the information amplified by the SA is rewritten into the same memory cells, respectively. At this time, the column-related signal is not activated.
For such read and refresh operations, M SAs, M digit lines, and M memory cells may be connected to one access line. Multiple WL groups may share the group SA.
Fig. 6C illustrates an embodiment of an example of memory operations for an
Read and refresh operations may be performed on
Fig. 7 is an illustration of features of an embodiment of an exemplary 3-D DRAM700, the 3-D DRAM700 being arranged in a plurality of horizontal levels in a vertical direction. Although three levels a, B, and C are shown, more or less than three levels may be implemented. For ease of illustration, the array of memory cells is not shown. Instead, groups of digit lines 712-A, 712-B, 712-C in tier A, tier B, and tier C are shown, respectively, with each digit line coupled to a plurality of DRAM cells stacked horizontally. DRAM700 may include a set of first digit lines 710-1, the set of first digit lines 710-1 being conductive structures disposed in the z-direction to couple to a set of first select devices 725-1-A, a set of first select devices 725-1-B, and a set of first select devices 725-1-C in levels A, B, and C, respectively. These group selection means are located at one end of the corresponding digital line groups 712-a, 712-B, 712-C in level a, level B and level C in the x-direction of the 3D structure and may be implemented by transistors.
DRAM700 may include a set of second digit lines 710-2, the set of second digit lines 710-2 being conductive structures disposed in the z-direction. The set of second digit lines 710-2 may be vertically coupled to a set of second select devices 725-2-a, a set of second select devices 725-2-B, and a set of second select devices 725-2-C in level a, level B, and level C, respectively. These group selection means are located at the other end of the corresponding digital line groups 712-a, 712-B, 712-C in level a, level B and level C in the x-direction of the 3D structure and may be implemented by transistors. The set of second select devices 725-2-A, the set of second select devices 725-2-B, and the set of second select devices 725-2-C are opposite the set of first select devices 725-1-A, the set of first select devices 725-1-B, and the set of first select devices 725-1-C with respect to the sets of digital lines 712-A, 712-B, 712-C in level A, level B, and level C, respectively.
A first sense amplifier 705-1 may be coupled to the set of first digit lines 710-1. A second sense amplifier 705-2 may be coupled to the set of second digit lines 710-2. In an embodiment, one of the first sense amplifier 705-1 or the second sense amplifier 705-2 may be used with internal control circuitry to perform read and write operations to memory cells coupled to selected ones of the set of digit lines 712-A, 712-B, 712-C with respect to a host device, such as a host processor. Additionally, the other of the first sense amplifier 705-1 or the second sense amplifier 705-2 may be used with internal control circuitry to refresh memory cells coupled to selected ones of the digit lines in the digit line groups 712-A, 712-B, 712-C. In this arrangement, the host processor may operate with little or no refresh impact. Control circuitry separate from the host processor may be operated to control the refresh of the memory cells so that host operations on memory cells that are not refreshed may be performed within a time interval that overlaps with the refresh, which may reduce overhead. In addition, the first sense amplifier 705-1 and the second sense amplifier 705-2 may allow memory cells in different levels to be refreshed in parallel. Access to the memory cells may be implemented using selected access lines (such as, but not limited to, access lines WL0, WL1 … … WLM).
As can be seen from fig. 1-5, in the exemplary 3-D DRAM700, the digit lines comprising the coupled DRAM memory cells are configured as a horizontal stack, rather than the vertical stack of the DRAM memory cells of fig. 1-5. For ease of illustration, fig. 1-5 show one level of DRAM cells. Considering only level a and rotating the level ninety degrees counterclockwise, the rotated structure would be similar to the architecture associated with fig. 1-5. For ease of illustration, the control circuitry is not shown in fig. 7. The exemplary 3-D DRAM700 of fig. 7 may be constructed with the circuitry of fig. 1-5, and may be modified to operate similar to the architecture of fig. 1-5 or a similar architecture. This horizontal arrangement of the 3-D DRAM700 may operate in a manner having the same advantages as the vertical arrangement of the 3-D DRAM associated with fig. 1 through 5.
FIG. 8 is a flow chart of an embodiment of an exemplary method 800 of accessing a memory cell of a memory device. At 810, data is written to or read from memory cells in an array of memory cells using a first digit line coupled to a first sense amplifier, the array being a three-dimensional array of pillars, each pillar having memory cells vertically stacked in a respective pillar. The plurality of columns may be arranged in a horizontal direction. At 820, memory cells in pillars other than the pillar containing the memory cell to which data is written or read are refreshed using a second digit line coupled to a second sense amplifier. One of the first digit line and the second digit line is disposed below the array and the other of the first digit line and the second digit line is disposed above the array.
The method 800 or a variation of a method similar to the method 800 may include many different embodiments, which may depend on the application of the methods and/or the architecture of the system implementing the methods. Such a method may include continuously refreshing memory cells in pillars other than the pillar in which data is being read from or written to the memory cells. Writing or reading data may include reading one or more bits from one or more pillars of the array into a static random access memory disposed below the array of memory cells. Method 800, or a variation of a method similar to method 800, may include storing a new cache page into a static random access memory cache disposed below an array of memory cells and storing an existing page stored in the static random access memory cache back to the array before loading the new page into the static random access memory cache.
In various embodiments, a memory device may include: an array of memory cells, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked therein, a plurality of the pillars being arranged in a horizontal direction; a first digit line disposed below the array, the first digit line coupled to each of the pillars in the horizontal direction through a respective first select device; a second digit line over the array, the second digit line coupled to each of the pillars in the horizontal direction through a respective second select device; a first sense amplifier coupled to the first digit line; a second sense amplifier coupled to the second digit line; and an input/output circuit coupled to the first sense amplifier or the second sense amplifier.
Variations of such memory devices or similar memory devices may include many different embodiments, which may depend on the application of such memory devices and/or the architecture of the system in which such memory devices are implemented. Such a memory device may include control circuitry to access a first memory cell in one of the pillars in a horizontal direction via an access line coupled to the first memory cell and via one of a first digit line or a second digit line coupled to the one pillar, and to access a second memory cell in another of the pillars in the horizontal direction via an access line coupled to the second memory cell and via the other of the first digit line or the second digit line. The control circuitry may be operable to control access to the first memory cell and access to the second memory cell in overlapping time intervals. Each of the memory cells in each pillar may be a DRAM cell coupled to a pillar digit line of the respective pillar, the pillar digit line coupled to a respective first select device and a respective second select device of the respective pillar.
Variations of this or similar memory devices may include many different features. The memory device may include an SRAM configured to store bits of memory cells from each of a selected number of the pillars in a horizontal direction, wherein the SRAM is integrated with the array of memory cells in a die. The SRAM may be configured to be located under the memory cell array. The memory device may include a processor disposed in the die below the array of memory cells to control the static random access memory. Another feature may include a memory device having a second input/output circuit coupled to the first sense amplifier or a second sense amplifier not coupled to the input/output circuit.
FIG. 9 is a flow diagram of an embodiment of an
The
In various embodiments, a memory device may include: an array of memory cells in a die, the array being a three-dimensional array of pillars, each pillar having a memory cell vertically stacked therein, a plurality of the pillars being arranged in a horizontal direction; a digit line disposed below or above the array, the digit line coupled to each of the pillars in the horizontal direction by a respective select device coupled to a pillar digit line of a respective pillar; an SRAM cache integrated in the die with and disposed below the array of memory cells; a sense amplifier coupled to the digit line; and an input/output circuit coupled to the sense amplifier. The array and the sram cache may share digit lines and sense amplifiers.
Variations of such memory devices or similar memory devices may include many different embodiments, which may depend on the application of such memory devices and/or the architecture of the system in which such memory devices are implemented. Such memory devices may include respective memory devices arranged to read data from the array to the sram cache and write data back to the array. The memory device may read data from the array into the sram cache at a rate of approximately 10 gbits/sec and write data back to the array at intervals of about 5 gbits/sec to about 10 gbits/sec. The memory device may include a processor disposed in the die below the array of memory cells to control the static random access memory.
Fig. 10 is a block diagram of features of a DRAM1000 in which a 3D structure and associated structures of pillars of memory cells, as taught herein, may be constructed such as a 3D DRAM structure according to, but not limited to, fig. 1-7. DRAM1000 may include an address decoder 1009 and a control circuit 1007 to operate with respect to memory cell array 1003 to read and write memory cells in memory cell array 1003 using sense amplifiers 1005 and I/O circuits 1020. Other components of DRAM1000 are not shown to focus on the exemplary use of a 3D memory array of cells and associated sense amplifiers in a vertical configuration. Additionally, address decoder 1009 may be coupled to an address bus, control circuit 1007 may be coupled to a control bus, and I/O circuitry 1020 may be coupled to a data bus.
Fig. 11 shows an example of a wafer 1100 arranged to provide a plurality of electronic components. Wafer 1100 may be provided as a wafer in which a plurality of dies 1105 may be fabricated. Alternatively, the wafer 1100 may be provided as a wafer in which multiple dies 1105 have been processed to provide electronic functionality and are waiting to be singulated from the wafer 1100 for packaging. Wafer 1100 may be provided as a semiconductor wafer, a semiconductor on insulator wafer, or other suitable wafer for processing electronic devices such as integrated circuit chips. Wafer 1100 may be fabricated in accordance with the teachings of the embodiments associated with fig. 1-7 and 10, using conventional semiconductor fabrication techniques to form devices.
Each die 1105 may be processed to include functional circuitry using various masking and processing techniques such that each die 1105 is fabricated as an integrated circuit having the same functionality and packaging structure as the other dies on the wafer 1100. Alternatively, various groups of dies 1105 can be processed to include functional circuitry using various masking and processing techniques, such that not all of the dies 1105 are fabricated as integrated circuits having the same functionality and packaging structure as the other dies on the wafer 1100. A packaged die having integrated circuits that provide electronic capabilities thereon is referred to herein as an Integrated Circuit (IC).
Wafer 1100 may contain memory devices, where each memory device is located in a die 1105. The memory die may be constructed as a 3D memory device having a plurality of memory cells disposed in a plurality of pillars between a lower digit line and an upper digit line with sense amplifiers to provide read/write operations and refresh operations, arranged as taught herein using conventional fabrication techniques and processes. An example of a memory device located in a die 1105 may include an array of memory cells that share sense amplifiers and digit lines with an SRAM cache formed under the array of memory cells in the same die.
Fig. 12 shows a block diagram of a system 1200, the system 1200 including a memory 1263, the memory 1263 being constructed as a 3D memory device having a plurality of memory cells disposed in a plurality of pillars between a lower digit line and an upper digit line having sense amplifiers to provide read/write operations and refresh operations, arranged as taught herein. The memory 1263, which is configured as a 3D memory device, may be configured to contain an array of memory cells that share sense amplifiers and digit lines with an SRAM cache formed under the array of memory cells in the same die. The device architecture of memory 1263 may be implemented in a manner similar or identical to the structure in accordance with the various embodiments discussed herein.
The system 1200 may include a controller 1262 operably coupled to a memory 1263. The controller 1202 may be in the form of one or more processors. The system 1200 may also include an electronic device 1267, peripheral devices 1269, and a communication module 1261. One or more of the controller 1262, memory 1263, electronics 1267, peripherals 1269, and communication module 1261 can be in the form of one or more ICs.
A bus 1266 provides electrical conductivity between the various components of the system 1200. In an embodiment, bus 1266 includes an address bus, a data bus, and a control bus that are each independently configured. In an alternative embodiment, bus 1266 uses common conductors to provide one or more of address, data, or control, and the use of bus 1266 is regulated by controller 1202. Bus 1266 may include components of a communication network.
The electronic device 1267 may include additional memory. Such additional memory in system 1200 may be constructed as one or more types of memory such as, but not limited to, DRAM, SRAM, Synchronous Dynamic Random Access Memory (SDRAM), Synchronous Graphics Random Access Memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, magnetic based memory, or other emerging memory cell technologies.
The peripheral devices 1269 may include a display, an imaging device, a printing device, a wireless device, additional storage memory, and a control device operable with the controller 1262. In various embodiments, system 1200 may include, but is not limited to, fiber optic systems or devices, electro-optic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices (such as wireless systems or devices, telecommunication systems or devices, and computers).
As taught herein, the architectural design of 3D DRAM may provide very fast loading of cache memory, up to 10 gigabits/second. Even if the cache is on the same chip as the DRAM, using the cache can access data much faster than directly from the DRAM. This may almost eliminate the need for the system to perform a refresh because it may be performed by the die in the background, but this may consume power. By layering digit lines, the number of sense amplifiers may be much smaller than a planar structure, and digit line capacitance may be less than a planar structure, but may cause 3D DRAM access device leakage, which may be addressed by more refresh cycles.
Compared to some conventional planar DRAMs, 3D DRAMs may be approximately 70% of cost and approximately 70% of die size, and may achieve at least three to four die shrinks of approximately 30% each. As taught herein, the architecture may overcome the barriers to access device leakage for 3D DRAMs, allowing fifty times more leakage while eliminating the overhead for refreshing. In various embodiments of an architecture in which SRAM is added below the memory array, high speed SRAM cache loading may be achieved. SRAM may be built underneath the memory array because space is available and the SRAM may be located behind the sense amplifiers underneath the memory array.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that other arrangements that depart from the teachings herein may be substituted for the specific embodiments shown. Various embodiments use permutations and/or combinations of the embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description.
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