Three-dimensional memory device and method for forming the same
阅读说明:本技术 三维存储器件及用于形成其的方法 (Three-dimensional memory device and method for forming the same ) 是由 吴林春 周文犀 于 2020-04-27 设计创作,主要内容包括:公开了3D存储器件及用于形成其的方法的实施例。在一个示例中,一种3D存储器件包括:衬底的N型掺杂区;位于所述N型掺杂区上的N型掺杂半导体层;位于所述N型掺杂半导体层上的包括交织的导电层和电介质层的存储堆叠层;垂直地延伸通过所述存储堆叠层和所述N型掺杂半导体层进入所述N型掺杂区的沟道结构;以及,垂直地延伸通过所述存储堆叠层和所述N型掺杂半导体层进入所述N型掺杂区的源触点结构。所述源触点结构的被所述N型掺杂区包围的第一部分的第一横向尺寸大于所述源触点结构的被所述存储堆叠层包围的第二部分的第二横向尺寸。(Embodiments of a 3D memory device and a method for forming the same are disclosed. In one example, a 3D memory device includes: an N-type doped region of the substrate; the N-type doped semiconductor layer is positioned on the N-type doped region; a memory stack layer comprising interleaved conductive and dielectric layers on the N-doped semiconductor layer; a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region; and a source contact structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.)
1. A three-dimensional (3D) memory device, comprising:
an N-type doped region of the substrate;
the N-type doped semiconductor layer is positioned on the N-type doped region;
a memory stack layer comprising interleaved conductive and dielectric layers on the N-doped semiconductor layer;
a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region; and
a source contact structure extending vertically through the storage stack layer and the N-doped semiconductor layer into the N-doped region, wherein a first lateral dimension of a first portion of the source contact structure surrounded by the N-doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.
2. The 3D memory device of claim 1, wherein the N-type doped semiconductor layer comprises polysilicon.
3. The 3D memory device of claim 2, wherein the N-type doped semiconductor layer is a single polysilicon layer having a uniform doping concentration profile.
4. The 3D memory device of claim 3, wherein the N-type doped semiconductor layer has a doping concentration of about 1017cm-3And about 1021cm-3In the meantime.
5. The 3D memory device of any one of claims 1-4, wherein the substrate is an N-type silicon substrate.
6. The 3D memory device of any one of claims 1-4, wherein the substrate is a P-type silicon substrate and the N-type doped region is an N-well.
7. The 3D memory device of any one of claims 1-6, wherein the channel structure includes a memory film and a semiconductor channel, and a portion of the semiconductor channel along a sidewall of the channel structure is in contact with the N-type doped semiconductor layer.
8. The 3D memory device of any one of claims 1-7, wherein the 3D memory device is configured to generate a gate-induced-drain-leakage (GIDL) assisted body bias voltage when performing an erase operation.
9. The 3D memory device of any one of claims 1-8, wherein the source contact structure comprises a source contact and a spacer each extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
10. The 3D memory device of claim 9, wherein the source contact is in contact with the N-type doped region.
11. The 3D memory device of claim 9 or 10, wherein the source contact comprises titanium nitride (TiN).
12. The 3D memory device of any one of claims 1-11, wherein the first lateral dimension of the first portion of the source contact structure is greater than a third lateral dimension of a third portion of the source contact structure surrounded by the N-doped semiconductor layer.
13. The 3D memory device of claim 12, wherein the third lateral dimension is greater than the second lateral dimension of the second portion of the source contact structure.
14. A three-dimensional (3D) memory device, comprising:
an N-type doped region of the substrate;
a memory stack layer comprising interleaved conductive and dielectric layers located over the N-type doped region;
a single N-type doped semiconductor layer located between the N-type doped region and the storage stack layer and having a uniform doping concentration profile; and
a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
15. The 3D memory device of claim 14, wherein the N-type doped semiconductor layer comprises polysilicon.
16. The 3D memory device of claim 14 or 15, wherein the N-type doped semiconductor layer has a doping concentration of about 1017cm-3And about 1021cm-3In the meantime.
17. The 3D memory device of any one of claims 14-16, wherein the channel structure includes a memory film and a semiconductor channel, and a portion of the semiconductor channel along a sidewall of the channel structure is in contact with the N-type doped semiconductor layer.
18. The 3D memory device of any one of claims 14-17, wherein the 3D memory device is configured to generate a gate-induced-drain-leakage (GIDL) assisted body bias when performing an erase operation.
19. The 3D memory device of any one of claims 14-18, further comprising:
a source contact structure extending vertically through the storage stack layer and the N-doped semiconductor layer into the N-doped region, wherein a first lateral dimension of a first portion of the source contact structure surrounded by the N-doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.
20. The 3D memory device of claim 19, wherein the source contact structure comprises a source contact and a spacer each extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
21. The 3D memory device of claim 20, wherein the source contact is in contact with the N-type doped region.
22. The 3D memory device of claim 20 or 21, wherein the source contact comprises titanium nitride (TiN).
23. The 3D memory device of any one of claims 19 to 22, wherein the first lateral dimension of the first portion of the source contact structure is greater than a third lateral dimension of a third portion of the source contact structure surrounded by the N-doped semiconductor layer.
24. The 3D memory device of claim 23, wherein the third lateral dimension is greater than the second lateral dimension of the second portion of the source contact structure.
25. The 3D memory device of any one of claims 14-24, wherein the substrate is an N-type silicon substrate.
26. The 3D memory device of any one of claims 14-24, wherein the substrate is a P-type silicon substrate and the N-type doped region is an N-well.
27. A method for forming a three-dimensional (3D) memory device, comprising:
forming a recess in the N-type doped region of the substrate;
subsequently forming a sacrificial layer on the N-type doped region and in the recess, and forming a dielectric stack layer on the sacrificial layer;
forming a channel structure extending vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region.
Forming an opening in the recess that extends vertically through the dielectric stack layer into the sacrificial layer;
replacing the sacrificial layer with an N-doped semiconductor layer between the N-doped region and the dielectric stack layer through the opening; and
forming a source contact structure in the opening and the recess.
28. The method of claim 27, further comprising, prior to forming the source contact structure:
replacing the dielectric stack layer with a storage stack layer through the opening such that the channel structure extends vertically through the storage stack layer and the N-doped semiconductor layer into the N-doped region.
29. The method of claim 27 or 28, wherein a lateral dimension of the recess is greater than a lateral dimension of the opening.
30. The method of any of claims 27-29, wherein forming the channel structure comprises:
forming a channel hole extending vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region; and
a memory film and a semiconductor channel are then formed along sidewalls of the channel hole.
31. The method of claim 30, wherein replacing the sacrificial layer with the N-type doped semiconductor layer comprises:
removing the sacrificial layer to form a cavity between the N-type doped region and the dielectric stack layer;
removing a portion of the storage film to expose a portion of the semiconductor channel along the sidewall of the channel hole; and
and depositing N-type doped polysilicon into the cavity to form an N-type doped semiconductor layer.
32. The method of claim 31, wherein depositing the N-type doped polysilicon into the cavity comprises: the polysilicon is in-situ doped to fill the cavity with a uniform doping concentration profile.
33. The method of any of claims 27-32, wherein forming the source contact structure comprises:
forming a spacer along sidewalls of the opening and the recess; and
a source contact is formed over the spacer and in contact with the N-doped region.
34. The method of claim 33, wherein the source contact comprises titanium nitride (TiN).
Technical Field
Embodiments of the present disclosure relate to a three-dimensional (3D) memory device and a method of fabricating the same.
Background
Flat memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, the planarization process and fabrication techniques become challenging and costly. Therefore, the storage density of the flat memory cell approaches the upper limit.
The 3D memory architecture can address density limitations in flat memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
Disclosure of Invention
Embodiments of a 3D memory device and methods for forming the same are disclosed herein.
In one example, a 3D memory device includes: an N-type doped region of the substrate; the N-type doped semiconductor layer is positioned on the N-type doped region; a memory stack layer comprising interleaved conductive and dielectric layers on the N-doped semiconductor layer; a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region; and a source contact structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.
In another example, a 3D memory device includes: an N-type doped region of the substrate; a memory stack layer comprising interleaved conductive and dielectric layers located over the N-type doped region; a single N-type doped semiconductor layer located between the N-type doped region and the storage stack layer and having a uniform doping concentration profile; and a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
In yet another example, a method for forming a 3D memory device is provided. A recess is formed in the N-type doped region of the substrate. Forming a sacrificial layer on the N-type doped region and in the recess, and subsequently forming a dielectric stack layer on the sacrificial layer. Forming a channel structure extending vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region. An opening is formed in the recess that extends vertically through the dielectric stack layer into the sacrificial layer. Replacing the sacrificial layer with an N-doped semiconductor layer between the N-doped region and the dielectric stack layer through the opening. Forming a source contact structure in the opening and the recess.
Drawings
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
FIG. 1 illustrates a side view of a cross-section of one exemplary 3D memory device, in accordance with some embodiments of the present disclosure.
2A-2I illustrate a fabrication process for forming one exemplary 3D memory device, according to some embodiments of the present disclosure.
FIG. 3 illustrates a flow diagram of a method for forming an exemplary 3D memory device, according to some embodiments of the present disclosure.
Embodiments of the present disclosure will be described with reference to the accompanying drawings.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the disclosure. It should be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.
It should be noted that references in this specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In general terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic in any singular sense, or may be used to describe a combination of features, structures, or characteristics in plural senses, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" again may be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, again depending at least in part on context, but may instead allow for the presence of additional factors that are not necessarily explicitly described.
It should be apparent that the meanings of "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest manner such that "on … …" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "on … …" or "above … …" not only means "on something" or "above something", but may also include the meaning of "on something" or "above something" without any intervening features or layers therebetween (i.e., directly on something).
Further, for ease of description, spatially relative terms (such as "below … …," "below … …," "lower," "above … …," "higher," etc.) may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, and the like). Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Further, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes there. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers located therein, and/or may have one or more layers located thereon, above, and/or below. A layer may comprise a plurality of layers. For example, one interconnect layer may include one or more conductor and contact layers (in which interconnect lines are formed and/or accessed via vertical interconnects of contacts) and one or more dielectric layers.
As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter of a component or process operation set during a design phase of a product or process, as well as a range of values above and/or below the desired value. The range of values may result from slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may indicate a value of a given amount that varies, for example, within 10-30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.
As used herein, the term "3D memory device" refers to a semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a "memory string," such as a NAND memory string) located on a laterally oriented substrate such that the memory string extends in a vertical direction with respect to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.
In some 3D NAND memory devices, a semiconductor plug is selectively grown to surround sidewalls of a channel structure, for example, referred to as sidewall Selective Epitaxial Growth (SEG). Compared to another type of semiconductor plug (e.g., a bottom SEG) formed at a lower end of the channel structure, the formation of the sidewall SEG avoids etching the memory film and the semiconductor channel (also referred to as a "SONO" via) at the bottom surface of the channel hole, thus increasing the process window, particularly when fabricating 3D NAND memory devices with advanced techniques, such as with 96 or more layers with a concomitant multi-stack architecture. However, since the thickness and distribution of the sidewall SEG depends on the topography of the semiconductor channel along the sidewalls of the channel structure, the residue on the semiconductor channel may cause a large change in the epitaxial growth of the sidewall SEG.
In addition, some 3D NAND memory devices having the sidewall SEG perform a P-well bulk erase operation using a P-well that supplies holes for erasing. However, when performing a read operation, the P-well needs to be inverted in order to form an inversion channel, which complicates the control of the source select gate.
Various embodiments according to the present disclosure provide improved 3D memory devices and methods of fabricating the same. An N-type doped semiconductor layer may be deposited in contact with the semiconductor channel along the sidewalls of the channel structure, which is unaffected by any residue on the semiconductor channel. The N-doped semiconductor layer in combination with the N-doped region may generate a gate-induced-drain-leakage (GIDL) auxiliary body bias when performing an erase operation (referred to herein as a "GIDL erase") by the 3D memory device instead of a P-well bulk erase, thus eliminating the need for an inversion channel when performing a read operation and simplifying control of the source select gate. In some embodiments, each opening (e.g., gate slit (GLS)) used to form the source contact structure falls into a respective enlarged recess in the N-type doped region to avoid any negative effects due to gouging variations between different openings.
Fig. 1 illustrates a side view of a cross-section of one exemplary
The
Alternatively, the
As shown in fig. 1, the substrate of the
As shown in fig. 1, the
In some embodiments, the
The
As shown in fig. 1, the
The
As shown in fig. 1, according to some embodiments, portions of the
As shown in fig. 1, the
The
In some embodiments, the source contact 130 includes an
According to some embodiments, the
2A-2I illustrate a fabrication process for forming one exemplary 3D memory device, according to some embodiments of the present disclosure. FIG. 3 illustrates a flow diagram of a method 300 for forming an exemplary 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in fig. 2A-2I and 3 include the
Referring to fig. 3, the method 300 begins at operation 302, where a recess is formed in an N-type doped region of a substrate in operation 302. In some embodiments, the substrate is an N-type silicon substrate. In some embodiments, the substrate is a P-type silicon substrate and the N-type doped region is an N-well. As illustrated in fig. 2A, an N-type doped
As illustrated in fig. 3, the method 300 proceeds to operation 304, and in operation 304, a sacrificial layer located on the N-type doped region and in the recess and a dielectric stack layer located on the sacrificial layer are subsequently formed. The sacrificial layer may be a polysilicon layer. The dielectric stack layer may include a plurality of interleaved stacked sacrificial layers and stacked dielectric layers.
As illustrated in fig. 2A, a
As illustrated in fig. 2A, a
As illustrated in fig. 3, the method 300 proceeds to operation 306, and in operation 306, a channel structure is formed that extends vertically through the dielectric stack and the sacrificial layer into the N-type doped region. In some embodiments, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region, and then the memory film and the semiconductor channel are formed along sidewalls of the channel hole. In some embodiments, a channel plug is formed over and in contact with the semiconductor channel.
As illustrated in fig. 2A, the channel hole is an opening that extends vertically through the
As illustrated in fig. 2A, a storage film 216 (including a barrier layer, a storage layer, and a tunneling layer) and a
As illustrated in fig. 2A, a cap layer 220 is formed in the channel hole and over the
As illustrated in fig. 3, the method 300 proceeds to operation 308, where in operation 308, an opening is formed that extends vertically through the dielectric stack layer into the sacrificial layer in the recess. In some embodiments, the lateral dimension of the recess is greater than the lateral dimension of the opening.
As illustrated in fig. 2B, the
As illustrated in fig. 3, the method 300 proceeds to operation 310, in operation 310, a sacrificial layer is replaced with an N-type doped semiconductor layer between the N-type doped region and the dielectric stack layer through the opening. In some embodiments, to replace the sacrificial layer with an N-type doped semiconductor layer, the sacrificial layer is removed to form a cavity between the N-type doped region and the dielectric stack layer, a portion of the memory film is removed to expose a portion of the semiconductor channel along a sidewall of the channel hole, and N-type doped polysilicon is deposited into the cavity to form an N-type doped semiconductor layer. In some embodiments, to deposit N-type doped polysilicon into the cavity, the polysilicon is in-situ doped with a uniform doping concentration profile to fill the cavity.
As illustrated in fig. 2C, sacrificial layer 204 (shown in fig. 2B) is removed by wet etching and/or dry etching to form
As illustrated in fig. 2D, the portion of the
As illustrated in fig. 2E, an N-doped
As illustrated in fig. 3, the method 300 proceeds to operation 312 where the dielectric stack layer is replaced with a storage stack layer through the opening in operation 312. As illustrated in fig. 2F, the N-doped
As illustrated in fig. 2G, the spacer 228 (as shown in fig. 2C) covering the sidewalls of the
As illustrated in fig. 3, the method 300 proceeds to operation 314, where in operation 314, source contact structures are formed in the openings and recesses. In some embodiments, to form the source contact structure, spacers are formed along sidewalls of the openings and recesses, and a source contact is formed over the spacers and in contact with the N-type doped region. The source contact may comprise TiN.
As illustrated in fig. 2H, spacers 238 comprising one or more dielectrics, such as silicon oxide, are formed along the sidewalls of the
As illustrated in fig. 2I, a source contact 244 is formed over the spacer 238 to fill the
According to an aspect of the present disclosure, a 3D memory device includes: an N-type doped region of the substrate; the N-type doped semiconductor layer is positioned on the N-type doped region; a memory stack layer comprising interleaved conductive and dielectric layers on the N-doped semiconductor layer; a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region; and a source contact structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region. A first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.
In some embodiments, the N-type doped semiconductor layer comprises polysilicon.
In some embodiments, the N-type doped semiconductor layer is a single polysilicon layer having a uniform doping concentration profile.
In some embodiments, the N-type doped semiconductor layer has a doping concentration of about 1017cm-3And about 1021cm-3In the meantime.
In some embodiments, the substrate is an N-type silicon substrate.
In some embodiments, the substrate is a P-type silicon substrate and the N-type doped region is an N-well.
In some embodiments, the channel structure includes a memory film and a semiconductor channel, and a portion of the semiconductor channel along a sidewall of the channel structure is in contact with the N-type doped semiconductor layer.
In some embodiments, the 3D memory device is configured to generate the GIDL assist body bias voltage when performing an erase operation.
In some embodiments, the source contact structure includes a source contact and a spacer each extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
In some embodiments, the source contact is in contact with the N-type doped region.
In some embodiments, the source contact comprises TiN.
In some embodiments, the first lateral dimension of the first portion of the source contact structure is greater than a third lateral dimension of a third portion of the source contact structure surrounded by the N-type doped semiconductor layer.
In some embodiments, the third lateral dimension is greater than the second lateral dimension of the second portion of the source contact structure.
According to another aspect of the present disclosure, a 3D memory device includes: an N-type doped region of the substrate; a memory stack layer comprising interleaved conductive and dielectric layers located over the N-type doped region; a single N-type doped semiconductor layer located between the N-type doped region and the storage stack layer and having a uniform doping concentration profile; and a channel structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
In some embodiments, the N-type doped semiconductor layer comprises polysilicon.
In some embodiments, the N-type doped semiconductor layer has a doping concentration of about 1017cm-3And about 1021cm-3In the meantime.
In some embodiments, the channel structure includes a memory film and a semiconductor channel, and a portion of the semiconductor channel along a sidewall of the channel structure is in contact with the N-type doped semiconductor layer.
In some embodiments, the 3D memory device is configured to generate the GIDL assist body bias voltage when performing an erase operation.
In some embodiments, the 3D memory device further includes: a source contact structure extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region. According to some embodiments, a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the storage stack layer.
In some embodiments, the source contact structure includes a source contact and a spacer each extending vertically through the memory stack layer and the N-doped semiconductor layer into the N-doped region.
In some embodiments, the source contact is in contact with the N-type doped region.
In some embodiments, the source contact comprises TiN.
In some embodiments, the first lateral dimension of the first portion of the source contact structure is greater than a third lateral dimension of a third portion of the source contact structure surrounded by the N-type doped semiconductor layer.
In some embodiments, the third lateral dimension is greater than the second lateral dimension of the second portion of the source contact structure.
In some embodiments, the substrate is an N-type silicon substrate.
In some embodiments, the substrate is a P-type silicon substrate and the N-type doped region is an N-well.
According to still another aspect of the present disclosure, a method for forming a 3D memory device is provided. A recess is formed in the N-type doped region of the substrate. A sacrificial layer is then formed over the N-type doped region and in the recess, and a dielectric stack layer is formed over the sacrificial layer. Forming a channel structure extending vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region. An opening is formed in the recess that extends vertically through the dielectric stack layer into the sacrificial layer. Replacing the sacrificial layer with an N-doped semiconductor layer between the N-doped region and the dielectric stack layer through the opening. Forming a source contact structure in the opening and the recess.
In some embodiments, prior to forming the source contact structure, replacing the dielectric stack layer with a storage stack layer through the opening such that the channel structure extends vertically through the storage stack layer and the N-doped semiconductor layer into the N-doped region.
In some embodiments, a lateral dimension of the recess is greater than a lateral dimension of the opening.
In some embodiments, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack layer and the sacrificial layer into the N-type doped region; and then forming a storage film and a semiconductor channel along sidewalls of the channel hole.
In some embodiments, to replace the sacrificial layer with the N-doped semiconductor layer, the sacrificial layer is removed to form a cavity between the N-doped region and the dielectric stack layer; removing a portion of the storage film to expose a portion of the semiconductor channel along the sidewall of the channel hole; and depositing N-type doped polysilicon into the cavity to form an N-type doped semiconductor layer.
In some embodiments, to deposit the N-type doped polysilicon into the cavity, the polysilicon is in-situ doped so as to fill the cavity with a uniform doping concentration profile.
In some embodiments, to form the source contact structure, spacers are formed along sidewalls of the opening and the recess; and forming a source contact over the spacer and in contact with the N-doped region.
In some embodiments, the source contact comprises TiN.
The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The abstract section may set forth one or more, but not all exemplary embodiments of the disclosure as contemplated by the inventors, and is therefore not intended to limit the disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
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