阅读说明：本技术 一种电路老化时序分析方法及系统 (Circuit aging time sequence analysis method and system ) 是由 吴玉平 陈岚 于 2020-06-23 设计创作，主要内容包括：本公开提供了一种电路老化时序分析方法,包括：S1,获取电路中同构路径；S2,对同构路径进行分析,以获得同构路径的工作状态；S3,获得工作状态对延时的影响大小,并根据影响大小对同构路径按预设规则进行排序；S4,对部分同构路径进行时序分析,对另一部分同构路径复用已进行时序分析的时序分析结果。另一方面,本公开还提供了一种电路老化时序分析系统。本公开中的方案根据工作状态对路径延时的影响大小对同构的路径进行排序,根据路径的排序仅对部分路径进行时序分析,对其他未进行时序分析的部分路径复用已进行时序分析的路径的时序分析结果,在确保时序分析精度的基础上提供了集成芯片的时序分析速度。(The present disclosure provides a circuit aging timing analysis method, including: s1, obtaining a isomorphic path in the circuit; s2, analyzing the isomorphic path to obtain the working state of the isomorphic path; s3, obtaining the influence of the working state on the time delay, and sequencing isomorphic paths according to the influence according to a preset rule; and S4, performing time sequence analysis on part of isomorphic paths, and multiplexing the time sequence analysis results of the time sequence analysis on the other part of isomorphic paths. On the other hand, the disclosure also provides a circuit aging time sequence analysis system. The scheme in the disclosure sequences isomorphic paths according to the influence of the working state on the path delay, only performs time sequence analysis on partial paths according to the sequencing of the paths, multiplexes the time sequence analysis results of the paths which have been subjected to the time sequence analysis on other partial paths which are not subjected to the time sequence analysis, and provides the time sequence analysis speed of the integrated chip on the basis of ensuring the time sequence analysis precision.)

1. A circuit aging timing analysis method comprises the following steps:

s1, obtaining a isomorphic path in the circuit;

s2, analyzing the isomorphic path to obtain the working state of the isomorphic path;

s3, obtaining the influence of the working state on the time delay, and sequencing the isomorphic paths according to the influence according to a preset rule;

and S4, performing time sequence analysis on part of isomorphic paths, and multiplexing the time sequence analysis results of the time sequence analysis on the other part of isomorphic paths.

2. The circuit aging timing analysis method according to claim 1, the step S2 comprising:

performing IR analysis on the circuit to obtain the actual working voltage of each circuit unit on each timing path; and/or

Performing thermal analysis on the circuit to obtain an actual operating temperature of each device of each circuit unit on each timing path; and/or

And carrying out logic simulation analysis on the circuit to obtain characteristic parameters of each device so as to obtain the aging state of the device at the working life time point of the circuit design, wherein the characteristic parameters comprise the frequency of a device control signal, the time duty ratio and the voltage value corresponding to the high level.

3. The circuit aging timing analysis method according to claim 2, the obtaining of the magnitude of the influence of the operating state on the extension comprising:

obtaining the time delay drift caused by the deviation of the actual working voltage from the designed working voltage; and/or

Obtaining delay drift caused by the fact that the actual working temperature deviates from the design working temperature; and/or

Obtaining the time delay drift caused by the aging of the device deviating from the aging of the device 0.

4. The circuit aging timing analysis method according to claim 3, the preset rule comprising from small to large or from large to small.

5. The method of any one of claims 1 to 4, wherein the step S4 is specifically to perform timing analysis on the sequentially arranged isomorphic paths from one end to a critical path, and the timing analysis on the isomorphic paths not subjected to timing analysis multiplexes the timing analysis result of the critical path, wherein the critical path is the isomorphic path that meets the transition between the timing requirement and the timing requirement.

6. The method for analyzing aging timing of a circuit according to any one of claims 1 to 4, wherein the step S4 further comprises:

and carrying out time sequence analysis on the path at the middle position m of the isomorphic paths arranged in sequence.

7. The circuit aging timing analysis method according to claim 6, the step S4 comprising: when the sequence is from small to large, if the middle position m meets the time sequence requirement, multiplexing the 1 st to m-1 st time sequence paths with the time sequence analysis result of the m-th path, and performing time sequence analysis on the m +1 th to the last path in the sequence arrangement; and if the middle position m does not meet the time sequence requirement, multiplexing the time sequence analysis result of the mth path from the m +1 th path to the last path in the sequential arrangement, and performing time sequence analysis on the 1 st path to the m-1 st path.

8. The circuit aging timing analysis method according to claim 6, the step S4 further comprising: when the sequence is from large to small, if the middle position m meets the time sequence requirement, multiplexing the time sequence analysis result of the mth path from the m +1 th path to the last path in the sequence arrangement, and performing time sequence analysis on the 1 st path to the m-1 st path; and if the middle position m does not meet the time sequence requirement, multiplexing the analysis results of the mth time sequence path from the 1 st to the m-1 st time sequence path, and performing time sequence analysis on the (m + 1) th to the last in the sequence arrangement.

9. A circuit aging timing analysis system, comprising:

the acquisition module is used for acquiring isomorphic paths in the circuit;

the analysis module is used for analyzing the isomorphic path to obtain the working state of the isomorphic path;

the sorting module is used for obtaining the influence of the working state on the time delay and sorting the isomorphic paths according to the influence according to a preset rule;

and the processing module is used for carrying out time sequence analysis on part of isomorphic paths and multiplexing the time sequence analysis result which is subjected to the time sequence analysis on the other part of isomorphic paths.

10. The circuit aging timing analysis system of claim 9, the analysis module comprising:

the IR analysis module is used for carrying out IR analysis on the circuit so as to obtain the actual working voltage of each circuit unit on each timing path; and/or

The thermal analysis module is used for carrying out thermal analysis on the circuit so as to obtain the actual working temperature of each device of each circuit unit on each time sequence path; and/or

And the simulation analysis module is used for carrying out logic simulation analysis on the circuit to obtain the characteristic parameters of each device so as to further obtain the aging state of the device at the working life time point of the circuit design, wherein the characteristic parameters comprise the frequency of a device control signal, the time duty ratio and the voltage value corresponding to the high level.

Technical Field

The present disclosure relates to the field of circuit timing analysis technologies, and in particular, to a circuit aging timing analysis method and system.

Background

One of the conventional methods for accelerating SoC timing analysis is to detect homogeneous paths, that is, to detect whether the paths are homogeneous or not in a graph G (V, E) formed by respective circuit units and the connection relationships between the circuit units on two or more paths, perform timing analysis on only one of the paths in the homogeneous path, and multiplex the timing analysis result of one of the paths with the rest of the homogeneous paths. The influence of device aging on circuit timing is negligible, and when actual working voltages are consistent, the isomorphic detection isomorphic paths are adopted, and an analysis acceleration method is feasible by multiplexing the timing analysis result of one path. With the reduction of the process feature size of an integrated circuit, the aging of devices is obvious, the influence on the path time sequence is not negligible, and for different paths with the same structure and connection relation, the pressed and recovered histories of a plurality of devices corresponding to the different paths with the same structure are different due to different high and low level distributions of input signals in the working history process, so that the devices originally corresponding to the same path are in different aging states at the same time point, the paths with the same structure present different time sequences, and the existing time sequence analysis acceleration method for detecting the paths with the same structure and multiplexing a path time sequence analysis result becomes infeasible. For a circuit working at a wide variable voltage, aging accumulation caused by the circuit working at a higher voltage has a remarkable influence on the timing when the circuit is switched to a low voltage, particularly a sub-threshold voltage, and the conventional timing analysis acceleration method can cause obvious errors and even timing analysis errors. When the circuit works at a higher voltage, the device works in a super-threshold region, and the IR voltage drop on the power line causes the deviation of the actual working voltage and the designed working voltage of the circuit unit to have little influence on the delay deviation of the circuit unit, because the device works in a saturation region of an Ids-Vds relation curve, and the current in the region is slightly and linearly changed along with the increase of Vds. When the circuit works at a lower voltage, particularly a sub-threshold value, the device works in a sub-threshold value region, the IR voltage drop on the power line causes the deviation of the actual working voltage of the circuit unit from the designed working voltage to have a remarkable influence on the delay deviation of the circuit unit although the deviation is small, because the device works in the sub-threshold value region of the Ids-Vgs relation curve, and the current in the region has an exponential change relation with the working voltage. Therefore, in the existing analysis acceleration method for detecting isomorphic paths and multiplexing the timing analysis result of one path, the actual working voltages of circuit units on different paths are different due to different IR voltage drops on power lines, the delay difference of the low-voltage working path is obviously increased due to the actual working voltage difference, and the existing timing analysis acceleration method can cause obvious errors and even timing analysis errors.

Disclosure of Invention

Technical problem to be solved

The present disclosure provides a circuit aging timing analysis method and system, which at least solve the above technical problems.

(II) technical scheme

The present disclosure provides a circuit aging timing analysis method, including: s1, obtaining a isomorphic path in the circuit; s2, analyzing the isomorphic path to obtain the working state of the isomorphic path; s3, obtaining the influence of the working state on the time delay, and sequencing isomorphic paths according to the influence according to a preset rule; and S4, performing time sequence analysis on part of isomorphic paths, and multiplexing the time sequence analysis results of the time sequence analysis on the other part of isomorphic paths.

Optionally, step S2 includes: performing IR analysis on the circuit to obtain the actual working voltage of each circuit unit on each timing path; and/or performing thermal analysis on the circuit to obtain an actual operating temperature of each device of each circuit unit on each timing path; and/or carrying out logic simulation analysis on the circuit to obtain characteristic parameters of each device so as to obtain the aging state of the device at the working life time point of the circuit design, wherein the characteristic parameters comprise the frequency of a device control signal, the time duty ratio and the voltage value corresponding to the high level.

Optionally, obtaining the magnitude of the effect of the operating state on the extension comprises: obtaining the time delay drift caused by the deviation of the actual working voltage from the designed working voltage; and/or obtaining a delay drift caused by the deviation of the actual working temperature from the designed working temperature; and/or obtain a drift in delay caused by device aging away from device 0 aging.

Optionally, the preset rule comprises from small to large or from large to small.

Optionally, step S4 is to perform timing analysis on the sequentially arranged isomorphic paths from one end to a critical path, where the timing analysis of the isomorphic paths that are not subjected to timing analysis multiplexes the timing analysis result of the critical path, where the critical path is the isomorphic path that meets the timing requirement and does not meet the timing requirement.

Optionally, step S4 further includes: and carrying out time sequence analysis on the path at the middle position m of the isomorphic paths arranged in sequence.

Optionally, step S4 includes: when the sequence is from small to large, if the middle position m meets the time sequence requirement, multiplexing the 1 st to m-1 st time sequence paths with the time sequence analysis result of the m-th path, and performing time sequence analysis on the m +1 th to the last path in the sequence arrangement; and if the middle position m does not meet the time sequence requirement, multiplexing the time sequence analysis result of the mth path from the m +1 th path to the last path in the sequential arrangement, and performing time sequence analysis on the 1 st path to the m-1 st path.

Optionally, step S4 further includes: when the sequence is from big to small, if the middle position m meets the time sequence requirement, multiplexing the time sequence analysis result of the mth path from the (m + 1) th path to the last path in the sequence arrangement, and performing time sequence analysis on the 1 st path to the (m-1) th path; and if the middle position m does not meet the time sequence requirement, multiplexing the analysis results of the mth time sequence path from the 1 st to the m-1 st time sequence path, and performing time sequence analysis on the (m + 1) th to the last time sequence path in the sequence arrangement.

It should be noted here that the intermediate position may be a position of any one path between the first path and the last path in the sequentially arranged isomorphic paths. Ideally, the position of the path which is equidistant or nearly equidistant to the first path and the last path in the sequentially arranged isomorphic paths can be selected as the middle position, and the time sequence analysis of the sequentially arranged isomorphic paths is accelerated by combining bisection and analysis result multiplexing.

On the other hand, the present disclosure also provides a circuit aging timing analysis system, including: the acquisition module is used for acquiring isomorphic paths in the circuit; the analysis module is used for analyzing the isomorphic path to obtain the working state of the isomorphic path; the sorting module is used for obtaining the influence of the working state on the time delay and sorting the isomorphic paths according to the influence according to a preset rule; and the processing module is used for carrying out time sequence analysis on part of isomorphic paths and multiplexing the time sequence analysis result which is subjected to the time sequence analysis on the other part of isomorphic paths.

Optionally, the analysis module comprises: the IR analysis module is used for carrying out IR analysis on the circuit to obtain the actual working voltage of each circuit unit on each time sequence path; and/or a thermal analysis module for performing thermal analysis on the circuit to obtain an actual operating temperature of each device of each circuit unit on each timing path; and/or the simulation analysis module is used for carrying out logic simulation analysis on the circuit to obtain the characteristic parameters of each device so as to obtain the aging state of the device at the working life time point of the circuit design, wherein the characteristic parameters comprise the frequency of the device control signal, the time duty ratio and the voltage value corresponding to the high level.

(III) advantageous effects

The circuit aging time sequence analysis method and the system subdivide isomorphic paths according to path working states such as working voltage, working temperature and aging state of devices of circuit units on the circuit paths on the basis of detecting the isomorphic paths in the circuit, sort the isomorphic paths according to the influence of the working states on path delay, perform time sequence analysis on only partial paths according to the sort of the paths, multiplex time sequence analysis results of the paths which are subjected to time sequence analysis on other partial paths which are not subjected to time sequence analysis, and provide time sequence analysis speed of an integrated chip on the basis of ensuring time sequence analysis precision.

Drawings

FIG. 1 schematically illustrates a step diagram of a circuit aging timing analysis method according to an embodiment of the present disclosure;

FIG. 2 schematically illustrates a circuit operating state analysis flow diagram according to an embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow chart of a calculation of the magnitude of the effect of operating state on latency, according to an embodiment of the present disclosure;

FIG. 4 schematically illustrates a timing path ordered from small to large by the effect of operating state on path delay, according to an embodiment of the disclosure;

FIG. 5 schematically illustrates a timing path ordered by operating state to path delay impact from large to small according to an embodiment of the disclosure;

FIG. 6 schematically illustrates a schematic diagram of a timing analysis starting from a timing path with minimal impact when homogeneous paths are arranged from small to large according to an embodiment of the disclosure;

FIG. 7 schematically illustrates a schematic diagram of a timing analysis starting from a timing path with minimal impact when homogeneous paths are arranged from large to small according to an embodiment of the disclosure;

FIG. 8 schematically illustrates a schematic diagram of a circuit aging timing analysis method corresponding to FIG. 6, in accordance with an embodiment of the present disclosure;

FIG. 9 schematically illustrates a schematic diagram of a circuit aging timing analysis method corresponding to FIG. 7, in accordance with an embodiment of the present disclosure;

FIG. 10 schematically illustrates a schematic diagram of a timing analysis starting from a most influential timing path when homogeneous paths are arranged from small to large according to an embodiment of the disclosure;

FIG. 11 schematically illustrates a diagram of a timing analysis starting from a most influential timing path when homogeneous paths are arranged from large to small according to an embodiment of the disclosure;

FIG. 12 schematically illustrates a schematic diagram of a circuit aging timing analysis method corresponding to FIG. 10, in accordance with an embodiment of the present disclosure;

FIG. 13 schematically illustrates a schematic diagram of a circuit aging timing analysis method corresponding to FIG. 11, in accordance with an embodiment of the present disclosure;

FIG. 14 schematically illustrates a schematic diagram of starting a timing analysis from an intermediate isomorphic path when the isomorphic paths are arranged from small to large according to an embodiment of the disclosure;

FIG. 15 schematically illustrates a schematic diagram of starting a timing analysis from an intermediate isomorphic path when the isomorphic paths are arranged from large to small according to an embodiment of the disclosure;

FIG. 16 schematically illustrates a schematic diagram of a circuit aging timing analysis method when intermediate paths meet timing requirements and when the sequence of homogenous paths is arranged from small to large, according to an embodiment of the disclosure;

FIG. 17 schematically illustrates a schematic diagram of a circuit aging timing analysis method when intermediate paths do not meet timing requirements and when the sequence of homogenous paths is arranged from small to large, according to an embodiment of the disclosure;

FIG. 18 schematically illustrates a schematic diagram of a circuit aging timing analysis method when intermediate paths meet timing requirements and when the sequence of homogenous paths is arranged from large to small, according to an embodiment of the disclosure;

FIG. 19 schematically illustrates a schematic diagram of a circuit aging timing analysis method when intermediate paths do not meet timing requirements and when the sequence of homogenous paths is arranged from large to small, according to an embodiment of the disclosure.

Detailed Description

The method comprises the steps of subdividing isomorphic paths according to path working states such as working voltage of circuit units on the paths, device aging states, temperature at device positions and the like on the basis of detecting the passing paths in the circuit, sequencing the isomorphic paths according to the working states and the influence of path delay, performing time sequence analysis on only partial paths according to the sequencing of the paths, multiplexing time sequence analysis results of the paths subjected to the time sequence analysis on other partial paths not subjected to the time sequence analysis, and improving the time sequence analysis speed of an integrated circuit Chip (System-on-a-Chip, SoC) on the basis of ensuring the time sequence analysis precision.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

The present disclosure provides a circuit aging timing analysis method, as shown in fig. 1, including: s1, obtaining a isomorphic path in the circuit; s2, analyzing the isomorphic path to obtain the working state of the isomorphic path; s3, obtaining the influence of the working state on the time delay, and sequencing the isomorphic paths according to the influence according to a preset rule; and S4, performing time sequence analysis on the isomorphic paths meeting the preset conditions, and multiplexing the corresponding time sequence analysis results of the time sequence analysis on the isomorphic paths not meeting the preset conditions.

In S1, a homogenous path in the circuit is obtained.

The detection of homogeneous paths in a circuit may create graph G (V, E) based on the circuit cells/devices within the circuit and their connections. And discovering a time sequence path formed by each device and a front end circuit thereof based on a path search algorithm related to graph theory, wherein each time sequence path is a sub-G (V, E) of a sub-graph in G (V, E), carrying out isomorphism check on sub-graphs corresponding to different paths according to a sub-graph isomorphism algorithm, and if the two sub-graphs are isomorphism, the corresponding two time sequence paths are isomorphism. There are multiple groups of isomorphic timing paths in SoC, each group of isomorphic timing paths has two or more isomorphic timing paths, and their respective circuit units and their connection relationship between circuit units form a sub-graph sub g (V, E) which is isomorphic.

And S2, analyzing the isomorphic path to obtain the working state of the isomorphic path.

The working state in the embodiment of the present disclosure includes an actual working voltage of each circuit unit, a working temperature of each device, a frequency of a control signal, a time duty ratio, a voltage value corresponding to a high level, and the like. The operating state to obtain an isomorphic path may thus be, as shown in fig. 2:

analyzing voltage drop (IR) caused by parasitic resistance on a power line and a low-line network of the whole circuit to obtain the actual working voltage of each circuit unit on each timing path; and/or

Analyzing the heat distribution among the whole circuits, and determining the actual working temperature of each device in each circuit unit on each time sequence path; and/or

And carrying out logic simulation analysis covering typical application on the whole circuit, determining parameters such as frequency, time duty ratio, voltage value corresponding to high level and the like of a grid control signal of each device, particularly an MOS device, and calculating the aging state of the device at the designed service life time point of the whole circuit by combining the actual working temperature of the device obtained by the analysis.

And S3, obtaining the influence of the working state on the time delay, and sequencing the isomorphic paths according to the influence according to a preset rule.

Obtaining the influence of the operating state on the delay may include (as shown in fig. 3) step a1, and/or a2, and/or A3, where:

and step A1, acquiring the time delay drift caused by the deviation of the actual working voltage from the designed working voltage.

The estimated delay drift caused by the deviation of the actual working voltage from the designed working voltage can be calculated by adopting the following formula:

the influence of voltage deviation on the circuit unit time delay is obtained by substituting actual working voltage into the circuit unit time delay estimation model to calculate time delay, and the designed working voltage is substituted into the circuit unit time delay estimation model to calculate the time delay

The circuit unit delay estimation model can calculate the influence of voltage on delay according to the voltage value. And accumulating the influence of the voltage deviation on the time delay of all circuit units on the same time sequence path to obtain the influence of the voltage deviation on the time delay of the time sequence path.

Step a2, obtaining the delay drift caused by the deviation of the actual working temperature from the designed working temperature.

The following formula can be used to estimate the delay shift caused by the deviation of the actual operating temperature of the device from the designed operating temperature:

substituting the actual working temperature into the circuit unit delay estimation model to calculate the delay, substituting the design working temperature into the circuit unit delay estimation model to calculate the delay

The circuit unit delay estimation model can calculate the influence of temperature on delay according to the temperature value. And accumulating the influence of the temperature deviation on the time delay of all circuit units on the same time sequence path to obtain the influence of the temperature deviation on the time delay of the time sequence path.

Step a3, obtaining the time delay drift caused by the aging of the device deviating from the aging of the device 0.

The estimated time delay drift caused by the aging deviation of the device can be calculated by adopting the following formula:

substituting the actual aging state of the device into the circuit unit delay estimation model to calculate the delay, and substituting the 0 aging state of the device into the circuit unit delay estimation model to calculate the delay

The circuit unit delay estimation model can calculate the influence of circuit aging on delay according to the circuit aging state. And accumulating the influence of the aging deviation of the device on the time delay of all circuit units on the same time sequence path to obtain the influence of the aging deviation of the device on the time sequence path time delay.

And according to the influence of the actual working electrical offset on the time sequence path delay, the influence of the temperature offset on the time sequence path delay and the influence of the device aging offset on the time sequence path delay, the influence of the actual working voltage offset, the device working temperature offset and the aging state offset on the time sequence path delay is obtained. Or integrally estimating the delay drift caused by the deviation of the actual working voltage from the designed working voltage, the deviation of the actual working temperature of the device from the designed working temperature, the aging deviation of the device and the like, wherein the calculation formula is as follows:

substituting the actual working voltage, the actual working temperature and the actual aging state of the device into the circuit unit delay estimation model to calculate the delay, and substituting the design working voltage, the design working temperature and the 0 aging state of the device into the circuit unit delay estimation model to calculate the delay

And accumulating the influence of the voltage offset, the temperature offset and the aging state offset on the time delay of all circuit units on the same time sequence path to obtain the influence of the actual working voltage offset, the device working temperature offset and the aging state offset on the time delay of the time sequence path.

And sequencing the isomorphic paths according to a preset rule according to the influence, wherein the preset rule can be from small to large or from large to small. A sorting algorithm may be used to obtain homogeneous timing paths that are sorted from small to large (as shown in fig. 4) or from large to small (as shown in fig. 5) in terms of the effect of the path's operating state on the delay.

And S4, performing time sequence analysis on part of isomorphic paths, and multiplexing the time sequence analysis results of the time sequence analysis on the other part of isomorphic paths.

The sequential isomorphic paths can be subjected to time sequence analysis from one end to a critical path, and the time sequence analysis of the isomorphic paths which are not subjected to the time sequence analysis multiplexes the time sequence analysis result of the critical path, wherein the boundary path is the isomorphic path which meets the time sequence requirement and does not meet the time sequence requirement for conversion. For example, the method may start from a path with the smallest influence on the delay from the path operating state (as shown in fig. 6 and 7), as shown in fig. 6, when the isomorphic paths are arranged from small to large, the path with the smallest influence is the 1 st isomorphic path, as shown in fig. 7, when the isomorphic paths are arranged from large to small, the path with the smallest influence is the nth isomorphic path. Fig. 8 corresponds to fig. 6, when the timing analysis is performed from the 1 st isomorphic path, the 1 st to i-1 st paths meet the timing requirement, and the ith isomorphic path does not meet the timing requirement, the ith isomorphic path is a critical path, and the timing analysis result of the ith timing path is multiplexed from the (i + 1) th to the nth timing paths. Fig. 9 corresponds to fig. 7, when performing timing analysis from the nth isomorphic path, the (i + 1) th to nth isomorphic paths meet the timing requirement, and the ith isomorphic path does not meet the timing requirement, the ith isomorphic path is a critical path, and performs timing analysis on the (N) th to (i + 1) th timing paths, and multiplexes the timing analysis results of the ith timing path on the 1 st to (i-1) th timing paths.

The method can also start from the path with the largest influence on the delay from the path working state (as shown in fig. 10 and fig. 11), as shown in fig. 10, when the isomorphic paths are arranged from small to large, the path with the largest influence is the nth isomorphic path; as shown in fig. 11, when the isomorphic paths are arranged from large to small, the path with the largest influence is the 1 st isomorphic path. Fig. 12 corresponds to fig. 10, when the time sequence analysis is performed from the nth time sequence path, the (i + 1) th to nth isomorphic paths do not meet the time sequence requirement, and the ith isomorphic path meets the time sequence requirement, the ith isomorphic path is a critical path, and the time sequence analysis result of the ith time sequence path is multiplexed to the 1 st to i-1 st time sequence paths. Fig. 13 corresponds to fig. 11, when the timing analysis is performed from the 1 st timing path, the 1 st to i-1 st timing paths do not meet the timing requirement, and the i th isomorphic path meets the timing requirement, the i th isomorphic path is a critical path, and the timing analysis result of the i th timing path is multiplexed for the (i + 1) th to N th timing paths.

The time sequence analysis is carried out on part of isomorphic paths, and the time sequence analysis can be carried out from an intermediate position:

and carrying out time sequence analysis on the path at the middle position m of the isomorphic paths arranged in sequence. The route corresponding to the intermediate position m is selected from the routes arranged in sequence (see fig. 14 and fig. 15), for example, for N routes of the same structure, the intermediate position m may be selected as N/2 or m as N/2+1, the mth route is subjected to timing analysis, and the timing analysis of the 1 st to m-1 st routes and the timing analysis of the m +1 th to N th routes are determined according to whether the mth route satisfies the timing requirement.

When N homogeneous timing paths are arranged in order from small to large according to the influence of the path operating states on the delay, if the mth path meets the timing requirement (as shown in fig. 16), then: and subsequently, the time sequence analysis is not carried out on the 1 st to the m-1 st time sequence paths, the time sequence analysis result of the m path is multiplexed on the 1 st to the m-1 st time sequence paths, and the time sequence analysis is carried out on the (m + 1) th to the N time sequence paths. Otherwise, if the mth path does not satisfy the timing requirement (as shown in fig. 17), the timing analysis is not performed on the (m + 1) th to nth timing paths, and the (m + 1) th to nth timing paths multiplex the timing analysis result of the mth path, and the timing analysis is performed on the (1) th to (m-1) th timing paths.

When N isomorphic timing sequence paths are arranged from large to small according to the influence of the path working state on the time delay: if the mth path meets the timing requirement (as shown in fig. 18), then the timing analysis is not performed on the (m + 1) th to nth timing paths, the timing analysis result of the mth path is multiplexed on the (m + 1) th to nth timing paths, and the timing analysis is performed on the (1) th to (m-1) th timing paths. Otherwise, if the mth path does not satisfy the timing requirement (as shown in fig. 19), the timing analysis is not performed on the 1 st to the m-1 st timing paths, and the 1 st to the m-1 st timing paths multiplex the timing analysis result of the mth path, and the timing analysis is performed on the m +1 th to the nth timing paths.

It should be noted here that the intermediate position may be a position of any one path between the first path and the last path in the sequentially arranged isomorphic paths. Ideally, the position of the path which is equidistant or nearly equidistant to the first path and the last path in the sequentially arranged isomorphic paths can be selected as the middle position, and the time sequence analysis of the sequentially arranged isomorphic paths is accelerated by combining bisection and analysis result multiplexing.

Another aspect of the present disclosure further provides a circuit aging timing analysis system, including:

the obtaining module may, for example, perform step S1 shown in fig. 1 for obtaining a homogenous path in the circuit;

the analyzing module may, for example, execute step S2 shown in fig. 1, for analyzing the isomorphic path to obtain an operating state of the isomorphic path;

the sorting module may execute step S3 shown in fig. 1, for example, to obtain the magnitude of the influence of the working state on the delay, and sort the isomorphic paths according to a preset rule according to the magnitude of the influence;

the processing module may execute step S4 shown in fig. 1, for example, to perform timing analysis on a part of the isomorphic paths, and multiplex the timing analysis results of the timing analysis on another part of the isomorphic paths.

Wherein, the analysis module includes:

the IR analysis module is used for carrying out IR analysis on the circuit so as to obtain the actual working voltage of each circuit unit on each timing path; and/or

The thermal analysis module is used for carrying out thermal analysis on the circuit so as to obtain the actual working temperature of each device of each circuit unit on each time sequence path; and/or

And the simulation analysis module is used for carrying out logic simulation analysis on the circuit to obtain the characteristic parameters of each device so as to further obtain the aging state of the device at the working life time point of the circuit design, wherein the characteristic parameters comprise the frequency of a device control signal, the time duty ratio and the voltage value corresponding to the high level.

Obtaining the magnitude of the effect of the operating condition on the extension includes: obtaining the time delay drift caused by the deviation of the actual working voltage from the designed working voltage; and/or obtaining a delay drift caused by the deviation of the actual working temperature from the designed working temperature; and/or obtain a drift in delay caused by device aging away from device 0 aging.

The circuit aging time sequence analysis method and the system thereof subdivide isomorphic paths according to path working states (the working states are different from the logic states of circuit units/nodes on the paths) such as the working voltage, the working temperature and the aging state of devices on the circuit paths on the basis of detecting the isomorphic paths in the circuit, sort the isomorphic paths according to the influence of the working states on the path delay, only carry out time sequence analysis on partial paths according to the sorting of the paths, multiplex the time sequence analysis results of the paths which are subjected to the time sequence analysis on other partial paths which are not subjected to the time sequence analysis, and provide the time sequence analysis speed of an integrated chip on the basis of ensuring the time sequence analysis precision.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.