阅读说明：本技术 一种集成电路版图中遵循布线格点的交互式布线方法 (Interactive wiring method following wiring lattice points in integrated circuit layout ) 是由 黄晔 苏鸿昌 张亚东 李起宏 陆涛涛 *** 于 2020-05-22 设计创作，主要内容包括：一种集成电路版图中遵循布线格点的交互式布线方法,包括以下步骤：1)设置交互式布线参数；2)布线网格的水平和垂直间距一致时,将所有点链吸附到布线格点上；3)布线网格的水平和垂直间距不一致时,将所有点链吸附到布线格点或布线方向与网格线的交点上。本发明的集成电路版图中遵循布线格点的交互式布线方法,能够在正交或者45°布线方向上,满足布线格点的要求,从而保证交互式布线的规则性,最终满足制造要求。(An interactive routing method following routing grid points in an integrated circuit layout, comprising the steps of: 1) setting interactive wiring parameters; 2) when the horizontal and vertical distances of the wiring grids are consistent, adsorbing all point chains to the wiring grid points; 3) and when the horizontal and vertical distances of the wiring grids are inconsistent, adsorbing all the point chains to the points of the wiring grids or the intersection points of the wiring direction and the grid lines. The interactive wiring method following the wiring grid points in the integrated circuit layout can meet the requirements of the wiring grid points in the orthogonal or 45-degree wiring direction, thereby ensuring the regularity of interactive wiring and finally meeting the manufacturing requirements.)

1. An interactive routing method for following routing grid points in an integrated circuit layout, comprising the steps of:

1) setting interactive wiring parameters;

2) when the horizontal and vertical distances of the wiring grids are consistent, adsorbing all point chains to the wiring grid points;

3) and when the horizontal and vertical distances of the wiring grids are inconsistent, adsorbing all the point chains to the points of the wiring grids or the intersection points of the wiring direction and the grid lines.

2. The method of interactive routing in an integrated circuit layout following a routing grid according to claim 1, wherein said step 2) further comprises,

comparing the distances between the first wiring point and 4 grid points of the grid where the first wiring point is located, and adsorbing the first wiring point to the nearest grid point;

the horizontal and vertical distance differences between the second and subsequent wiring points and the previous point are compared, the wiring direction is determined, and the wiring direction is corrected to the nearest lattice point that coincides with the wiring direction.

3. The method of claim 2, further comprising revising the routing points to the nearest routing grid points based on a minimum distance rule.

4. The method of interactive routing in an integrated circuit layout following a routing grid according to claim 1, wherein said step 3) further comprises,

comparing the distances between the first wiring point and 4 grid points of the grid where the first wiring point is located, and adsorbing the first wiring point to the nearest grid point;

comparing the horizontal and vertical distance difference between the second wiring point and each subsequent wiring point and the previous point, determining the wiring direction, correcting the wiring direction to the nearest grid point consistent with the wiring direction, judging whether the wiring direction and the grid line are orthogonal wiring, and if so, adjusting the wiring point to the nearest wiring grid point; if not, the wiring points are adjusted to the intersection points of the wiring direction and the grid lines which are nearest.

5. The method of claim 4, wherein the adjusting the routing points to the closest intersection of the routing direction and the grid lines is based on a slope of the routing direction.

6. A computer-readable storage medium, on which a computer program is stored, which computer program, when running, performs the steps of the interactive routing method in an integrated circuit layout following a routing grid as claimed in any one of claims 1 to 5.

7. An interactive routing device for an integrated circuit layout following routing grid points, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the interactive routing method for an integrated circuit layout following routing grid points according to any one of claims 1 to 5.

Technical Field

The invention relates to the technical field of EDA (electronic design automation) design, in particular to an interactive wiring method in an integrated circuit layout.

Background

With the increasingly complex chip design and the progress of the process, the physical design faces more and more challenges, the ultra-deep submicron process is continuously perfected, the density of the chip is continuously improved under the reduction of the chip area, the wiring is used as a back-end node of the physical design in the ultra-large scale integrated circuit, and the wiring result plays a crucial role in the performance of the chip, so that the application of an EDA (electronic design automation) tool becomes an indispensable auxiliary means.

Routing refers to allocating metal lines between units, pins or other electronic devices to be connected in a physical design stage, and the metal lines of different connection relationships cannot overlap, in addition to which a large number of geometric constraints in the physical design are satisfied. With the maturity of the photolithography process, the improvement of the chip performance usually means the increase of the chip density, the wiring space is further reduced, the number of geometric constraints is continuously increased, and finally, the difficulty and complexity of wiring are greatly increased. This presents new challenges to EDA tools.

The conventional wiring method is based on Grid point (Grid) wiring. In the wiring process and the wiring layer conversion in the wiring process are performed on the basis of grid points, the Design Rule Check (DRC) is not passed without following the requirement of wiring grid points (off-grid), and the DRC Rule Check is usually performed after the layout is finished. Considering DRC rules at each stage of the design has a significant impact on the final chip stream, which also improves the performance of the chip.

In low-end processes, especially those above 16nm, layout design requirements are not too stringent and the wiring can be done at arbitrary Spacing (Spacing) on grid points. However, in the FinFET high-end process of 14nm or less, the specification of the trace becomes severe, the wiring density increases, and the physical design of the trace is considered to be better even if the space for the wiring is minimum.

In EDA high-end design tools, especially layout tools for high-end processes, it is necessary to verify whether each routing complies with the routing grid point requirements, which requires EDA vendors to develop interactive routers for high-end processes for chip manufacturing.

Disclosure of Invention

In order to solve the defects of the prior art, the invention aims to provide an interactive wiring method following wiring grid points in an integrated circuit layout, which meets the requirements of the wiring grid points in the orthogonal or 45-degree wiring direction, thereby ensuring the regularity of interactive wiring and finally meeting the manufacturing requirements.

In order to achieve the above object, the present invention provides an interactive wiring method following wiring lattice points in an integrated circuit layout, comprising the following steps:

1) setting interactive wiring parameters;

2) when the horizontal and vertical distances of the wiring grids are consistent, adsorbing all point chains to the wiring grid points;

3) and when the horizontal and vertical distances of the wiring grids are inconsistent, adsorbing all the point chains to the points of the wiring grids or the intersection points of the wiring direction and the grid lines.

Further, the step 2) further comprises,

comparing the distances between the first wiring point and 4 grid points of the grid where the first wiring point is located, and adsorbing the first wiring point to the nearest grid point;

the horizontal and vertical distance differences between the second and subsequent wiring points and the previous point are compared, the wiring direction is determined, and the wiring direction is corrected to the nearest lattice point that coincides with the wiring direction.

Further, the method comprises the step of secondarily correcting the wiring points to the nearest wiring grid points according to the minimum distance principle.

Further, the step 3) further comprises,

comparing the distances between the first wiring point and 4 grid points of the grid where the first wiring point is located, and adsorbing the first wiring point to the nearest grid point;

comparing the horizontal and vertical distance difference between the second wiring point and each subsequent wiring point and the previous point, determining the wiring direction, correcting the wiring direction to the nearest grid point consistent with the wiring direction, judging whether the wiring direction and the grid line are orthogonal wiring, and if so, adjusting the wiring point to the nearest wiring grid point; if not, the wiring points are adjusted to the intersection points of the wiring direction and the grid lines which are nearest.

Further, the adjusting of the wiring points to the intersections of the wiring directions and the grid lines closest to each other is performed by adjusting the wiring points to the intersections of the wiring directions and the grid lines closest to each other based on the slope of the wiring directions.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed, performs the steps of the interactive routing method following routing grid points in an integrated circuit layout as described above.

In order to achieve the above object, the present invention further provides an interactive wiring device for following wiring grid points in an integrated circuit layout, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the steps of the interactive wiring method for following wiring grid points in an integrated circuit layout as described above when executing the computer program.

The interactive wiring method following the wiring lattice points in the integrated circuit layout has the following beneficial effects:

1) in an equally spaced (pitch) routing grid, all routing points generated by the routing direction are at the intersection of the routing grid.

2) In an unequal interval (pitch) wiring grid, wiring points generated in orthogonal wiring directions are all on the intersection point of the wiring grid, and wiring points generated in 45-degree wiring directions are all on the intersection point of the wiring direction and the grid.

3) In the orthogonal or 45-degree wiring direction, the requirement of wiring lattice points is met, so that the regularity of interactive wiring is ensured, and finally the manufacturing requirement is met.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of an interactive routing method following routing grid points in an integrated circuit layout according to the present invention;

FIG. 2 is a schematic diagram of an interactive routing parameter setting interface according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of orthogonal routing results for equal x-axis and y-axis spacing of a routing grid according to the present invention;

FIG. 4 is a schematic diagram of the results of 45 degree routing with equal spacing of the x-axis and y-axis of the routing grid according to the present invention;

FIG. 5 is a schematic diagram of orthogonal wiring results when the x-axis and y-axis of the wiring grid are not equally spaced according to the present invention;

FIG. 6 is a schematic diagram of 45 degree wiring results when the x-axis and y-axis of the wiring grid are not equally spaced according to the present invention;

FIG. 7 is a diagram illustrating an interactive routing result according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Fig. 1 is a flowchart of an interactive routing method following routing grid points in an integrated circuit layout according to the present invention, and the following describes in detail the interactive routing method following routing grid points in an integrated circuit layout according to the present invention with reference to fig. 1.

First, in step 101, a wiring grid of a layer for wiring is detected. In this step, a layer wiring grid for wiring is automatically detected.

In step 102, it is determined whether the distances between the x-axis and the y-axis of the wiring grid are consistent, and if so, the process jumps to step 103, and if not, the process jumps to step 104.

In step 103, all dot chains are attached to the wiring grid dots. In this step, fig. 3 is a schematic diagram of orthogonal wiring results when the x-axis and the y-axis of the wiring grid according to the present invention are equally spaced, fig. 4 is a schematic diagram of 45 ° wiring results when the x-axis and the y-axis of the wiring grid according to the present invention are equally spaced, and as shown in fig. 3 and fig. 4, when the horizontal and vertical pitches (pitch) of the wiring grid points are the same, all the dot chains, the generated orthogonal wiring or 45 ° diagonal wiring are on the wiring grid points.

Preferably, the distances between the first wiring point and the 4 grid points on the grid are compared, and the wiring point is adsorbed to the nearest grid point. In the step, when the distances between the x axis and the y axis of the wiring grid are consistent, the first wiring point is compared with the distances between the first wiring point and the 4 wiring grid points of the grid, and the first wiring point is automatically adsorbed to the nearest point.

Preferably, the wiring direction is determined by comparing the horizontal and vertical distance differences between the 2 nd to n th points and the previous point, adjusted to the closest point consistent with the wiring direction, and secondarily corrected to the closest wiring grid point according to the minimum distance principle. In the step, the point after the first correction is respectively subjected to vertical grid line mode correction and horizontal grid line mode correction to obtain a point which is equal to the x coordinate or the y coordinate of the previous point, a horizontal distance difference deltax between the previous point and the current point, and a vertical distance difference deltay, wherein if the deltax is greater than the deltay, the wiring direction is horizontal, and the y coordinate of the current point is adjusted to be consistent with the y coordinate of the previous point, which is the closest point with the wiring direction. The closest point is not necessarily on a grid point, so a quadratic adjustment is required, if the current routing direction is horizontal, the quadratic adjustment of the closest point can only adjust the x-coordinate to the nearest vertical grid.

At step 104, all the dot chains are adsorbed onto the intersection of the grid dots or wiring directions and the grid lines.

FIG. 5 is a schematic diagram of orthogonal wiring results when the x-axis and y-axis of the wiring grid are not equally spaced according to the present invention,

fig. 6 is a schematic diagram showing the 45 ° wiring result when the x-axis and y-axis of the wiring grid are not equidistant according to the present invention, and as shown in fig. 5 and 6, when the horizontal vertical spacing (pitch) of the wiring grid points is not uniform, the first point generated by the orthogonal wiring is on the intersection point of the grid, the rest of the point chains are on the intersection point of the grid or the intersection point with the grid line, and the 45 ° diagonal wiring is attached to at least one grid line.

Preferably, the distances between the first wiring point and the 4 grid points on the grid are compared, and the first wiring point is adsorbed to the nearest grid point. In the step, when the distances between the x axis and the y axis of the wiring grid are inconsistent, the first wiring point is compared with the distances between the first wiring point and the 4 wiring grid points of the grid, and the first wiring point is automatically adsorbed to the nearest point.

Preferably, the difference between the horizontal distance and the vertical distance between the 2 nd to the nth point and the previous point is compared, the wiring direction is determined, the wiring direction is absorbed to the closest point consistent with the wiring direction, whether the wiring direction and the grid line are orthogonal wiring is judged, and if yes, the wiring direction and the grid line are secondarily adjusted to the closest wiring grid point; if not, the inclination of the wiring direction is adjusted to the intersection point where the wiring direction is closest to the grid line.

Preferably, in step 103 and step 104, horizontal gridline mode (SnapY) adsorption or vertical gridline mode (SnapX) adsorption or 45 ° wiring direction adsorption is performed on the wiring points. In this step, SnapY, SnapX45 ° wiring mode support is required to complete the interactive results of step 103 and step 104. Adsorbing to the nearest horizontal grid line mode (SnaPy) only corrects the value of the y-axis coordinate; adsorption to the nearest vertical gridline mode (SnapX) corrects only the value of the x-axis coordinate; by adsorbing to the 45 ° wiring direction pattern, whether the wiring slope k is 1 or-1 is calculated.

The following describes a method for interactive routing in an integrated circuit layout, which follows routing grid points, in accordance with an embodiment of the present invention.

(1) And starting an interactive wiring command, and setting interactive wiring parameters through an interactive wiring parameter setting interface.

Fig. 2 is a schematic diagram of an interactive wiring parameter setting interface according to an embodiment of the invention, and as shown in fig. 2, a user can set an interactive wiring parameter in the interactive wiring parameter setting interface in fig. 2.

(2) Clicking the mouse to select a starting point required to perform a wiring operation or a starting object to be connected.

(3) Double-clicking generates an interactive routing result, as shown in FIG. 7.

The invention provides an interactive wiring method following wiring grid points in an integrated circuit layout, wherein in a high-end process, the following wiring grid points are important methods of an EDA tool in a physical design wiring stage process, and the EDA tool is not aligned to grid points (off-grid) which do not meet manufacturing requirements.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed, performs the steps of the interactive routing method following routing grid points in an integrated circuit layout as described above.

In order to achieve the above object, the present invention further provides an interactive wiring device for following wiring grid points in an integrated circuit layout, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to execute the above steps of the interactive wiring method for following wiring grid points in an integrated circuit layout.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.