阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 沓掛静香 松本浩史 斋藤广翔 于 2019-07-26 设计创作，主要内容包括：实施方式提供一种能够实现高集成化及高速化的半导体装置。实施方式的半导体装置具备：衬底；第1绝缘层及第2绝缘层,在与衬底的表面交叉的第1方向上与衬底并排；空隙层,设置在第1绝缘层及第2绝缘层之间；以及第1接点电极及第2接点电极,在第1方向上延伸并在与第1方向交叉的第2方向上排列。第1接点电极及第2接点电极分别具备：第1方向的一端部；第1方向的另一端部；以及第1部分,设置在一端部与另一端部之间且第2方向上的宽度大于一端部的第2方向上的宽度及另一端部的第2方向上的宽度。第1接点电极的第1部分及第2接点电极的第1部分设置在空隙层。(Embodiments provide a semiconductor device capable of realizing high integration and high speed. The semiconductor device of the embodiment includes: a substrate; a 1 st insulating layer and a 2 nd insulating layer which are arranged side by side with the substrate in a 1 st direction intersecting with a surface of the substrate; a void layer provided between the 1 st insulating layer and the 2 nd insulating layer; and a 1 st contact electrode and a 2 nd contact electrode extending in the 1 st direction and arranged in a 2 nd direction intersecting the 1 st direction. The 1 st contact electrode and the 2 nd contact electrode are respectively provided with: one end part in the 1 st direction; the other end in the 1 st direction; and a 1 st portion provided between the one end portion and the other end portion and having a width in the 2 nd direction larger than a width in the 2 nd direction of the one end portion and a width in the 2 nd direction of the other end portion. The 1 st part of the 1 st contact electrode and the 1 st part of the 2 nd contact electrode are provided in the void layer.)

1. A semiconductor device includes:

a substrate;

a 1 st insulating layer and a 2 nd insulating layer which are arranged side by side with the substrate in a 1 st direction intersecting a surface of the substrate;

a void layer disposed between the 1 st insulating layer and the 2 nd insulating layer; and

a 1 st contact electrode and a 2 nd contact electrode extending in the 1 st direction and arranged in a 2 nd direction intersecting the 1 st direction; and is

The 1 st contact electrode and the 2 nd contact electrode each include: one end portion in the 1 st direction; the other end in the 1 st direction; and a 1 st portion which is provided between the one end portion and the other end portion, and has a width in the 2 nd direction which is larger than a width in the 2 nd direction of the one end portion and a width in the 2 nd direction of the other end portion;

the 1 st portion of the 1 st contact electrode and the 1 st portion of the 2 nd contact electrode are provided in the void layer.

2. The semiconductor device according to claim 1, wherein

The 1 st contact electrode and the 2 nd contact electrode each include a 2 nd portion which is provided on the substrate side of the 1 st portion and has a width in the 2 nd direction larger than the one end portion and the other end portion, and

gaps are provided between the 2 nd portion of the 1 st contact electrode and the 1 st insulating layer, and between the 2 nd portion of the 2 nd contact electrode and the 1 st insulating layer.

3. The semiconductor device according to claim 1, wherein

The 1 st contact electrode includes:

a 1 st contact portion extending in the 1 st direction; and

a 2 nd contact portion extending in the 1 st direction and farther from the substrate than the 1 st contact portion; and is

The other end of the 1 st contact portion and one end of the 2 nd contact portion are provided in the void layer.

4. A semiconductor device includes:

a substrate;

a 1 st insulating layer juxtaposed to the substrate in a 1 st direction intersecting a surface of the substrate; and

a 1 st contact electrode extending in the 1 st direction; and is

The 1 st contact electrode includes: one end portion in the 1 st direction; the other end in the 1 st direction; and a 1 st portion that is provided between the one end portion and the other end portion and has a width in a 2 nd direction intersecting the 1 st direction that is larger than a width in the 2 nd direction of the one end portion and a width in the 2 nd direction of the other end portion;

a gap is provided between the 1 st portion of the 1 st contact electrode and the 1 st insulating layer.

5. The semiconductor device according to claim 4, wherein

The other end of the 1 st contact electrode is farther from the substrate than the one end, and

a 1 st layer is provided between the other end portion of the 1 st contact electrode and the 1 st insulating layer,

a portion of the layer 1 is exposed to the void.

6. The semiconductor device according to any one of claims 1 to 5, wherein

The width in the 2 nd direction of the 1 st portion of the 1 st contact electrode is the largest or greatest width in the 2 nd direction of the 1 st contact electrode.

Technical Field

The present embodiment relates to a semiconductor device.

Background

With the high integration of semiconductor devices, the use of contacts having a large aspect ratio has been increasing. For example, as a semiconductor memory device, a three-dimensional memory in which a plurality of memory cells are provided in a direction intersecting with a substrate is known. In a three-dimensional memory, the aspect ratio of a contact for connecting a memory cell array to a peripheral circuit, a contact for constituting a peripheral circuit, or the like is increasing.

Disclosure of Invention

Drawings

Fig. 1 is an equivalent circuit diagram showing a schematic configuration of a semiconductor memory device according to embodiment 1.

Fig. 2 is a schematic plan view of the semiconductor memory device.

FIG. 3 is a schematic cross-sectional view of the construction shown in FIG. 2, taken along line A-A' and viewed in the direction of the arrows.

Fig. 4 is a schematic enlarged view of a portion indicated by B of fig. 2.

FIG. 5 is a schematic cross-sectional view of the construction shown in FIG. 4, taken along the line C-C' and viewed in the direction of the arrows.

Fig. 6 is a schematic cross-sectional view illustrating the contact CS.

Fig. 7 is a schematic cross-sectional view illustrating the contact CS.

Fig. 8 is a schematic cross-sectional view of the peripheral circuit PCA of embodiment 1.

Fig. 9 to 17 are schematic cross-sectional views showing a method of manufacturing the peripheral circuit PCA.

Fig. 18 is a schematic cross-sectional view of the memory cell array MCA of embodiment 2.

Fig. 19 is a schematic sectional view of the peripheral circuit PCB of embodiment 2.

Fig. 20 to 29 are schematic cross-sectional views showing a method of manufacturing the peripheral circuit PCB.

Fig. 30 is a schematic cross-sectional view of the peripheral circuit PCC of embodiment 3.

Fig. 31 to 38 are schematic cross-sectional views illustrating a method of manufacturing the peripheral circuit PCC.

Fig. 39 is a schematic cross-sectional view of the peripheral circuit PCD of embodiment 4.

Fig. 40 is a schematic cross-sectional view of the peripheral circuit PCE of embodiment 5.

Fig. 41 to 46 are schematic cross-sectional views showing a method of manufacturing a peripheral circuit PCE.

Fig. 47 is a schematic sectional view of the peripheral circuit PCF of embodiment 6.

Fig. 48 is a schematic cross-sectional view of the peripheral circuit PCG of embodiment 7.

Fig. 49 is a schematic cross-sectional view of the peripheral circuit PCH of the 8 th embodiment.

Fig. 50 is a schematic sectional view of the peripheral circuit PCI according to embodiment 9.

Fig. 51 is a schematic cross-sectional view of the peripheral circuit PCJ of embodiment 10.

Fig. 52 is a schematic cross-sectional view of the peripheral circuit PCK according to embodiment 11.

Fig. 53 is a schematic sectional view for explaining another embodiment.

The embodiment provides a semiconductor device capable of realizing high integration and high speed.

A semiconductor device according to one embodiment includes: a substrate; a 1 st insulating layer and a 2 nd insulating layer which are arranged side by side with the substrate in a 1 st direction intersecting with a surface of the substrate; a void layer provided between the 1 st insulating layer and the 2 nd insulating layer; and a 1 st contact electrode and a 2 nd contact electrode extending in the 1 st direction and arranged in a 2 nd direction intersecting the 1 st direction. The 1 st contact electrode and the 2 nd contact electrode are respectively provided with: one end part in the 1 st direction; the other end in the 1 st direction; and a 1 st portion provided between the one end portion and the other end portion and having a width in the 2 nd direction larger than a width in the 2 nd direction of the one end portion and a width in the 2 nd direction of the other end portion. The 1 st part of the 1 st contact electrode and the 1 st part of the 2 nd contact electrode are provided in the void layer.

A semiconductor device according to another embodiment includes: a substrate; a 1 st insulating layer juxtaposed to the substrate in a 1 st direction intersecting a surface of the substrate; and a 1 st contact electrode extending in the 1 st direction. The 1 st contact electrode includes: one end part in the 1 st direction; the other end in the 1 st direction; and a 1 st portion that is provided between the one end portion and the other end portion and has a width in a 2 nd direction intersecting the 1 st direction that is larger than a width in the 2 nd direction of the one end portion and a width in the 2 nd direction of the other end portion. A gap is provided between the 1 st portion of the 1 st contact electrode and the 1 st insulating layer.