Semiconductor memory device with a plurality of memory cells
阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 安彦尚文 吉原正浩 于 2019-07-05 设计创作，主要内容包括：实施方式提供一种高品质的半导体存储装置。实施方式的半导体存储装置(1)包括：存储单元(MT_n)及存储单元(MT_m),连接于字线(WL_sel)；第1位线(BL),连接于存储单元(MT_n)；第2位线(BL),连接于存储单元(MT_m)；以及控制电路；所述控制电路包括：第1晶体管(Tr5),设置于第1位线(BL)与节点(SEN_n)之间,包括电连接于节点(SEN_n)的一端；第2晶体管(Tr5),设置于第2位线(BL)与节点(SEN_m)之间,包括电连接于节点(SEN_m)的一端；第2晶体管(Tr5)以与第1晶体管(Tr5)相邻的方式设置；所述控制电路构成为：一面将第1晶体管(Tr5)与第2晶体管(Tr5)的其中一个设为断开状态,一面将另一个设为接通状态。(Embodiments provide a high-quality semiconductor memory device. A semiconductor memory device (1) according to an embodiment includes: memory cells (MT _ n) and (MT _ m) connected to word lines (WL _ sel); a 1 st Bit Line (BL) connected to the memory cell (MT _ n); a 2 nd Bit Line (BL) connected to the memory cell (MT _ m); and a control circuit; the control circuit includes: a 1 st transistor (Tr5) disposed between the 1 st Bit Line (BL) and the node (SEN _ n), and including one end electrically connected to the node (SEN _ n); a 2 nd transistor (Tr5) provided between the 2 nd Bit Line (BL) and the node (SEN _ m), and including one end electrically connected to the node (SEN _ m); the 2 nd transistor (Tr5) is disposed adjacent to the 1 st transistor (Tr 5); the control circuit is configured to: one of the 1 st transistor (Tr5) and the 2 nd transistor (Tr5) is turned off, and the other is turned on.)
1. A semiconductor memory device includes:
a 1 st memory cell and a 2 nd memory cell connected to a 1 st word line;
a 1 st bit line connected to the 1 st memory cell;
a 2 nd bit line connected to the 2 nd memory cell; and
a control circuit including a 1 st node and a 2 nd node, a 1 st transistor and a 2 nd transistor, the 1 st transistor being disposed between the 1 st bit line and the 1 st node and including one end electrically connected to the 1 st node, the 2 nd transistor being disposed between the 2 nd bit line and the 2 nd node and including one end electrically connected to the 2 nd node;
the 2 nd transistor is provided adjacent to the 1 st transistor;
the control circuit is configured to:
electrically connecting the 1 st node to the 1 st bit line while turning off the 2 nd transistor and turning on the 1 st transistor, and sensing the 1 st node electrically connected to the 1 st bit line;
the 1 st transistor is turned off and the 2 nd transistor is turned on, so that the 2 nd node is electrically connected to the 2 nd bit line, and the 2 nd node electrically connected to the 2 nd bit line is sensed.
2. The semiconductor storage device according to claim 1, wherein the control circuit is configured to: turning on the 1 st transistor while maintaining the potential of the 2 nd node; the 2 nd transistor is turned on while the potential of the 1 st node is maintained.
3. The semiconductor storage device according to claim 1, wherein the control circuit is configured to: turning on the 1 st transistor while supplying a 1 st voltage to the 2 nd node; the 2 nd transistor is turned on while the 1 st voltage is supplied to the 1 st node.
4. The semiconductor storage device according to claim 3, wherein the control circuit is configured to: the 1 st transistor is turned on after the 1 st node is charged with the 1 st voltage, and the 2 nd transistor is turned on after the 2 nd node is charged with the 1 st voltage.
5. The semiconductor storage device according to claim 1, wherein the control circuit is provided with:
a 3 rd transistor including a 1 st terminal electrically connected to the 1 st node and a 2 nd terminal supplied with a 1 st voltage; and
a 4 th transistor including a 1 st terminal electrically connected to the 2 nd node and a 2 nd terminal supplied with the 1 st voltage; and is
The structure is as follows: turning the 1 st transistor on while turning the 3 rd transistor off and turning the 4 th transistor on; the 2 nd transistor is turned on while the 4 th transistor is turned off and the 3 rd transistor is turned on.
6. The semiconductor memory device according to claim 1, wherein the control circuit is configured to sense the 1 st node and the 2 nd node at different timing points.
7. The semiconductor memory device according to claim 1, wherein an active region where the 1 st transistor is provided with a space from an active region where the 2 nd transistor is provided.
8. The semiconductor memory device according to claim 1, further comprising:
a 3 rd memory cell connected to the 1 st word line; and
a 3 rd bit line connected to the 3 rd memory cell;
the control circuit further includes a 3 rd node and a 5 th transistor, wherein the 5 th transistor is disposed between the 3 rd bit line and the 3 rd node and includes one end electrically connected to the 3 rd node;
the 5 th transistor is provided adjacent to the 1 st transistor;
the control circuit is configured to: the 1 st transistor is turned off and the 5 th transistor is turned on, so that the 3 rd node is electrically connected to the 3 rd bit line, and the 3 rd node electrically connected to the 3 rd bit line is sensed.
9. The semiconductor memory device according to claim 8, wherein the 5 th transistor, the 1 st transistor, and the 2 nd transistor are provided adjacent to the 5 th transistor, the 1 st transistor, and the 2 nd transistor in this order along a 1 st direction.
10. A semiconductor memory device includes:
a 1 st memory cell and a 2 nd memory cell connected to a 1 st word line;
a 1 st bit line connected to the 1 st memory cell;
a 2 nd bit line connected to the 2 nd memory cell;
a 1 st sense amplifier connected to the 1 st bit line and including a 1 st node, and configured to sense the 1 st node after the 1 st node is electrically connected to the 1 st bit line;
a 2 nd sense amplifier connected to the 2 nd bit line and including a 2 nd node, and configured to sense the 2 nd node after the 2 nd node is electrically connected to the 2 nd bit line; and
and a control circuit configured to electrically connect the 1 st node to the 1 st bit line while maintaining a potential of the 2 nd node with a 2 nd voltage after charging the 1 st node with a 1 st voltage, and to electrically connect the 2 nd node to the 2 nd bit line while maintaining a potential of the 1 st node with the 2 nd voltage after charging the 2 nd node with the 1 st voltage.
11. The semiconductor storage device according to claim 10, wherein a magnitude of the 1 st voltage is equal to a magnitude of the 2 nd voltage.
Technical Field
Background
As a semiconductor memory device, a NAND (Not AND) type flash memory is known.
Disclosure of Invention
Drawings
Fig. 1 is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device according to
Fig. 2 is a block diagram showing an example of the configuration of the semiconductor memory device according to
Fig. 3 is a diagram showing an example of a circuit configuration of a memory cell array in the semiconductor memory device according to
Fig. 4 is a diagram showing an example of a part of a cross-sectional structure of a memory cell array in the semiconductor memory device according to
Fig. 5 is a diagram showing an example of threshold voltage distribution formed by memory cell transistors in the semiconductor memory device according to
Fig. 6 is a block diagram showing an example of the configuration of a sense amplifier module in the semiconductor memory device according to
Fig. 7 is a diagram showing an example of a part of the circuit configuration of the sense amplifier module in the semiconductor memory device according to
Fig. 8 is a block diagram showing an example of distribution of control signals to be supplied to the sense amplifier units in the semiconductor memory device according to
Fig. 9 is a diagram showing an example of the layout of a sense amplifier unit and transistors in the sense amplifier unit in the semiconductor memory device according to
Fig. 10 is a diagram showing an example of a part of a cross-sectional structure of the semiconductor memory device according to
Fig. 11 is a timing chart showing an example of temporal changes in voltages applied to various circuit components of the sense amplifier unit used in the read operation in the semiconductor memory device according to
Fig. 12 is a timing chart showing an example of temporal changes in voltages applied to various circuit components of a certain sense amplifier unit, which are used in a read operation in the semiconductor memory device of the comparative example.
Embodiments relate to a semiconductor memory device.
- 上一篇：一种医用注射器针头装配设备
- 下一篇：半导体存储器装置