阅读说明：本技术 阻变存储器、阻变存储器芯片及其制备方法 (Resistive random access memory, resistive random access memory chip and preparation method thereof ) 是由 孙雯 李辛毅 高滨 唐建石 吴华强 钱鹤 于 2020-06-17 设计创作，主要内容包括：一种阻变存储器、阻变存储芯片及其制备方法。该阻变存储器包括晶体管和阻变存储元件。该晶体管包括第一源漏极、栅极、第二源漏极以及分别与第一源漏极、栅极和第二源漏极电连接的第一源漏极连接电极、栅极连接电极和第二源漏极连接电极。该阻变存储元件包括第一电极、第二电极以及在第一电极和第二电极之间的阻变层,第一电极通过第二源漏极连接电极与第二源漏极电连接。第一源漏极连接电极、栅极连接电极、第二源漏极连接电极和阻变存储元件沿第一方向并列排布在同一平面上。由此,该阻变存储器可以实施限流作用下的原位透射电镜观测实验,并且得到高可靠性的实验数据。(A resistive random access memory, a resistive random access memory chip and a preparation method thereof are provided. The resistive random access memory includes a transistor and a resistive random access memory element. The transistor comprises a first source drain electrode, a grid electrode, a second source drain electrode, a first source drain electrode connecting electrode, a grid electrode connecting electrode and a second source drain electrode connecting electrode which are respectively and electrically connected with the first source drain electrode, the grid electrode and the second source drain electrode. The resistive memory element comprises a first electrode, a second electrode and a resistive layer between the first electrode and the second electrode, wherein the first electrode is electrically connected with the second source drain through a second source drain connecting electrode. The first source-drain connection electrode, the gate connection electrode, the second source-drain connection electrode, and the resistive memory element are arranged in parallel on the same plane along a first direction. Therefore, the resistive random access memory can be used for carrying out in-situ transmission electron microscope observation experiments under the current limiting effect, and high-reliability experimental data can be obtained.)

1. A resistance change memory comprising:

the transistor comprises a first source drain electrode, a grid electrode, a second source drain electrode, a first source drain electrode connecting electrode, a grid electrode connecting electrode and a second source drain electrode connecting electrode, wherein the first source drain electrode, the grid electrode and the second source drain electrode are respectively and electrically connected with the first source drain electrode, the grid electrode and the second source drain electrode; and

a resistance change memory element including a first electrode, a second electrode, and a resistance change layer between the first electrode and the second electrode, the first electrode being electrically connected to the second source-drain via the second source-drain connection electrode,

the first source-drain connection electrode, the gate connection electrode, the second source-drain connection electrode and the resistive random access memory element are arranged in parallel on the same plane along a first direction.

2. The resistance change memory according to claim 1, wherein the transistor further comprises a ground electrode and a ground electrode connection electrode electrically connected to the ground electrode, and

the ground electrode connecting electrode, the first source/drain electrode connecting electrode, the gate electrode connecting electrode, the second source/drain electrode connecting electrode and the resistive random access memory element are arranged in parallel on the same plane along a first direction.

3. The resistance change memory according to claim 2, wherein, in the first direction, the ground connection electrode, the first source-drain connection electrode, the gate connection electrode, the second source-drain connection electrode, and the resistance change memory element are arranged in this order, and a distance between the ground connection electrode and the first source-drain connection electrode, a distance between the first source-drain connection electrode and the gate connection electrode, a distance between the gate connection electrode and the second source-drain connection electrode, and a distance between the second source-drain connection electrode and the resistance change memory element are 2 to 4 μm.

4. The resistive random access memory of claim 1, wherein the transistor further comprises a ground electrode and a ground electrode connection trace electrically connected to the ground electrode, and

the ground electrode connecting wire, the first source-drain electrode connecting electrode, the gate electrode connecting electrode, the second source-drain electrode connecting electrode and the resistive random access memory element are arranged on the same plane.

5. The resistance change memory according to claim 4, wherein the first source-drain connection electrode, the gate connection electrode, the second source-drain connection electrode, and the resistance change memory element are arranged in this order in the first direction, and a distance between the first source-drain connection electrode and the gate connection electrode, a distance between the gate connection electrode and the second source-drain connection electrode, and a distance between the second source-drain connection electrode and the resistance change memory element are 2 to 4 μm.

6. The resistive-switching memory according to any one of claims 1 to 5, wherein the resistive-switching memory has a length of 15 to 25 micrometers, a width of 2 to 3 micrometers, and a height of 10 to 15 micrometers,

the length direction is the first direction, and the width direction and the height direction are both perpendicular to the first direction.

7. A resistive memory chip, comprising:

a substrate;

the resistive-switching memory according to claim 1;

a plurality of conductive lines; and

the resistive random access memory and the plurality of wires are arranged on the substrate, the same plane on which the first source-drain connecting electrode, the gate connecting electrode, the second source-drain connecting electrode and the resistive random access memory element of the resistive random access memory are arranged is parallel to the surface of the substrate, and the same plane is parallel to the surface of the substrate

One ends of the plurality of wires are respectively and electrically connected with the first source-drain electrode connecting electrode, the gate electrode connecting electrode and the second electrode of the resistive random access memory element one by one, and the other ends of the plurality of wires are used for connecting a driving circuit.

8. The resistive random access memory chip according to claim 7, wherein the transistor of the resistive random access memory further comprises an earth electrode and an earth electrode connection electrode or an earth electrode connection trace electrically connected to the earth electrode, the earth electrode connection electrode or the earth electrode connection trace being electrically connected to one end of one of the plurality of wires.

9. The resistance change memory chip according to claim 7, wherein end portions of the first source-drain connection electrode, the gate connection electrode, and the second electrode of the resistance change memory element have exposed connection terminals, respectively, to be electrically connected to one ends of the plurality of wires.

10. The resistance change memory chip according to claim 9, further comprising a metal protection layer disposed on a side where the connection terminal is located,

the metal protection layer comprises a first cutting groove and a second cutting groove, the first cutting groove is located between the connecting end of the first source drain electrode and the connecting end of the grid electrode connecting electrode, the second cutting groove is located between the connecting end of the grid electrode connecting electrode and the connecting end of the second electrode of the resistive random access memory element, and therefore the first source drain electrode, the grid electrode connecting electrode and the resistive random access memory element are mutually insulated.

Technical Field

The embodiment of the disclosure relates to a resistive random access memory, a resistive random access memory chip and a preparation method thereof.

Background

The resistive random access memory is a volatile or nonvolatile memory for recording and storing data information based on resistance value change, has the characteristics of high speed and low power consumption, and can realize a storage function in a small size. The resistive random access memory has good compatibility with the traditional CMOS circuit manufacturing process. In view of these advantages, the resistive random access memory becomes especially important in the context of the current intelligent products and the explosive development of the internet of things.

Disclosure of Invention

At least one embodiment of the present disclosure provides a resistive random access memory. The resistive random access memory includes: the transistor comprises a first source drain electrode, a grid electrode, a second source drain electrode, a first source drain electrode connecting electrode, a grid electrode connecting electrode and a second source drain electrode connecting electrode, wherein the first source drain electrode, the grid electrode and the second source drain electrode are respectively and electrically connected with the first source drain electrode, the grid electrode and the second source drain electrode; and the resistive memory element comprises a first electrode, a second electrode and a resistive layer between the first electrode and the second electrode, wherein the first electrode is electrically connected with the second source drain through a second source drain connecting electrode, and the first source drain connecting electrode, the grid connecting electrode, the second source drain connecting electrode and the resistive memory element are arranged on the same plane in parallel along a first direction.

For example, in the resistive random access memory provided in at least one embodiment of the present disclosure, the transistor further includes a ground electrode and a ground electrode connection electrode electrically connected to the ground electrode, and the ground electrode connection electrode, the first source/drain connection electrode, the gate connection electrode, the second source/drain connection electrode, and the resistive random access memory element are arranged in parallel on the same plane along the first direction.

For example, in the resistive random access memory provided in at least one embodiment of the present disclosure, in the first direction, the ground electrode connection electrode, the first source-drain electrode connection electrode, the gate electrode connection electrode, the second source-drain electrode connection electrode, and the resistive random access memory element are sequentially arranged, and a distance between the ground electrode connection electrode and the first source-drain electrode connection electrode, a distance between the first source-drain electrode connection electrode and the gate electrode connection electrode, a distance between the gate electrode connection electrode and the second source-drain electrode connection electrode, and a distance between the second source-drain electrode connection electrode and the resistive random access memory element are 2 to 4 micrometers.

For example, in the resistive random access memory provided in at least one embodiment of the present disclosure, the transistor further includes a ground electrode and a ground electrode connection trace electrically connected to the ground electrode, and the ground electrode connection trace is arranged on the same plane as the first source/drain connection electrode, the gate connection electrode, the second source/drain connection electrode, and the resistive random access memory element.

For example, in the resistive random access memory provided in at least one embodiment of the present disclosure, in the first direction, the first source-drain connection electrode, the gate connection electrode, the second source-drain connection electrode, and the resistive random access memory element are sequentially arranged, and a distance between the first source-drain connection electrode and the gate connection electrode, a distance between the gate connection electrode and the second source-drain connection electrode, and a distance between the second source-drain connection electrode and the resistive random access memory element are 2 to 4 micrometers.

For example, in the resistive random access memory provided in at least one embodiment of the present disclosure, a length of the resistive random access memory is 15 to 25 micrometers, a width of the resistive random access memory is 2 to 3 micrometers, and a height of the resistive random access memory is 10 to 15 micrometers, where a direction in which the length is located is a first direction, and directions in which the width and the height are both located are perpendicular to the first direction.

At least one embodiment of the present disclosure provides a resistive random access memory chip. The resistive random access memory chip comprises: a substrate; at least one embodiment of the present disclosure provides a resistive random access memory; a plurality of conductive lines; the resistive random access memory and the plurality of wires are arranged on the substrate, the same plane where the first source-drain electrode connecting electrode, the gate electrode connecting electrode, the second source-drain electrode connecting electrode and the resistive random access memory element of the resistive random access memory are arranged is parallel to the surface of the substrate, one ends of the plurality of wires are respectively and electrically connected with the first source-drain electrode connecting electrode, the gate electrode connecting electrode and the second electrode of the resistive random access memory element one by one, and the other ends of the wires are used for being connected with the driving circuit.

For example, in the resistive random access memory chip provided in at least one embodiment of the present disclosure, the transistor of the resistive random access memory further includes a ground electrode and a ground electrode connection electrode or a ground electrode connection trace electrically connected to the ground electrode, and the ground electrode connection electrode or the ground electrode connection trace is electrically connected to one end of one of the plurality of wires.

For example, in the resistive random access memory chip provided in at least one embodiment of the present disclosure, end portions of the first source-drain connection electrode, the gate connection electrode, and the second electrode of the resistive random access memory element respectively have an exposed connection terminal to be electrically connected to one end of the plurality of wires.

For example, in the resistive random access memory chip provided in at least one embodiment of the present disclosure, the resistive random access memory chip further includes a metal protection layer disposed on the side where the connection end is located, where the metal protection layer includes a first cut groove located between the connection end of the first source-drain connection electrode and the connection end of the gate connection electrode, and a second cut groove located between the connection end of the gate connection electrode and the connection end of the second electrode of the resistive random access memory element, so that the first source-drain connection electrode, the gate connection electrode, and the resistive random access memory element are insulated from each other.

For example, in the resistive random access memory chip provided in at least one embodiment of the present disclosure, an observation window exposing the resistive random access memory element is further included for observing the resistive layer, wherein a thickness of the resistive random access memory element exposed by the observation window is 10 to 50 nanometers in a direction perpendicular to the substrate.

For example, at least one embodiment of the present disclosure provides a method for manufacturing a resistive random access memory chip, including: providing a substrate and a resistive random access memory provided as at least one embodiment of the present disclosure; arranging a resistive random access memory on a substrate; and forming a plurality of wires on the substrate, wherein one ends of the plurality of wires are electrically connected with the first source-drain electrode connecting electrode, the grid electrode connecting electrode and the second electrode of the resistive random access memory element one by one, and the other ends of the plurality of wires are used for connecting a driving circuit.

For example, in a manufacturing method of a resistive random access memory chip provided in at least one embodiment of the present disclosure, a transistor of the resistive random access memory further includes a ground electrode and a ground electrode connection electrode electrically connected to the ground electrode or a ground electrode connection trace, and the manufacturing method further includes: and electrically connecting the grounding electrode connecting electrode or the grounding electrode connecting trace with one end of one of the plurality of wires.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, before disposing a resistive random access memory on a substrate, the method further includes: the resistive random access memory is pre-processed on the intermediate medium, and then transferred to be disposed on the substrate using the intermediate medium.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, the preprocessing includes: exposed connection terminals are formed at end portions of the first source-drain connection electrode, the gate connection electrode, and the second electrode of the resistance change memory element, respectively, to be electrically connected to one ends of the plurality of wires.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, forming exposed connection ends at ends of a first source-drain connection electrode, a gate connection electrode, and a second electrode of a resistive random access memory element, respectively includes: forming a hole exposing the first source-drain connection electrode, the gate connection electrode and the second electrode of the resistive memory element at the end portions of the first source-drain connection electrode, the gate connection electrode and the second electrode of the resistive memory element, and filling a conductive material in the hole to form a connection terminal.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, the preprocessing further includes: and forming a metal protection layer on the side where the connecting end is located, and forming a first cutting groove between the connecting end of the first source-drain electrode connecting electrode and the connecting end of the grid electrode connecting electrode and a second cutting groove between the connecting end of the grid electrode connecting electrode and the second electrode of the resistive random access memory element in the metal protection layer so as to insulate the first source-drain electrode connecting electrode, the grid electrode connecting electrode and the resistive random access memory element from each other.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, the method further includes: the resistance change memory element is thinned in a direction perpendicular to the substrate to form an observation window exposing the resistance change memory element for observing the resistance change layer, and the thickness of the resistance change memory element is thinned to 10 to 50 nm.

For example, in a method for manufacturing a resistive random access memory chip provided in at least one embodiment of the present disclosure, a focused ion beam microscope is used to perform preprocessing and form an observation window.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.

Fig. 1A is a schematic cross-sectional view of a resistive random access memory provided in at least one embodiment of the present disclosure.

Fig. 1B is a schematic top view of a resistive random access memory according to at least one embodiment of the present disclosure.

Fig. 2A is a schematic cross-sectional view of a resistive random access memory provided in at least one embodiment of the present disclosure.

Fig. 2B is a schematic top view of a resistive random access memory according to at least one embodiment of the present disclosure.

Fig. 3A is a schematic cross-sectional view of a resistive random access memory provided in at least one embodiment of the present disclosure.

Fig. 3B is a schematic top view of a resistive random access memory according to at least one embodiment of the present disclosure.

Fig. 4 is a schematic plan view of a resistive random access memory chip provided in at least one embodiment of the present disclosure.

Fig. 5 is a schematic plan view of a resistive random access memory chip according to at least one embodiment of the present disclosure.

Fig. 6 is a schematic plan view of a resistive random access memory chip provided in at least one embodiment of the present disclosure.

Fig. 7 is a schematic plan view of a resistive random access memory chip according to at least one embodiment of the present disclosure.

Fig. 8 is a schematic plan view of a resistive random access memory chip according to at least one embodiment of the present disclosure.

Fig. 9 is a schematic plan view of a resistive random access memory chip provided in at least one embodiment of the present disclosure.

Fig. 10 is a schematic flow chart of a manufacturing method corresponding to the resistive random access memory chip in fig. 4.

Fig. 11 is a schematic flow chart of a manufacturing method corresponding to the resistive random access memory chip in fig. 5 and 6.

Fig. 12 is a schematic flow chart of a manufacturing method corresponding to the resistive random access memory chip in fig. 7.

Fig. 13 is a schematic flow chart of a manufacturing method corresponding to the resistance random access memory chip in fig. 8.

Fig. 14 is a schematic flow chart of a manufacturing method corresponding to the resistance random access memory chip in fig. 9.

Fig. 15 is a diagram of an effect of a current limiting test of a resistive random access memory chip provided in at least one embodiment of the present disclosure of fig. 9.

Fig. 16 is a schematic flow chart of a macro-fabrication method of a resistive random access memory chip for in-situ transmission electron microscope observation according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In order to further improve the structure and performance of the resistive random access memory and promote wider application of the resistive random access memory, the working state and the working mechanism of the resistive random access memory can be deeply and carefully studied. For example, an in-situ transmission electron microscope can be used for observing the microstructure evolution process of the resistive random access memory in a working state, so that a valuable experimental basis is provided for the structure and performance improvement of the resistive random access memory.

However, the conventional resistive random access memory cannot be placed on a sample stage of an in-situ transmission electron microscope for in-situ transmission electron microscope observation experiments due to the overlarge size. Moreover, since the silicon nitride film window and the electrical test chip (hereinafter referred to as a driving circuit or a driving chip) used in the in-situ transmission electron microscope observation experiment are very expensive, it is not practical to adapt to the size of the observed resistive random access memory by adjusting the sample stage of the in-situ transmission electron microscope itself.

In the experimental process, the inventor of the present disclosure finds that the resistive random access memory currently available for the in-situ transmission electron microscope observation experiment lacks a current limiting means, has poor durability, and the like. For example, in order to meet the requirements of in-situ transmission electron microscope observation experiments on resistive random access memory samples, the structure of the resistive random access memory needs to be simplified and modified in the experimental process, for example, in order to measure the performance parameters of the electrodes and the resistive layer, a sandwich structure of a top electrode, the resistive layer and a bottom electrode of the resistive random access memory is modified from a stacked state to an unfolded state, so that the structure and the working mechanism of the resistive random access memory for experiments are different from those of the actually applied resistive random access memory, and the reliability of experimental data is low. In addition, the resistive random access memory adopted in the experiment has no current limiting means, and after the resistive random access memory is subjected to establishment and reset operations for a small number of times, a resistive layer of the resistive random access memory is easily damaged by high current in a low-resistance state, so that repeated cycle testing of the resistive random access memory is difficult to realize.

At least one embodiment of the disclosure provides a resistive random access memory, a resistive random access memory chip and a preparation method of the resistive random access memory chip. The resistive random access memory comprises a transistor and a resistive random access memory element, wherein the transistor comprises a first source drain electrode, a grid electrode, a second source drain electrode, a first source drain electrode connecting electrode, a grid electrode connecting electrode and a second source drain electrode connecting electrode which are respectively and electrically connected with the first source drain electrode, the grid electrode and the second source drain electrode; the resistance change memory element comprises a first electrode, a second electrode and a resistance change layer between the first electrode and the second electrode, wherein the first electrode is electrically connected with the second source drain through a second source drain connecting electrode, and the first source drain connecting electrode, the grid connecting electrode, the second source drain connecting electrode and the resistance change memory element are arranged on the same plane in parallel along a first direction.

Each structure of the resistive random access memory provided by at least one embodiment of the present disclosure is arranged on the same plane, so that the resistive random access memory has a relatively thin size, which is convenient for in-situ transmission electron microscope observation, and a transistor in the resistive random access memory has a current limiting function, so that the durability of the resistive random access memory can be improved, the resistive random access memory cannot be disabled even if being established and reset for multiple times, and time cost and economic cost are saved. And the working mechanism of the resistive random access memory is the same as that of the practically applied resistive random access memory, so that high-reliability experimental data can be obtained by in-situ observation of the resistive random access memory, and the high-approximation simulation of the working state of the practically applied resistive random access memory is realized.

Hereinafter, a resistance change memory chip, and methods of manufacturing the same provided by embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

Fig. 1A is a schematic cross-sectional view of a resistive random access memory 100 provided in at least one embodiment of the present disclosure. Fig. 1B is a schematic top view of a resistive random access memory 100 provided in at least one embodiment of the present disclosure, and fig. 1A is taken along an AA' line in fig. 1B, for example.

Referring to fig. 1A, a resistance change memory 100 includes a transistor 101 and a resistance change memory element 102. The transistor 101 includes a first source-drain 1011, a gate 1013, a second source-drain 1015, and a first source-drain connection electrode 1012, a gate connection electrode 1014, and a second source-drain connection electrode 1016 electrically connected to the first source-drain 1011, the gate 1013, and the second source-drain 1015, respectively. For example, the transistor 101 further includes an active layer including a channel region and a doped region, the active layer and the gate electrode 1013 being spaced apart by an insulating layer.

The resistive-switching memory element 102 includes a first electrode (e.g., a bottom electrode of the resistive-switching memory element) 1021, a second electrode (e.g., a top electrode of the resistive-switching memory element) 1023, and a resistive layer 1022 between the first electrode 1021 and the second electrode 1023. The first electrode 1021 is electrically connected to the second source/drain 1015 via the second source/drain connection electrode 1016. In addition, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive memory element 102 are arranged in parallel on the same plane along the first direction (for example, the longitudinal direction of the resistive memory 100, the horizontal direction in the drawing). That is, the resistance change memory 100 has a cross section in which the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistance change memory element 102 are arranged in parallel in one direction.

It should be noted that, in the embodiment of the present disclosure, an arrangement order of the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive memory element 102 is not limited, and fig. 1A illustrates that the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive memory element 102 are sequentially arranged along the first direction, but the embodiment of the present disclosure is not limited thereto, and the arrangement order of the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive memory element 102 may be adjusted as needed.

For example, the first source/drain 1011, the gate 1013, and the second source/drain 1015 are electrodes formed of a metal material such as copper, aluminum, or titanium, or an alloy material, and the first source/drain connection electrode 1012, the gate connection electrode 1014, and the second source/drain connection electrode 1016 are metal pillars made of a metal material such as tungsten or cobalt, or an alloy material. The transistor 101 is, for example, a thin film transistor.

For example, in some embodiments, the end portion of the second source-drain connection electrode 1016 may be provided with an intermediate connection electrode 1017, and the first electrode 1021 is electrically connected to the second source-drain 1015 through the intermediate connection electrode 1017, so that the first electrode 1021 is electrically connected to the second source-drain 1015. The intermediate connection electrode 1017 is made of a metal material such as copper, aluminum, or titanium, or an alloy material.

For example, in some embodiments, as shown in fig. 1A, in the length direction of the resistive random access memory 100, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive random access memory element 102 are sequentially arranged in parallel on the same plane. A pitch P1 between the first source-drain connection electrode 1012 and the gate connection electrode 1014, a pitch P2 between the gate connection electrode 1014 and the second source-drain connection electrode 1016, and a pitch P3 between the second source-drain connection electrode 1016 and the resistance change memory element 102 are 2 to 4 micrometers, for example, 2 micrometers, 3 micrometers, or 4 micrometers. With reference to fig. 1B, in a top view of the resistive random access memory 100, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016 and the resistive random access memory element 102 are approximately arranged on the same straight line, so that the resistive random access memory 100 may have a smaller width.

For example, the length L of the resistive random access memory 100 may be 15 to 25 micrometers, for example, 20 micrometers, the width W of the resistive random access memory 100 may be 2 to 3 micrometers, for example, 2.5 micrometers, and the height H of the resistive random access memory 100 may be 10 to 15 micrometers, for example, 10 micrometers, so that the width of the resistive random access memory 100 is very small, and the resistive random access memory can be placed on a sample stage of an in-situ transmission electron microscope, so as to be used for in-situ observation.

Fig. 2A is a schematic cross-sectional view of a resistive random access memory 100' provided in at least one embodiment of the present disclosure. Fig. 2B is a schematic top view of a resistive random access memory 100 'provided in at least one embodiment of the present disclosure, and fig. 2A is taken along an AA' line in fig. 2B, for example.

Referring to fig. 2A, the resistance change memory 100 'is different from the resistance change memory 100 shown in fig. 1A in that the transistor 101 thereof further includes a ground electrode 1019 and a ground electrode connection electrode (e.g., a tungsten metal pillar or a cobalt metal pillar) 1018 electrically connected to the ground electrode 1019, and the ground electrode connection electrode 1018 is arranged in parallel on the same plane along a first direction (e.g., a length direction of the resistance change memory 100', a horizontal direction in the drawing) together with the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistance change memory element 102. That is, the resistance change memory 100' has a cross section in which the ground connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistance change memory element 102 are arranged in parallel in one direction.

For example, the ground electrode 1019 may be an electrode formed of a metal material or an alloy material such as copper, aluminum, titanium, or the like, and the ground electrode connection electrode 1018 may be a metal pillar made of a metal material or an alloy material such as tungsten, cobalt, or the like.

As shown in fig. 2A, in the longitudinal direction (horizontal direction in the figure) of the resistance change memory 100', a first ground connection electrode 1018, a first source-drain connection electrode 1012, a gate connection electrode 1014, a second source-drain connection electrode 1016, and the resistance change memory element 102 are arranged in parallel in this order. A pitch P4 between the ground connection electrode 1018 and the first source-drain connection electrode 1012, a pitch P1 between the first source-drain connection electrode 1012 and the gate connection electrode 1014, a pitch P2 between the gate connection electrode 1014 and the second source-drain connection electrode 1016, and a pitch P3 between the second source-drain connection electrode 1016 and the resistance change memory element 102 are 2 to 4 micrometers, for example, 2 micrometers, 3 micrometers, or 4 micrometers.

With reference to fig. 2B, in a top view of the resistive random access memory 100', the first ground connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive random access memory element 102 are approximately arranged on the same straight line, so that the resistive random access memory 100 may have a smaller width.

For example, the length L of the resistive random access memory 100 ' may be 15 to 25 micrometers, for example, 20 micrometers, the width W of the resistive random access memory 100 ' may be 2 to 3 micrometers, for example, 2.5 micrometers, and the height H of the resistive random access memory 100 ' may be 10 to 15 micrometers, for example, 10 micrometers, so that the width of the resistive random access memory 100 is small, and the resistive random access memory can be placed on a sample stage of an in-situ transmission electron microscope, so as to be used for in-situ observation.

In the embodiment of the present disclosure, the pitches P4, P1, and P2 may ensure that when the resistive random access memory 100' is prepared as a resistive random access memory chip (such as the resistive random access memory chip 10 described in fig. 4 below) for an in-situ transmission electron microscope observation experiment by, for example, a Focused Ion Beam (FIB) microscope, the first source and drain, the gate, and the second source and drain are not mutually short-circuited due to outward diffusion of a deposition layer when a wire is deposited in an FIB preparation process. Meanwhile, the P3 may reserve a required processing region for processing an observation window for observing a microstructure evolution process of the resistance change layer due to penetration of an electron beam at the position of the resistance change memory element 102, so as to avoid damage to the working structure of the second source/drain 1015 of the transistor when the resistance change memory element is thinned by methods such as FIB.

The intermediate connection electrode 1017 is provided so that a gap P3 is reserved between the second source-drain connection electrode 1016 and the resistance change memory element 102. However, it should be understood by those skilled in the art that when the resistive random access memory element 102 is used for other purposes besides in-situ transmission electron microscopy, or when a processing region is not required to be reserved in the manufacturing process, the distance P3 between the second source-drain connection electrode 1016 and the resistive random access memory element 102 is not required to exist, and the first electrode 1021 of the resistive random access memory element 102 may be directly electrically connected to the second source-drain connection electrode 1016.

Fig. 3A is a schematic cross-sectional view of a resistive random access memory 100 ″ provided in at least one embodiment of the present disclosure. Fig. 3B is a schematic top view of the resistive random access memory 100 ″ provided in at least one embodiment of the present disclosure. Fig. 3B is a cross-section taken along line AA' in fig. 3B, for example.

Referring to fig. 3A, the resistance change memory 100 ″ is different from the resistance change memory 100 shown in fig. 1A in that the transistor 101 further includes a ground electrode 1019 and a ground electrode connection trace 1010 electrically connected to the ground electrode, and the ground electrode connection trace 1010 is arranged on the same plane as the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistance change memory element 102.

As shown in fig. 3A, the resistance change memory 100 ″ is different from the resistance change memory 100' shown in fig. 2A in that a ground connection trace 1010 is connected to a ground 1019 in the resistance change memory 100 ″ instead of including the ground connection electrode 1018. For example, after the substrate of the resistance change memory 100 ″ may be thinned to expose the ground level 1019, the ground trace 1010 may be formed at the ground 1019 by deposition or sputtering to be electrically connected to the ground 1019.

For example, the ground connection trace 1010 may be a wire formed of a metal material such as platinum, copper, aluminum, or an alloy material.

Further, as shown in fig. 3A, in a first direction (e.g., a length direction, a horizontal direction in the drawing) of the resistance change memory 100 ″, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistance change memory element 102 are arranged in parallel in this order, and a pitch P1 between the first source-drain connection electrode 1012 and the gate connection electrode 1014, a pitch P2 between the gate connection electrode 1014 and the second source-drain connection electrode 1016, and a pitch P3 between the second source-drain connection electrode 1016 and the resistance change memory element 102 are 2 to 4 micrometers, for example, 2 micrometers, 3 micrometers, or 4 micrometers.

For example, the design principles of the pitches P1, P2, and P3 are similar to those of fig. 2A, and are not described herein again. The difference from fig. 2A is that the ground trace 1010 has no limitation of the layout pitch. This is because, as described above, the ground trace 1010 may be formed by deposition or sputtering at the ground 1019 after the substrate of the resistance change memory 100 ″ may be subjected to thinning processing to expose the ground 1019, so there is no possibility of a short circuit between the ground trace 1010 and the first source drain 1012.

With reference to fig. 3B, in a top view of the resistive random access memory 100 ″, the first ground connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the resistive random access memory element 102 are approximately arranged on the same straight line, so that the resistive random access memory 100 ″ can have a smaller width.

For example, the length L of the resistive random access memory 100 "may be 15 to 25 micrometers, for example, 20 micrometers, the width W of the resistive random access memory 100" may be 2 to 3 micrometers, for example, 2.5 micrometers, and the height H of the resistive random access memory 100 "may be 10 to 15 micrometers, for example, 10 micrometers, so that the width of the resistive random access memory 100" is very small, and the resistive random access memory can be placed on a sample stage of an in-situ transmission electron microscope, so as to be used for in-situ observation.

As shown in fig. 1A and 1B, fig. 2A and 2B, and fig. 3A and 3B, the resistive random access memory 100, 100', 100 ″ has a small width, and can be directly disposed on a sample stage of an in-situ transmission electron microscope, and can be matched with the size of the sample stage of the in-situ transmission electron microscope for in-situ observation. Of course, in other embodiments, the resistive random access memory 100, 100', 100 ″ may have other dimensions according to different sample or experimental requirements through the above configuration, and the embodiments of the present disclosure are not limited thereto. These dimensions may be changed or modified according to actual needs.

In addition, in the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one pole of the transistor is described as a first source/drain, and the other pole of the transistor is described as a second source/drain. For example, in fig. 1A and 1B, fig. 2A and 2B, and fig. 3A and 3B, when the first source-drain 1011 is a source, the second source-drain 1015 is a drain, and when the first source-drain 1011 is a drain, the second source-drain 1015 is a source. In practice, the second source-drain 1015 electrically connected to the resistive memory element 102 is a source or a drain depending on convenience in a manufacturing process or actual needs. Herein, for simplicity and to avoid unnecessary repetition of the description, the first source-drain 1011 is described as a source and the second source-drain 1015 is described as a drain.

The resistive random access memory which can be used for in-situ transmission electron microscope observation is described above with reference to fig. 1A to 3B. Wherein, the pitches P4, P1 and P2 are designed to be 2 to 4 micrometers to ensure that the source, the gate and the drain are not mutually short-circuited due to the out diffusion of the deposited layer when the conductive wire is deposited by using a Focused Ion Beam (FIB) microscope; the pitch P3 is designed to be 2 to 4 micrometers to reserve a processing area required when an observation window (for example, the observation window 600 shown in fig. 9) for observing the microstructure evolution process of the resistive layer occurring due to the penetration of an electron beam therethrough is processed at the position of the resistive memory element 102, so that the working structure of the second source and drain 1015 of the transistor is prevented from being damaged when the resistive memory element 102 is thinned by the FIB method; and the ground electrode connecting electrode 1018, the first source-drain electrode 1012, the gate electrode 1014, the second source-drain electrode 1016, and the resistive memory element 102 are arranged in the same plane, so that the size of the whole resistive memory device 102 is thinned, and the size requirement of a sample platform of a general in-situ transmission electron microscope is met. Through these improvements, a resistive random access memory having a transistor with a current limiting function and the same operation mechanism as that of a practically applied resistive random access memory is obtained. The resistive random access memory is prepared into a resistive random access memory chip, and can be used for in-situ observation.

A resistive random access memory chip including the resistive random access memory and a manufacturing method corresponding to the resistive random access memory chip are described below with reference to fig. 4 to 13.

Fig. 4 is a schematic plan view of a resistive random access memory chip 10 provided in at least one embodiment of the present disclosure.

Referring to fig. 4, the resistance change memory chip 10 includes a substrate (e.g., a silicon nitride thin film window) 300, a resistance change memory 100 as shown in fig. 1A and 1B, and a plurality of wires (e.g., platinum wires) 200. The resistive random access memory 100 and the plurality of conductive wires 200 are disposed on the substrate 300, a first source-drain connection electrode (for example, a tungsten metal pillar connected to a source) 1012, a gate connection electrode 1014, a second source-drain connection electrode (for example, a tungsten metal pillar connected to a drain) 1016, and the resistive random access memory element 102 of the resistive random access memory 100 are arranged on a same plane parallel to the surface of the substrate 300, one end of each of the plurality of conductive wires 200 is electrically connected to the first source-drain connection electrode 1012, the gate connection electrode 1014, and a second electrode (for example, a top electrode) 1023 of the resistive random access memory element 102 one by one, and the other end of each of the plurality of conductive wires 200 is used for connecting a driving circuit (for example, a driving chip or an electrical. The driving circuit may apply voltages to the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode of the resistive random access memory element 102 through the plurality of wires 200, so as to drive the resistive random access memory to operate under the current limiting effect of the transistor.

As shown in fig. 4, the resistive random access memory chip 10 includes a substrate 300, which may be a silicon nitride thin film window, which can withstand high temperatures >1000 ℃ in-situ transmission electron microscopy experiments, withstand harsh deposition and chemical conditions, provide a desirable balance in imaging resolution and mechanical strength, and can provide a flat, insulating, hydrophobic plane. The driving circuit can be a driving chip or an electrical testing chip which has a driving function on driving the electrodes of the resistive random access memory chip in an in-situ transmission electron microscope observation experiment, and the driving circuit is provided with driving electrodes which correspond to the electrodes of the resistive random access memory chip one by one. At present, a driving circuit (or a driving chip) and silicon nitride film windows with various window sizes and thicknesses can be directly obtained through the market.

Fig. 10 is a flowchart of a manufacturing method corresponding to the resistance change memory chip 10 in fig. 4.

Referring to fig. 10, in step S100, a substrate 300 and the resistance change memory 100 as illustrated in fig. 1A and 1B are provided. In step S200, the resistance change memory 100 is disposed on a substrate (e.g., a silicon nitride thin film window) 300. For example, the back surface of the resistance change memory 100 may be flattened and then placed over the substrate 300, so that the back surface of the resistance change memory 100 is attached to the substrate 300. In step S300, a plurality of conductive lines 200 are formed on the substrate 300, one ends of the plurality of conductive lines 200 are electrically connected to the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode 1023 of the resistance change memory element 200 one by one, and the other ends of the plurality of conductive lines 200 are used for connecting a driving circuit. For example, the conductive line may be formed on the substrate 300 by deposition, sputtering, or the like. The material of the conducting wire can adopt platinum or other metals or metal alloys meeting the requirements. If platinum is used as the material for depositing the platinum wire, the conduction effect can be achieved when the deposition thickness of the platinum wire is about 300 nanometers.

Fig. 5 is a schematic diagram of a resistive random access memory chip 10' provided in at least one embodiment of the present disclosure. Fig. 6 is a schematic diagram of a resistive random access memory chip 10 ″ provided in at least one embodiment of the present disclosure.

As shown in fig. 5 and 6, the difference from fig. 4 is that, instead of the resistance change memory 100 shown in fig. 1A and 1B, the resistance change memory chip 10 'shown in fig. 5 includes the resistance change memory 100' shown in fig. 2A and 2B, and the resistance change memory chip 10 ″ shown in fig. 6 includes the resistance change memory 100 "shown in fig. 3A and 3B.

Referring to fig. 5 and 6, in the resistance change memory chip 10' and the resistance change memory chip 10 ″, the transistor 101 further includes an earth electrode 1019 and an earth electrode connection electrode 1018 or an earth electrode connection trace 1010 electrically connected to the earth electrode, and the earth electrode connection electrode 1018 or the earth electrode connection trace 1010 is electrically connected to one end of one of the plurality of wires 200.

Fig. 11 is a flowchart of a manufacturing method corresponding to the resistance change memory chip 10' or 10 ″ of fig. 5 and 6.

Referring to FIG. 11, steps S100-S300 therein are the same as steps S100-S300 shown in FIG. 10. The difference is that since the resistance change memory chip 10 'or 10 ″ includes a ground electrode, additionally, in step S300a, a ground connection electrode 1018 (with respect to the resistance change memory chip 10' shown in fig. 5) or a ground trace 1010 (with respect to the resistance change memory chip 10 shown in fig. 6) is electrically connected to one end of one of the plurality of wires 200, and the other end of the one wire is connected to a driving circuit (e.g., a ground terminal of the driving circuit).

The resistive memory chips (e.g., the resistive memory chips 10, 10 ', and 10 ") shown in the foregoing fig. 4, 5, and 6 satisfy the basic requirements of in-situ transmission electron microscope observation, and in the manufacturing process, in some cases, before the resistive memory (e.g., the resistive memory 100, 100', and 100") is disposed on the substrate 300, the resistive memory is further required to be preprocessed on an intermediate medium (not shown) and then disposed on the substrate 300 by transferring the resistive memory using the intermediate medium. The intermediate medium may comprise, for example, a copper mesh or a copper ring of an in-situ transmission electron microscope or other medium suitable for pre-processing the resistive random access memory. In addition, the resistance change memory may be preprocessed by a Focused Ion Beam (FIB) microscope or the like.

The preprocessing performed on the resistance change memory chip is described in detail below with reference to fig. 7 to 8 and 12 to 13.

Fig. 7 is a schematic diagram of a resistive random access memory chip 10 provided in at least one embodiment of the present disclosure.

Referring to fig. 7, in some embodiments, the first source-drain connection electrode 1012, the gate connection electrode 1014, and the end portions of the second electrode 1023 of the resistive memory element 102 respectively have an exposed connection terminal 400 to be electrically connected with one end of a plurality of conductive lines.

For example, in some cases, due to layout design and tape-out requirements, the connection electrodes (e.g., the ground connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, or the second source-drain connection electrode 1016) in the transistor 101 and the second electrode (e.g., the top electrode 1023) of the resistive random access memory element 102 may be located at different depths below the surface of the resistive random access memory (e.g., the resistive random access memories 100, 100', and 100 "), which has no terminals on which wires can be deposited. Therefore, in order to subsequently deposit wires for electrically connecting the resistive memory chip with the driving circuit on the substrate 300, it is necessary to perform surface pretreatment on the resistive memory chip to expose a connection terminal (e.g., connection terminal 400 shown in fig. 7) for connection with one end of a plurality of wires.

As shown in fig. 7, unlike the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode 1023 of the resistive memory element 102 in the resistive memory chip in fig. 4, which are directly electrically connected to the plurality of conductive wires 200, the resistive memory chip 10 shown in fig. 7 is electrically connected to the plurality of conductive wires 200 through the respective connection terminals 400.

Fig. 12 is a flowchart of a manufacturing method corresponding to the resistance change memory chip 10 in fig. 7. Referring to fig. 12, steps S100 and S300 therein are the same as steps S100 and S300 in fig. 10 and 11. The difference is that before the resistance change memory 102 is provided on the substrate 300, in step S201, a pretreatment including forming an exposed connection terminal 400 at an end of the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode (e.g., top electrode) 1023 of the resistance change memory element 102 is performed on the resistance change memory. In step S202, the preprocessed resistance change memory is transferred from the intermediate medium and disposed on the substrate 300.

Specifically, forming the exposed connection terminal 400 at the end portions of the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode (e.g., top electrode) 1023 of the resistance change memory element 102 in step S201 includes: a hole exposing the first source-drain connection electrode 1012 and the gate connection electrode 1014 and the second electrode 1023 of the resistive memory element 102 is formed at an end portion of the first source-drain connection electrode 1012 and the gate connection electrode 1014 and the second electrode 1023 of the resistive memory element 102, and a conductive material (for example, platinum metal) is filled in the hole to form the connection terminal 400.

For example, holes may be formed with an ion beam (e.g., a gallium ion beam) at positions of the surface of the resistive memory corresponding to the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode (e.g., the top electrode) 1023 of the resistive memory element 102, respectively, exposing the respective electrodes, and then depositing, for example, platinum metal within the holes to form the connection terminals 400. In this manner, conductive lines 200 may be subsequently deposited from each connection 400 for electrical connection to the driver circuit.

It should be noted that the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second electrode (e.g., the top electrode) 1023 of the resistive memory element 102 are all described above as being located below the surface, but this is merely for illustration, and the disclosed embodiment is not limited thereto. For example, in some cases, the ground connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, the second source-drain connection electrode 1016, and the top electrode 1023 of the resistance change memory element in the transistor 101 are not all located below the surface, but the corresponding connection terminals may be exposed using the above-described method as long as one of them is located below the surface.

Further, holes may be formed between the connection electrode 1018, the first source-drain connection electrode 1012, the gate connection electrode 1014, and the second source-drain connection electrode 1016 and/or between the second source-drain connection electrode 1016 and an electrode of the resistance change memory element by ion beams (for example, gallium ion beams), and an insulating material (for example, silicon dioxide) may be filled in the holes to prevent short circuits between the connection electrodes and/or between the connection electrode and the electrode of the resistance change memory element.

Fig. 8 is a schematic diagram of a resistive random access memory chip 10 provided in at least one embodiment of the present disclosure.

Referring to fig. 8, unlike the resistance change memory chip shown in fig. 7, the resistance change memory chip 10 shown in fig. 8 further includes a metal protection layer 500 disposed on the side of the connection terminal 400, and the metal protection layer 500 includes a first cutting groove 501 between the connection terminal 400 of the first source-drain connection electrode 1012 and the connection terminal 400 of the gate connection electrode 1014 and a second cutting groove 502 between the connection terminal 400 of the gate connection electrode 1014 and the connection terminal 400 of the second electrode 1023 of the resistance change memory element 102 to insulate the first source-drain connection electrode 1012, the gate connection electrode 1014, and the resistance change memory element 102 from each other.

For example, in general, the purpose of observing the resistive random access memory element in an in-situ transmission electron microscope observation experiment is to observe a resistive layer in the resistive random access memory element, and the resistive layer is usually close to the surface of the resistive random access memory, and in order to avoid the resistive layer from being damaged in the subsequent processing and observation processes, it is necessary to deposit a metal protection layer on the surface of the resistive random access memory to protect the resistive random access memory element, especially the resistive layer, from being damaged. Therefore, as shown in fig. 8, the resistive memory chip 10 may further include a metal protection layer 500 deposited on the side of the connection terminal 400. In addition, in order to insulate the connection electrodes 1012 and 1014 and the resistance change memory element 102 from each other, the metal cap layer 500 may further include a first cutting groove 501 and a second cutting groove 502.

Fig. 13 is a flowchart of a manufacturing method corresponding to the resistance change memory chip 10 in fig. 8.

Referring to fig. 13, steps S100 and S300 therein are the same as steps S100 and S300 in fig. 10 to 12. Unlike fig. 12, the preprocessing performed on the resistance change memory in step S201 includes forming a metal protection layer 400 on the side of the connection terminal 400 in addition to forming the connection terminal 400 as described above, and forming a first cutting groove 501 between the connection terminal 400 of the first source-drain connection electrode 1012 and the connection terminal 400 of the gate connection electrode 1014 and a second cutting groove 502 between the connection terminal 400 of the gate connection electrode 1014 and the connection terminal 400 of the second electrode 1023 of the resistance change memory element 102 in the metal protection layer 400. In step S202, the preprocessed resistance change memory is transferred from the intermediate medium and disposed on the substrate 300.

Therefore, the preprocessed resistive random access memory chip can bear the high-temperature environment in the in-situ transmission electron microscope observation experiment more stably.

Fig. 9 is a schematic diagram of a resistive random access memory chip 10 provided in at least one embodiment of the present disclosure.

Referring to fig. 9, unlike the resistance change memory chip shown in fig. 8, the resistance change memory chip 10 further includes an observation window 600 exposing the resistance change memory element for observing the resistance change layer 1022. Wherein the thickness of the resistive memory element 102 exposed by the observation window 600 in the resistive memory in a direction perpendicular to the substrate 300 is 10 to 50 nm. The thickness refers to a dimension of the thinned resistive memory element 102 in a direction perpendicular to the substrate 300.

In addition, the width of the orthographic projection of the observation window 600 on the plane parallel to the substrate 300 is about 2 to 5 micrometers, for example, 3 micrometers or 4 micrometers, so as to meet the requirement of in-situ electron microscope observation, and simultaneously ensure the structure and function of the resistive random access memory element 102.

In general, a resistive memory chip is fabricated in order to observe a microstructure evolution process of a resistive layer therein in the case of an electron beam transmissive resistive memory element, and thus, after forming a wire (e.g., a platinum wire) 200 for connecting a resistive memory (e.g., resistive memories 100, 100', and 100 ") and a driving circuit on a substrate (a silicon nitride thin film window) 300, an observation window (e.g., an observation window 600) for observing the resistive layer needs to be processed. Moreover, the resistive memory element 102 needs to be thinned to a certain thickness (e.g., 10 to 50 nm) to allow an electron beam to penetrate therethrough, so as to observe the microstructure evolution process thereof.

Fig. 14 is a flowchart of a manufacturing method corresponding to the resistance change memory chip 10 in fig. 9. Steps S100 to S300 are the same as steps S100 to S300 shown in fig. 13. Except that, in step S400, the resistance change memory element 102 is thinned in a direction perpendicular to the substrate 300 to form an observation window 600 exposing the resistance change memory element 200, and the thickness of the resistance change memory element 102 is thinned to 10 to 50 nm.

It should be noted that, although fig. 7 to 9 and fig. 12 to 14 are described by taking the memory chip 10 shown in fig. 4 as an example, the corresponding structures of the connection terminal, the metal protection layer, the cutting groove, the observation window, and the like and the preparation steps thereof are also applicable to the memory chips 10' and 10 ″ shown in fig. 5 and 6.

Fig. 15 is a diagram of an effect of a current limiting test of the resistive random access memory chip 10 provided in at least one embodiment of the present disclosure in fig. 9.

Referring to fig. 15, in a case where the second source-drain electrode electrically connected to the resistance change memory chip 10 is the drain electrode, a transistor current-limiting test is performed on the resistance change memory chip 10, and a current-voltage curve of the drain electrode is obtained. These curves show that the transistor 101 can achieve the purpose of limiting the current for the resistive random access memory element 102 under different operating current conditions in the range where the drain voltage is increased to 5V at maximum. It should be understood by those skilled in the art that when the resistive random access memory chip 10 in fig. 9 is replaced by the corresponding resistive random access memory chips 10 and 10 ″, a similar current limiting effect can be obtained.

A resistance change memory, a resistance change memory chip including the same, and a method of manufacturing the resistance change memory chip using a Focused Ion Beam (FIB) according to at least one embodiment of the present disclosure are described above with reference to fig. 1 to 14. From a macroscopic perspective, a method for manufacturing a resistive random access memory chip for in-situ transmission electron microscope observation from layout design is described with reference to fig. 16. Fig. 16 is a flowchart of a macro fabrication method of a resistive random access memory chip for in-situ transmission electron microscope observation.

Referring to fig. 16, in step S1601, a resistance change memory (e.g., the resistance change memories 100, 100', and 100 ") is designed and a design layout is formed, as shown in fig. 1A and 1B, fig. 2A and 2B, and fig. 3A and 3B. In step 1602, the design layout is delivered to a foundry for tape-out processing to obtain a transistor (e.g., transistor 101) therein. Typically, foundries process a batch of transistors at a time rather than one transistor. In step S1603, a resistance change memory element (e.g., the resistance change memory element 102) is bonded (i.e., electrically connected) to the transistor formed by the flow sheet processing to obtain a resistance change memory array. In step S1604, a single resistance change memory is selected from the resistance change memory array, and an electrical performance test is performed with a probe station. In step S1605, it is determined whether the single resistance change memory can normally perform the set-up and reset operations of the resistance change memory element 102 under the current limiting action of the transistor. If normal, the single resistance change memory is processed into a resistance change memory chip (for example, the resistance change memory chips 10, 10 ', and 10') using a focused ion beam FIB or the like in step S1606. If the operation cannot be performed normally, the process returns to step S1604, and one resistive random access memory is selected again from the resistive random access memory array. After the resistive random access memory chip is finished by processing with focused ion beam FIB or the like, in step S1607, the resistive random access memory chip is subjected to an electrical performance test on a probe stage. In step S1608, it is determined whether the single resistance change memory chip can normally perform the set-up and reset operations of the resistance change memory element under the current limiting action of the transistor. If the normal operation is possible, in step S1609, the in-situ transmission electron microscope observation is performed using the resistive random access memory chip. If the process cannot be normally performed, the process returns to step S1604, and a resistive random access memory is newly selected from the resistive random access memory array, and the subsequent preparation steps are performed as described above.

Therefore, the resistive random access memory chip conforming to the in-situ transmission electron microscope observation experiment can be placed on the in-situ sample table and placed in the electronic light path of the in-situ transmission electron microscope. And carrying out an electrical loading test on the resistive random access memory chip through the driving circuit, and observing the microstructure evolution process of the resistive layer under an electron beam. The resistive random access memory chip for the in-situ transmission electron microscope observation experiment has a transistor current limiting means, so that the resistive random access memory chip is high in tolerance and can be repeatedly established and reset for multiple times, and the working mechanism of the resistive random access memory in the resistive random access memory chip is the same as that of a practically applied resistive random access memory, so that experimental data obtained through the experiment is high in reliability and strong in practicability.

The following points need to be explained:

(1) the drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to general designs.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the appended claims and their equivalents.