阅读说明：本技术 一种半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 李相遇 安重镒 金成基 熊文娟 李亭亭 杨涛 李俊峰 王文武 于 2020-04-09 设计创作，主要内容包括：本发明涉及一种半导体结构及其制备方法。一种含电容孔的半导体结构,包括电容孔,所述电容孔的蚀刻终止层由至少两层氮化物膜组成；所述两层氮化物膜的密度不同；为使所述至少两层氮化物膜的密度不同,采用原位沉积方式。一种半导体结构的制备方法,包括下列步骤：在半导体衬底上沉积蚀刻终止层,再经过后续工艺形成电容孔；其中,所述沉积蚀刻终止层的方法为：在所述半导体衬底上沉积多层氮化物膜,所述多层氮化物膜依次上下层叠,并且所述多层氮化物膜所采用的沉积方法不同。本发明解决了现有技术因电容孔形貌不佳导致器件不良的问题。(The invention relates to a semiconductor structure and a preparation method thereof. A semiconductor structure containing a capacitor hole comprises a capacitor hole, wherein an etching stop layer of the capacitor hole is composed of at least two nitride films; the two nitride films have different densities; in order to make the densities of the at least two nitride films different, an in-situ deposition mode is adopted. A method of fabricating a semiconductor structure, comprising the steps of: depositing an etching stop layer on the semiconductor substrate, and forming a capacitor hole through a subsequent process; the method for depositing the etching stop layer comprises the following steps: and depositing a plurality of nitride films on the semiconductor substrate, wherein the plurality of nitride films are sequentially stacked up and down, and the plurality of nitride films are deposited by different deposition methods. The invention solves the problem of poor device caused by poor appearance of the capacitor hole in the prior art.)

1. A semiconductor structure with capacitor holes is characterized by comprising more than one capacitor holes; and

the etching stop layer is positioned between the adjacent capacitor holes and is basically level with the bottoms of the capacitor holes;

the etching stop layer is composed of at least two nitride films;

the at least two nitride films have different densities;

in order to make the densities of the at least two nitride films different, an in-situ deposition mode is adopted.

2. The semiconductor structure of claim 1, wherein the nitride film is a silicon nitride film or a boron nitride film.

3. The semiconductor structure of claim 1, wherein the etch stop layer comprises a triple layer of nitride.

4. A method for fabricating a semiconductor structure, comprising the steps of:

depositing an etching stop layer on the semiconductor substrate, and forming a capacitor hole through a subsequent process;

the method for depositing the etching stop layer comprises the following steps:

and depositing a plurality of nitride films on the semiconductor substrate, wherein the plurality of nitride films are sequentially stacked up and down, and the plurality of nitride films are deposited by different deposition methods.

5. The method of claim 4, wherein the deposition method is a plasma atomic layer deposition method, a thermal atomic layer deposition method, or a chemical vapor deposition method.

6. The method of claim 4, wherein the chemical composition of the plurality of nitride films is the same or different.

7. The method according to claim 4, wherein the nitride film is a silicon nitride film or a boron nitride film.

8. The method of any of claims 4-7, wherein the multilayer nitride film is three layers.

9. The method according to claim 8, wherein the three-layer nitride film is formed by an atomic layer deposition method or a chemical vapor deposition method, and the deposition temperature of the three-layer nitride film is gradually increased from bottom to top.

10. The method according to claim 9, wherein the deposition temperature of the three-layer nitride film is adjusted between 500 ℃ and 750 ℃.

11. The method according to claim 10, wherein the deposition temperature of the first nitride film is 500 to 550 ℃, the deposition temperature of the second nitride film is 600 to 650 ℃, and the deposition temperature of the third nitride film is 700 to 750 ℃ from bottom to top.

12. The method of any of claims 4-7, wherein the precursor used to deposit the multilayer nitride film is at least one of: dichlorosilane, tetrachlorosilane, hexachlorodisilane.

13. The method according to any one of claims 4 to 7, wherein the deposition method used for the multilayer nitride film comprises at least: plasma deposition and plasma-free deposition; wherein the deposition method is an atomic deposition method or a chemical vapor deposition method.

14. Use of a semiconductor structure according to any of claims 1 to 3, or a method according to any of claims 4 to 13, for the manufacture of a semiconductor device.

15. The use of claim 14, the semiconductor device comprising a capacitor in a DRAM.

Technical Field

The invention relates to the field of semiconductor preparation, in particular to a semiconductor structure and a preparation method thereof.

Background

In the preparation of semiconductor capacitors, the appearance quality of Capacitor holes (Capacitor contacts) is particularly important to the quality of devices. The capacitance hole is etched on a multi-layer stack which is formed on a substrate, the critical dimension of the hole is narrower as the Etching goes deep, which is very adverse to the electrical characteristics of the device, and especially, the shape of the capacitance hole is significantly affected by an Etching stop layer (Etching stopper) at the bottommost layer, so that how to improve the problem that the capacitance hole is narrowed at the bottom is very important to improve the quality of the device.

Disclosure of Invention

The first objective of the present invention is to provide a semiconductor structure with capacitor holes, wherein the capacitor holes of the structure have good shapes, so as to solve the problem of poor devices caused by poor shapes of the capacitor holes in the prior art.

A second object of the present invention is to provide a method for fabricating the above semiconductor structure.

In order to achieve the above purpose, the invention provides the following technical scheme:

a semiconductor structure with capacitor holes comprises capacitor holes,

the etching stop layer of the capacitor hole consists of at least two nitride films;

the two nitride films have different densities;

in order to make the densities of the at least two nitride films different, an in-situ deposition mode is adopted.

Compared with the existing semiconductor capacitor hole structure, the etching stop layer in the capacitor hole of the invention is composed of a plurality of nitride films, and the required etching conditions (such as different etching rates) are different due to different densities of the plurality of nitride films, so that the stop layer can be removed by stages by adopting different etching conditions, thereby avoiding the problem of the gradual narrowing of the hole caused by one-time etching in the prior art and obtaining the hole with better appearance uniformity. In general, the number of stages of the etch stop layer corresponds to the number of layers of the nitride film in the etch layer.

A method of fabricating a semiconductor structure, comprising the steps of:

depositing an etching stop layer on the semiconductor substrate, and forming a capacitor hole through a subsequent process;

the method for depositing the etching stop layer comprises the following steps:

and depositing a plurality of nitride films on the semiconductor substrate, wherein the plurality of nitride films are sequentially stacked up and down, and the plurality of nitride films are deposited by different deposition methods.

In the method, because the density and the physicochemical property of the multilayer nitride film are different due to different deposition methods, the required etching rate is different, and therefore, different etching conditions are required to remove the stop layer in stages, so that the problem that the holes are gradually narrowed due to one-time etching in the prior art can be avoided, and the holes with better morphology uniformity are obtained.

The deposition methods may be different deposition principles or different process conditions of the same deposition principle.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.

FIG. 1 is a schematic diagram of a prior art method for forming an etch stop layer;

FIG. 2 is an enlarged view of a portion of an etched capacitor hole in the laminate obtained by the method of FIG. 1;

FIG. 3 is a schematic view of the semiconductor structure including the capacitor hole obtained by the method of FIG. 1;

FIG. 4 is a schematic diagram of a capacitor structure formed by the structure shown in FIG. 3;

FIG. 5 is a schematic diagram of a method of forming an etch stop layer according to the present invention;

FIG. 6 is an enlarged view of a portion of an etched capacitor hole in the stack resulting from the method of FIG. 5;

fig. 7 shows the etch rates required for nitride films obtained by different deposition methods.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

As shown in fig. 1, the etching stop layer in the prior art is formed at one time (i.e., deposition in one stage), so that the etching conditions (mainly, etching rate) of each region in the etching layer are substantially the same, but the phenomenon shown in fig. 2 to 3 occurs when etching at one time, that is, the holes 102 are narrower in the uniform etching stop layer 101, the uniformity of the holes is poor, and the uniformity of the formed capacitance profile is poor, as shown in fig. 4.

In order to solve the above problems, the present invention proposes a method for forming an etching layer in stages, specifically, as shown in fig. 5, three nitride films are formed in three stages, i.e., a, b, and c, wherein chemical vapor deposition is used in all three stages, but the specific conditions used are different. The three nitride films 201, 202, 203 constitute an etch stop layer, as shown in fig. 6, where 201, 202, 203 respectively represent films formed in the above three stages.

In the stage a, plasma enhanced Chemical Vapor Deposition (CVD) (or Atomic Layer Deposition (ALD)) is adopted, the temperature is 500-550 ℃, dichlorosilane or boron trichloride is adopted as a precursor, and ammonia is adopted as a reaction gas; in the stage b, plasma-enhanced CVD (or ALD) is adopted, the temperature is 600-650 ℃, and Dichlorosilane (DCS) or boron trichloride (BCl) is adopted as a precursor₃) The reaction gas is ammonia; and c, adopting plasma-enhanced CVD (or ALD) at 700-750 ℃, adopting dichlorosilane or boron trichloride as a precursor, and adopting ammonia gas as a reaction gas.

Because the three-stage deposition method causes the difference of the physicochemical properties (including density and the like) of the three-layer nitride film, the required etching rate is different, so that different etching conditions are needed to remove the stop layer in stages, thereby avoiding the problems of one-time formation of the stop layer and gradual narrowing of holes generated by one-time etching, and obtaining the holes 204 with better morphology uniformity. As shown in fig. 7, different wet etch rates are required for different deposition methods (different means and or process conditions). With SiCl₄And NH₃The time rate of the film formed by ACD deposition is maximum at 500 ℃ as a reaction gas; with SiH₂Cl₂And NH₃The time rate of LPCVD deposition of the formed film at 760 c is the smallest for the reactive gas.

The above shows only an embodiment of forming an etching layer in three stages, however, in practical application, it is only necessary to form an etching layer in two or more stages, but different deposition methods are required for each stage. Accordingly, the number of layers of the nitride thin film in the etching layer is the same as the number of stages.

In addition, the deposition of each stage can be performed in situ without moving equipment or wafers, and can be operated continuously, with changing conditions as new stages are entered.

The chemical composition of the different nitride film layers in the etch layer can be the same or different, typically a silicon nitride film or a boron nitride film.

The deposition method of the etching layer is CVD, but the present invention is not limited to the type of the method, and a thermal atomic layer deposition method, Plasma Enhanced Atomic Layer Deposition (PEALD), chemical vapor deposition method, or the like may be used. When using PEALD, the different stages may be selected to alternate on/off of the plasma, or any combination of on and off.

The deposition temperature, the type of reactive gas for each stage is adjustable and not limited to the above list. For etch stop layer nitrides, useful precursors include, but are not limited to, DCS, SiCl₄Hexachlorodisilane (HCD), and the like.

In order to improve the production efficiency and the deposition continuity of each stage, the deposition temperature of the above three stages can be gradually increased from bottom to top (i.e. from stage a to stage c), and is usually adjusted to be between 500 ℃ and 750 ℃.

All the above embodiments are based on the same features: the nitride film is deposited in multiple stages (two, three, four, five, etc.) such that the etch layer is composed of layers having different densities or other properties, and the etch conditions required are different to maintain uniformity of the holes during etching.

Any of the above methods may be used to fabricate semiconductor devices containing capacitive pores, including but not limited to integrated circuit devices or semiconductor capacitors, such as DRAM, 2D NAND, 3D NAND, or LCD, among others.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.