阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 吴晗 于 2020-04-10 设计创作，主要内容包括：该发明涉及半导体制造技术领域,公开了一种半导体结构及其形成方法。该方法包括：提供半导体衬底,所述半导体衬底表面具有多个间隔排列的导电结构；将所述导电结构的表面刻蚀成曲面后,依次沉积形成第一保护层、第二保护层、第三保护层；对所述第一保护层、所述第二保护层及所述第三保护层进行刻蚀处理,以形成显露出所述导电结构刻蚀后的曲面的接触孔；在所述接触孔的表面形成一掩膜层。本发明通过对半导体制造工艺流程的创新与优化,能够改善目前电容连接处的形状,增加接触面积,降低电容接触的阻值；避免造成两个相邻的电容短路的风险,从而提升半导体制造工艺中半导体结构的良品率。(The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of conducting structures which are arranged at intervals; etching the surface of the conductive structure into a curved surface, and then sequentially depositing to form a first protective layer, a second protective layer and a third protective layer; etching the first protection layer, the second protection layer and the third protection layer to form a contact hole exposing the etched curved surface of the conductive structure; and forming a mask layer on the surface of the contact hole. By innovating and optimizing the semiconductor manufacturing process, the shape of the connecting part of the capacitor at present can be improved, the contact area is increased, and the resistance value of capacitor contact is reduced; the risk of short circuit of two adjacent capacitors is avoided, and therefore the yield of the semiconductor structure in the semiconductor manufacturing process is improved.)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of conducting structures which are arranged at intervals;

etching the surface of the conductive structure into a curved surface, and then sequentially depositing to form a first protective layer, a second protective layer and a third protective layer;

etching the first protection layer, the second protection layer and the third protection layer to form a contact hole exposing the etched curved surface of the conductive structure;

and forming a mask layer on the surface of the contact hole.

2. The method of claim 1, wherein the step of etching the surface of the conductive structure into a curved surface further comprises: and removing the covering layer on the surface of the conductive structure, and etching the surface of the conductive structure into a curved surface.

3. The method of claim 2, further comprising: after etching, the conductive structure is convex on the top surface and the top is narrow at the top and wide at the bottom.

4. The method of claim 1, wherein the material of the protective layer comprises: at least one of silicon oxide, silicon nitride, monocrystalline silicon, and polycrystalline silicon.

5. The method of claim 1, wherein the mask layer comprises a material comprising: titanizing nitrogen.

6. A semiconductor structure, comprising:

the semiconductor substrate is provided with a plurality of conducting structures arranged at intervals, and a contact hole exposing a curved surface of the conducting structures after etching is formed on the surface of the semiconductor substrate;

the conductive structures are arranged on the surface of the semiconductor substrate at intervals;

the protective layer is deposited on the semiconductor substrate and the etched curved surface of the conductive structure;

the contact hole is positioned on the surface of the semiconductor substrate;

and the mask layer is formed on the surface of the contact hole and the etched curved surface of the conductive structure.

7. The semiconductor structure of claim 6, further comprising: after etching, the conductive structure is convex on the top surface and the top is narrow at the top and wide at the bottom.

8. The semiconductor structure of claim 6, wherein the material of the conductive structure comprises: at least one of copper and tungsten.

9. The semiconductor structure of claim 6, wherein the material of the mask layer comprises: titanizing nitrogen.

10. The semiconductor structure of claim 6, wherein the material of the protective layer comprises: at least one of silicon oxide, silicon nitride, monocrystalline silicon, and polycrystalline silicon.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage. The capacitor of the DRAM is electrically connected with a capacitor connecting pad (connecting pad) through a lower electrode of the capacitor, and forms an access path with the drain electrode of the transistor.

As the feature size of semiconductor integrated circuit devices is continuously reduced, the requirements for semiconductor manufacturing technology are also continuously increased. The existing capacitor has larger resistance at the contact position with the capacitor connecting pad, if the cross section area of the capacitor column is increased or the area of the capacitor connecting pad is increased, the resistance value of the contact resistor is improved, the requirement on the prior art is extremely high, and the control is very difficult; but also the risk of shorting two adjacent capacitors. Therefore, it is an urgent technical problem to reduce the resistance between the capacitor and the capacitor connecting pad and increase the contact area between the capacitor and the capacitor connecting pad without increasing the size of the capacitor pillar by innovating and optimizing the semiconductor manufacturing process.

Disclosure of Invention

The invention aims to provide a semiconductor structure and a forming method thereof, which can improve the shape of the connection part of the existing capacitor, increase the contact area and reduce the resistance value of the capacitor contact by innovating and optimizing the semiconductor manufacturing process flow.

In order to solve the above technical problem, the present invention provides a method for forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of conducting structures which are arranged at intervals;

etching the surface of the conductive structure into a curved surface, and then sequentially depositing to form a first protective layer, a second protective layer and a third protective layer;

etching the first protection layer, the second protection layer and the third protection layer to form a contact hole exposing the etched curved surface of the conductive structure;

and forming a mask layer on the surface of the contact hole.

Optionally, the step of etching the surface of the conductive structure into a curved surface further includes: and removing the covering layer on the surface of the conductive structure, and etching the surface of the conductive structure into a curved surface.

Optionally, after etching, the top surface of the conductive structure is convex, and the top of the conductive structure is narrow at the top and wide at the bottom.

Optionally, the material of the protective layer includes: at least one of silicon oxide, silicon nitride, monocrystalline silicon, and polycrystalline silicon.

Optionally, the material of the mask layer includes: titanizing nitrogen.

Accordingly, an aspect of the present invention further provides a semiconductor structure, including:

the semiconductor substrate is provided with a plurality of conducting structures arranged at intervals, and a contact hole exposing a curved surface of the conducting structures after etching is formed on the surface of the semiconductor substrate;

the conductive structures are arranged on the surface of the semiconductor substrate at intervals;

the protective layer is deposited on the semiconductor substrate and the etched curved surface of the conductive structure;

the contact hole is positioned on the surface of the semiconductor substrate;

and the mask layer is formed on the surface of the contact hole and the etched curved surface of the conductive structure.

Optionally, after etching, the top surface of the conductive structure is convex, and the top of the conductive structure is narrow at the top and wide at the bottom.

Optionally, the material of the conductive structure includes: at least one of copper and tungsten.

Optionally, the material of the mask layer includes: titanizing nitrogen.

Optionally, the material of the protective layer includes: at least one of silicon oxide, silicon nitride, monocrystalline silicon, and polycrystalline silicon.

Compared with the existing semiconductor manufacturing process, the invention has the advantages that the invention carries out innovation and optimization on the semiconductor manufacturing process flow, can improve the shape of the connecting part of the existing capacitor, increases the contact area and further reduces the resistance value of the capacitor contact. Therefore, the risk of short circuit of two adjacent capacitors can be avoided, and the yield of the semiconductor structure in the semiconductor manufacturing process is improved.

Drawings

Fig. 1 to 6 are schematic structural diagrams of a semiconductor structure forming method according to an embodiment of the present invention, in which steps are sequentially performed;

FIG. 7 is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the present invention.

Reference numerals:

100: a semiconductor substrate; 200: a conductive structure; 201: a masking layer; 101: a first protective layer;

102: a second protective layer; 103: a third protective layer; 300: a contact hole; 301: and (5) masking the layer.

Detailed Description

The following describes a method for forming a semiconductor structure according to the present invention in detail with reference to the accompanying drawings and the detailed description.

Providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of conducting structures arranged at intervals.

Referring to fig. 1, a semiconductor substrate 100 is provided, where the semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate 100 is a single crystal substrate or a polycrystalline substrate, the semiconductor substrate may also be an intrinsic silicon substrate or a doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

The surface of the semiconductor substrate 100 is provided with a plurality of conductive structures 200 arranged at intervals; the conductive structure 200 penetrates through the surface of the semiconductor substrate 100; the conductive structure 200 may be, but is not limited to, tungsten, copper, and the like, associated integrated circuit conductive material.

The forming method of the conductive structure 200 comprises the following steps: recesses are formed in the semiconductor substrate 100 and a metal layer (not shown) is deposited on the semiconductor substrate 100. And continuously depositing a mask layer on the surface of the metal layer. The mask layer is patterned to form conductive structures 200 spaced apart on the semiconductor substrate 100, which is defined as a main etch in this embodiment. The reaction time is generally about (30s-50 s). Therefore, a plurality of conductive structures 200 arranged at intervals can be formed on the semiconductor substrate 100 by main etching.

As will be understood by those skilled in the art, the capacitor of the dram is electrically connected to a capacitor connecting pad (connecting pad) through its bottom electrode and forms an access path with the drain of the transistor. The conductive structure 200 may also be referred to as a capacitive connection pad. Further, the conductive structure 200 is located on the surface of the semiconductor substrate 100, and has a specific offset characteristic, which is to ensure that the conductive structure can be connected to the bottom conductive structure, and can ensure the close packing arrangement of the capacitor openings, increase the capacitor density, and increase the capacitor storage capacity per unit area.

Referring to fig. 2, the masking layer 201 on the surface of the conductive structure 200 is removed.

The floodcoat layer 201 on the surface of the conductive structure 200 is first removed before proceeding to the next step. The masking layer 201 may include, but is not limited to, an oxide, a nitride, or an impurity. Therefore, it is desirable to ensure the purity of the conductive structure 200 and thus control the success rate in the semiconductor fabrication process. The masking layer 201 on the surface of the conductive structure 200 can be removed by physical polishing and grinding. The etching process may also be performed by a chemical method, and the masking layer 201 on the surface of the conductive structure 200 is removed by wet etching.

Referring to fig. 3, the surface of the conductive structure 200 is etched into a curved surface by dry etching.

There are two basic etching processes in semiconductor manufacturing: dry etching and wet etching. Dry etching is a process technique for etching away the exposed surface material on a silicon wafer by using plasma generated in a gas state and carrying out physical and chemical reactions with the silicon wafer exposed to the plasma through a mask layer window opened by photoetching. Dry etching is used in fine etching of small feature sizes of advanced circuits. Dry etching refers to an etching technique using gas as a main medium, and the material does not need liquid chemicals or washing, and enters and exits the system in a dry state. Compared with wet etching, dry etching shows both chemical isotropy (meaning that etching exists in both vertical and horizontal directions) and physical anisotropy (meaning that etching exists in a single vertical direction) in etching characteristics.

In this embodiment, a dry etching process may be used to etch the surface of the conductive structure 200. The method comprises the following specific steps: the semiconductor structure is transferred to a reaction chamber, and the internal pressure is reduced by a vacuum system. After the vacuum is established, the reaction chamber is filled with a reaction gas. For etching of conductive materials of associated integrated circuits, such as tungsten, copper, etc., a mixture of nitrogen fluoride and oxygen is typically used as the reactive gas. Alternatively, other fluorine-containing gases may be used as the etching gas, such as carbon tetrafluoride, sulfur hexafluoride, nitrogen trifluoride, etc. The power supply creates a radio frequency electric field through electrodes in the reaction chamber. The energy field excites the mixed gas into a plasma state. In the excited state, the reactive fluorine etches and converts it into volatile components which are exhausted by the vacuum system.

Further, in this embodiment, in order to meet the corresponding process requirement, the etching time needs to be increased after the masking layer is removed. The main component of the reaction gas adopted by the over-etching is nitrogen fluoride. Wherein, the ratio of the nitrogen ions to the fluorine ions is controlled to be between 1:2 and 1: 3.5. The over-etching time is generally 20% to 50% of the main etching time. Thereby, the surface of the conductive structure 200 is etched into a curved surface. Finally, other etching residues are removed. After etching, the top surface of the conductive structure 200 is convex, and the top of the conductive structure is narrow at the top and wide at the bottom, that is, the curved surface.

As will be appreciated by those skilled in the art, the capacitor of the dram is electrically connected to the capacitor pad through its bottom electrode and forms an access path with the drain of the transistor. In the structure of the prior art in which the capacitor is electrically connected to the capacitor connecting pad, the curved surface means that the contact area between the capacitor and the capacitor connecting pad is increased, thereby reducing the resistance between the capacitor and the capacitor connecting pad.

Therefore, under the condition of not increasing the size of the capacitor column, the resistance value between the current capacitor and the capacitor connecting pad is reduced by increasing the contact area of the capacitor column and the capacitor connecting pad, and the risk of short circuit of two adjacent capacitors is avoided. Meanwhile, the method meets the technical requirements of the existing semiconductor process, and is easier to control and operate.

Referring to fig. 4, a protective layer is formed on the surfaces of the semiconductor substrate 100 and the etched conductive structure 200.

Specifically, after the surface of the conductive structure 200 is etched to be a curved surface, a first protective layer 101, a second protective layer 102, and a third protective layer 103 are sequentially deposited on the surface of the semiconductor substrate 100 and the surface of the etched conductive structure 200 through a deposition process.

In the thin film deposition process, there are two main deposition methods: chemical vapor deposition, a growth technique in which a gas of one or more substances is activated in some way to chemically react on the surface of the substrate and deposit a desired solid film. Physical vapor deposition, which is a technique of transferring atoms or molecules onto the surface of a silicon substrate and depositing the atoms or molecules into a thin film by using a physical process. The techniques for depositing the thin film include spin coating, electroplating, and the like. In this embodiment, the specific deposition manner of the first protection layer 101 may be various. For example, a chemical vapor deposition method is adopted to deposit a protective layer 101 with a preset thickness distribution on the surface of the semiconductor substrate 100 and the surface of the etched conductive structure 200. Furthermore, the control means of controlling the flow rate of the introduced gas flow, controlling the deposition duration or controlling the deposition temperature can be independently applied, and by improving the control precision of the gas flow and the temperature, the atoms can be ensured to be orderly arranged during deposition to form a single crystal layer, and finally a first protective layer 101 with uniform thickness is obtained on the surfaces of the semiconductor substrate 100 and the etched conductive structure 200. In the same deposition manner, the second protective layer 102 is continuously deposited on the surface of the first protective layer 101. The deposition of the third protective layer 103 is continued on the surface of the second protective layer 102.

Commonly used deposition materials are monocrystalline silicon, polycrystalline silicon, silicon dioxide, silicon nitride, and the like insulating materials that isolate the interconnect layers. Therefore, the materials of the first, second, and third protective layers 101, 102, and 103 may include, but are not limited to, silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, carbon, and other relevant integrated circuit insulating materials. For example, in this embodiment, the first protective layer 101 may be a silicon nitride layer, the second protective layer 102 may be an oxide layer, and the third protective layer 103 may be a silicon nitride layer. In addition, the deposition thickness of the protective layer may be, according to the properties of the material: the thickness of the oxide layer is (30-120 nm), the thickness of the silicon nitride layer is (30-50 nm), and the like.

In step five, please refer to fig. 5, the semiconductor structure with the contact hole structure is formed by etching process. The forming method of the semiconductor structure is used for forming a novel structure with a capacitor connecting pad.

Specifically, the first protection layer 101, the second protection layer 102, and the third protection layer 103 are etched to form a contact hole 300 exposing a curved surface of the etched conductive structure 200; the surface of the conductive structure 200 is etched into a curved surface by dry etching.

In this embodiment, a dry etching process may be used to etch the surface of the conductive structure 200. The method comprises the following specific steps: the semiconductor structure is transferred to a reaction chamber, and the internal pressure is reduced by a vacuum system. After the vacuum is established, the reaction chamber is filled with a reaction gas. For etching of conductive materials of associated integrated circuits, such as tungsten, copper, etc., a mixture of nitrogen fluoride and oxygen is typically used as the reactive gas. Alternatively, other fluorine-containing gases may be used as the etching gas, such as carbon tetrafluoride, sulfur hexafluoride, nitrogen trifluoride, etc. The power supply creates a radio frequency electric field through electrodes in the reaction chamber. The energy field excites the mixed gas into a plasma state. In the excited state, the reactive fluorine etches and converts it into volatile components which are exhausted by the vacuum system.

Further, in the present embodiment, the main component of the reaction gas used is carbon fluoride. Wherein, the ratio of the carbon ions to the fluorine ions is controlled to be 1:1 to 1: 2. By selecting the etching ratio between 1:1 and 1:2, the etching selection ratio of the first passivation layer 101 to the conductive structure 200 can be increased, and the shape of the conductive structure 200 is not affected by etching the conductive structure 200 during the process of removing the passivation layer 101. If the ratio of the etching gas is greater or not less than this ratio, it may cause the contact surface of the conductive structure 200 to form a concave or planar structure. Finally, other etching residues are removed to form the contact hole 300 exposing the etched curved surface of the conductive structure 200.

Referring to fig. 6, a mask layer 301 is formed on the surface of the contact hole 300 and the curved surface of the etched conductive structure 200.

Specifically, a mask layer 301 is formed in the contact hole 300, and the contact hole 300 is communicated with the curved surface of the etched conductive structure 200. In this embodiment, a mask layer 301 is formed on the surface of the contact hole 300 and the curved surface of the etched conductive structure 200 by using an electroplating ECP technique. The material of the mask layer 301 includes: titanizing nitrogen. The thickness of the mask layer 301 may be, according to the material properties: the thickness of the titanium nitride layer is (30-50 nm).

Since the capacitor of the dram is electrically connected to a capacitor connecting pad (connecting pad) through its lower electrode and forms an access path with the drain of the transistor. In the structure of the prior art in which the capacitor is electrically connected to the capacitor connecting pad, the curved surface means that the contact area between the capacitor and the capacitor connecting pad is increased, thereby reducing the resistance between the capacitor and the capacitor connecting pad.

Therefore, the present embodiment mainly aims at the innovation and optimization of the semiconductor manufacturing process flow, and can improve the shape of the current capacitor connection, increase the contact area, and thus reduce the resistance of the capacitor contact. The risk of short circuit of two adjacent capacitors is avoided, and therefore the yield of the semiconductor structure in the semiconductor manufacturing process is improved.

Embodiments of the present invention also provide a semiconductor structure.

Fig. 7 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.

The semiconductor structure includes: the semiconductor device comprises a semiconductor substrate 100, a conductive structure contact hole 300, a first protective layer 101, a second protective layer 102, a third protective layer 103 and a mask layer 301. Namely, a novel structure with a capacitor connecting pad is formed by the semiconductor forming method.

The semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate 100 is a single crystal substrate or a polycrystalline substrate, it may also be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

The surface of the semiconductor substrate 100 is provided with a plurality of conductive structures 200 arranged at intervals; the conductive structure 200 penetrates through the surface of the semiconductor substrate 100; the conductive structure 200 may be, but is not limited to, tungsten, copper, and the like, associated integrated circuit conductive material. As will be appreciated by those skilled in the art, the capacitor of the dram is electrically connected to the capacitor pad through its bottom electrode and forms an access path with the drain of the transistor. The conductive structure 200 may also be referred to as a capacitive connection pad. Further, the conductive structure 200 is located on the surface of the semiconductor substrate 100, and has a specific offset characteristic, which is to ensure that the conductive structure can be connected to the bottom conductive structure, and can ensure the close packing arrangement of the capacitor openings, increase the capacitor density, and increase the capacitor storage capacity per unit area.

The first protective layer 101, the second protective layer 102, and the third protective layer 103 are sequentially deposited on the etched curved surfaces of the semiconductor substrate 100 and the conductive structure 200. Commonly used deposition materials are monocrystalline silicon, polycrystalline silicon, silicon dioxide, silicon nitride, and the like insulating materials that isolate the interconnect layers. Therefore, the materials of the first, second, and third protective layers 101, 102, and 103 may include, but are not limited to, silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, carbon, and other relevant integrated circuit insulating materials. For example, in this embodiment, the first protective layer 101 may be a silicon nitride layer, the second protective layer 102 may be an oxide layer, and the third protective layer 103 may be a silicon nitride layer. In addition, the deposition thickness of the protective layer may be, according to the properties of the material: the thickness of the oxide layer is (30-120 nm), the thickness of the silicon nitride layer is (30-50 nm), and the like.

After etching, the top surface of the conductive structure 200 is convex, and the top of the conductive structure is narrow at the top and wide at the bottom, that is, the curved surface. The contact hole 300 is located on the surface of the semiconductor substrate 100.

The mask layer 301 is formed on the surface of the contact hole 300 and the etched curved surface of the conductive structure 200. Specifically, a mask layer 301 is formed in the contact hole 300, and the contact hole 300 is communicated with the curved surface of the etched conductive structure 200. The mask layer is made of materials including: titanizing nitrogen. The thickness of the mask layer 301 may be, according to the material properties: the thickness of the titanium nitride layer is (30-50 nm).

Since the capacitor of the dram is electrically connected to a capacitor connecting pad (connecting pad) through its lower electrode and forms an access path with the drain of the transistor. In the structure of the prior art in which the capacitor is electrically connected to the capacitor connecting pad, the curved surface means that the contact area between the capacitor and the capacitor connecting pad is increased, thereby reducing the resistance between the capacitor and the capacitor connecting pad. Therefore, under the condition of not increasing the size of the capacitor column, the resistance value between the current capacitor and the capacitor connecting pad is reduced by increasing the contact area of the capacitor column and the capacitor connecting pad, and the risk of short circuit of two adjacent capacitors is avoided. Meanwhile, the method meets the technical requirements of the existing semiconductor process, and is easier to control and operate.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.