阅读说明：本技术 铁电随机存取存储器器件及形成方法 (Ferroelectric random access memory device and method of forming ) 是由 林孟汉 杨柏峰 贾汉中 王圣祯 杨丰诚 杨世海 林佑明 于 2021-01-13 设计创作，主要内容包括：一种形成铁电随机存取存储器(FeRAM)器件的方法,包括：依次在衬底上形成第一层堆叠和第二层堆叠,其中,第一层堆叠和所述第二层堆叠具有相同的层状结构,层状结构包括在第一介电材料层上方的第一导电材料层,其中,第一层堆叠延伸超过第二层堆叠的横向范围；形成延伸穿过该第一层堆叠和第二层堆叠的沟槽；用铁电材料加衬该沟槽的侧壁和底部；在铁电材料的上方的沟槽中共形地形成沟道材料；用第二介电材料填充该沟槽；在第二介电材料中形成第一开口和第二开口；以及用第二导电材料填充第一开口和第二开口。本发明的实施例还涉及铁电随机存取存储器器件。(A method of forming a ferroelectric random access memory (FeRAM) device, comprising: sequentially forming a first layer stack and a second layer stack on a substrate, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack; forming a trench extending through the first layer stack and the second layer stack; lining the sidewalls and bottom of the trench with a ferroelectric material; forming channel material conformally in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in a second dielectric material; and filling the first opening and the second opening with a second conductive material. Embodiments of the present invention also relate to ferroelectric random access memory devices.)

1. A method of forming a ferroelectric random access memory device, the method comprising:

sequentially forming a first layer stack and a second layer stack over a substrate, wherein each of the first layer stack and the second layer stack has a first dielectric layer and a conductive layer formed over the first dielectric layer;

forming a second dielectric layer over the second layer stack;

patterning the first layer stack, the second layer stack, and the second dielectric layer, wherein the patterning forms a stepped region, wherein in the stepped region the second layer stack extends beyond a lateral extent of the second dielectric layer and the first layer stack extends beyond a lateral extent of the second layer stack, wherein after the patterning, the conductive layers of the first layer stack and the second layer stack form a first word line and a second word line, respectively;

forming a trench extending through the first layer stack, the second layer stack, and the second dielectric layer after the patterning;

lining the sidewalls and bottom of the trench with a ferroelectric material;

forming a channel material over the ferroelectric material;

filling the trench by forming a dielectric material over the channel material; and

forming a source line and a bit line in the dielectric material, wherein the source line and the bit line extend through the second dielectric layer, the second layer stack, and the first layer stack.

2. The method of claim 1, wherein, in the stepped region, the second layer stack extends along a first direction beyond a lateral extent of the second dielectric layer, and the first layer stack extends along the first direction beyond a lateral extent of the second layer stack.

3. The method of claim 2, wherein the trench is formed to have a longitudinal axis along the first direction.

4. The method of claim 3, wherein, after the patterning, sidewalls of the patterned second dielectric layer define a memory array region adjacent to the stepped region.

5. The method of claim 4, wherein the trench is formed to extend through the memory array region and the stepped region.

6. The method of claim 5, further comprising: after forming the source line and the bit line, the channel material is removed from the stepped region.

7. The method of claim 5, further comprising: after forming the source line and the bit line, the channel material and the ferroelectric material are removed from the stepped region.

8. The method of claim 4, wherein the trench is formed within the memory array region.

9. A method of forming a ferroelectric random access memory device, the method comprising:

sequentially forming a first layer stack and a second layer stack on a substrate, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack;

forming a trench extending through the first layer stack and the second layer stack;

lining the sidewalls and bottom of the trench with a ferroelectric material;

conformally forming a channel material in the trench over the ferroelectric material;

filling the trench with a second dielectric material;

forming a first opening and a second opening in the second dielectric material; and

filling the first opening and the second opening with a second conductive material.

10. A ferroelectric random access memory device, comprising:

a first layer stack;

a second layer stack over the first layer stack, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack;

a second dielectric material embedded in the first layer stack and the second layer stack, the second dielectric material extending through the first layer stack and the second layer stack;

a ferroelectric material between the second dielectric material and the first layer stack and between the second dielectric material and the second layer stack;

a channel material between the ferroelectric material and the second dielectric material; and

a conductive line embedded in the second dielectric material, wherein the conductive line extends through the first layer stack and the second layer stack.

Technical Field

The present invention relates generally to semiconductor memory devices and, in particular embodiments, to three-dimensional (3D) ferroelectric random access memory (FeRAM) devices, ferroelectric random access memory devices, and methods of formation.

Background

Semiconductor memories are used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories. One is a volatile memory; the other is a non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose stored information when not powered.

On the other hand, nonvolatile memory may store data thereon without power up. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include fast write/read speed and small size.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a method of forming a ferroelectric random access memory device, the method including: sequentially forming a first layer stack and a second layer stack over a substrate, wherein each of the first layer stack and the second layer stack has a first dielectric layer and a conductive layer formed over the first dielectric layer; forming a second dielectric layer over the second layer stack; patterning the first layer stack, the second layer stack and the second dielectric layer, wherein the patterning forms a stepped region, wherein in the stepped region the second layer stack extends beyond a lateral extent of the second dielectric layer and the first layer stack extends beyond a lateral extent of the second layer stack, wherein after the patterning, the conductive layers of the first layer stack and the second layer stack form a first word line and a second word line, respectively; after patterning, forming a trench extending through the first layer stack, the second layer stack, and the second dielectric layer; lining the sidewalls and bottom of the trench with a ferroelectric material; forming a channel material over the ferroelectric material; filling the trench by forming a dielectric material over the channel material; and forming a source line and a bit line in the dielectric material, wherein the source line and the bit line extend through the second dielectric layer, the second layer stack, and the first layer stack.

According to another aspect of embodiments of the present invention, there is provided a method of forming a ferroelectric random access memory device, the method including: sequentially forming a first layer stack and a second layer stack on a substrate, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack; forming a trench extending through the first layer stack and the second layer stack; lining the sidewalls and bottom of the trench with a ferroelectric material; forming channel material conformally in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in a second dielectric material; and filling the first opening and the second opening with a second conductive material.

According to still another aspect of an embodiment of the present invention, there is provided a ferroelectric random access memory device including: a first layer stack; a second layer stack above the first layer stack, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material above a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack; a second dielectric material embedded in the first layer stack and the second layer stack, the second dielectric material extending through the first layer stack and the second layer stack; a ferroelectric material between the second dielectric material and the first layer stack and between the second dielectric material and the second layer stack; a channel material between the ferroelectric material and the second dielectric material; and a conductive line embedded in the second dielectric material, wherein the conductive line extends through the first layer stack and the second layer stack.

Drawings

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 shows a cross-sectional view of a semiconductor device with an integrated memory device in an embodiment;

2A, 2B, 3A, 3B, 4-7, 8A, 8B, 8C, 8D, 8E, 9, 10A, and 10B illustrate various views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device at various stages of fabrication in an embodiment;

FIGS. 11 and 12 show perspective views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device at various stages of fabrication in another embodiment;

FIGS. 13-19 illustrate perspective views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device at various stages of fabrication in yet another embodiment;

fig. 20 shows an equivalent circuit diagram of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device in an embodiment; and

fig. 21 illustrates a flow diagram of a method of forming a three-dimensional (3D) ferroelectric random access memory (FeRAM) device in some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Throughout the discussion herein, the same or similar reference numbers in different figures refer to the same or similar elements formed by the same or similar processes using the same or similar materials, unless otherwise specified.

In some embodiments, a method of forming a ferroelectric random access memory (FeRAM) device includes a first layer stack and a second layer stack formed successively over a substrate, wherein the first layer stack and the second layer stack have a same layer structure including a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack. The method also includes forming a trench extending through the first layer stack and the second layer stack, lining sidewalls and a bottom of the trench with a ferroelectric material, conformally forming a channel material in the trench over the ferroelectric material, filling the trench with a second dielectric material, forming a first opening and a second opening in the second dielectric material, and filling the first opening and the second opening with a second conductive material.

Fig. 1 illustrates a cross-sectional view of a semiconductor device 100 with an integrated memory device 123 (e.g., 123A and 123B) in an embodiment. In the illustrated embodiment, the semiconductor device 100 is a fin field effect transistor (FinFET) device with a three-dimensional (3D) ferroelectric random access memory (FeRAM) device 123 integrated in a back end of line (BEOL) process of semiconductor fabrication. To avoid clutter, the details of the storage device 123 are not shown in fig. 1, but are shown in subsequent figures below.

As shown in fig. 1, the semiconductor device 100 includes different regions for forming different types of circuits. For example, the semiconductor device 100 may include a first region 110 for forming a logic circuit, and may include a second region 120 for forming, for example, a peripheral circuit, an input/output (I/O) circuit, an electrostatic discharge (ESD) circuit, and/or an analog circuit. Other regions for forming other types of circuits are possible and are all contemplated to be within the scope of the present invention.

The semiconductor device 100 includes a substrate 101. The substrate 101 may be a bulk substrate, such as a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 101 may comprise other semiconductor materials, such as germanium, a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide and/or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP, or combinations thereof. Other substrates, such as multilayer or graded substrates, may also be used.

In a front end of line (FEOL) process of semiconductor fabrication, electrical components such as transistors, resistors, capacitors, inductors, diodes, and the like are formed in or on the substrate 101. In the example of fig. 1, a semiconductor fin 103 (also referred to as a fin) is formed to protrude above a substrate 101. Isolation regions 105, such as Shallow Trench Isolation (STI) regions, are formed between or around the semiconductor fins 103. The gate electrode 109 is formed over the semiconductor fin 103. Gate spacers 111 are formed along sidewalls of the gate electrode 109. Source/drain regions 107, such as epitaxial source/drain regions, are formed on opposite sides of the gate electrode 109. Contacts 113, such as gate contacts and source/drain contacts, are formed over and electrically coupled to the respective underlying conductive features (e.g., gate electrode 109 or source/drain regions 107). One or more dielectric layers 117, such as an interlayer dielectric (ILD) layer, are formed over the substrate 101 and around the semiconductor fin 103 and the gate electrode 109. Other conductive features, such as interconnect structures including conductive lines 115 and vias 114, may also be formed in one or more dielectric layers 117. The finfets in fig. 1 may be formed by any suitable method known or used in the art and will not be described in detail herein. For purposes of discussion herein, the substrate 101, electronic components (e.g., finfets) formed in the substrate 101, or the substrate 101, contacts 113, conductive members 115/114, and one or more dielectric layers 117 are collectively referred to as the substrate 50.

Still referring to fig. 1, a dielectric layer 119 may be formed on one or more of the dielectric layers 117, and the dielectric layer 119 may be an Etch Stop Layer (ESL). In an embodiment, the dielectric layer 119 is formed of plasma enhanced physical vapor deposited (PECVD) silicon nitride, although other dielectric materials, such as nitrides, carbides, combinations thereof, and the like, may alternatively be used, as well as alternative techniques for forming the dielectric layer 119, such as Low Pressure Chemical Vapor Deposition (LPCVD), PVD, and the like. In some embodiments, dielectric layer 119 is omitted. Next, a dielectric layer 121 is formed over the dielectric layer 119. Dielectric layer 121 may be any suitable dielectric material, such as silicon oxide, silicon nitride, etc., formed by suitable methods such as PVD, CVD, etc. One or more memory devices 123A are formed in the dielectric layer 121, each memory device 123A including a plurality of memory cells, and the memory devices 123A are coupled to conductive features (e.g., vias 124 and conductive lines 125) in the dielectric layer 121. Various embodiments of the memory device 123A or 123B (e.g., 3D FeRAM devices 200, 200A, and 200B) of fig. 1 will be discussed in detail below.

Fig. 1 also shows a second layer of memory device 123B formed over memory device 123A. The memory devices 123A and 123B may have the same or similar structure and may be collectively referred to as the memory device 123. As a non-limiting example, the example of FIG. 1 shows a two-layer memory device 123. Other numbers of memory devices 123 are possible, such as one, three, or more layers, and are all contemplated to be within the scope of the present invention. One or more layers of memory devices 123 are formed in the memory region 130 of the semiconductor device 100 and may be formed in a back end of line (BEOL) process of semiconductor fabrication. The memory device 123 may be formed at any suitable location within the semiconductor device 100 in a BEOL process, such as over the first region 110 (e.g., directly over the first region 110), over the second region 120, or over multiple regions.

In the example of fig. 1, the memory device 123 occupies some, but not all, of the memory region 130 of the semiconductor device 100, as other components, such as the conductive lines 125 and vias 124, may be formed in other regions of the memory region 130 to connect to conductive components above and below the memory region 130. In some embodiments, to form memory device 123A or 123B, a mask layer, such as a patterned photoresist layer, is formed to cover certain areas of memory region 130, while memory device 123A or 123B is formed in other areas of memory region 130 exposed through the mask layer. After the memory device 123 is formed, the mask layer is then removed.

Still referring to fig. 1, after forming memory region 130, an interconnect structure 140 is formed over memory region 130, interconnect structure 140 including dielectric layer 121 and conductive features (e.g., vias 124 and conductive lines 125) in dielectric layer 121. The interconnect structure 140 may electrically connect electrical components formed in/on the substrate 101 to form a functional circuit. The interconnect structure 140 may also electrically couple the memory device 123 to components formed in/on the substrate 101 and/or couple the memory device 123 to conductive pads formed over the interconnect structure 140 for connection with external circuitry or external devices. The formation of interconnect structures is known in the art and therefore details are not repeated here.

In some embodiments, the memory device 123 is electrically coupled to electrical components (e.g., transistors) formed on the substrate 50, for example, through vias 124 and conductive lines 125, and in some embodiments, the memory device 123 is controlled or accessed (e.g., written to or read from) by functional circuitry of the semiconductor device 100. Additionally or alternatively, the memory device 123 is electrically coupled to a conductive pad formed over a top metal layer of the interconnect structure 140, in which case, in some embodiments, the memory device 123 may be controlled or accessed directly by external circuitry (e.g., another semiconductor device) without involving functional circuitry of the semiconductor device 100. Although additional metal layers (e.g., interconnect structure 140) are formed on memory device 123 in the example of fig. 1, memory device 123 may be formed in a top (e.g., topmost) metal layer of semiconductor device 100, and these and other variations are all intended to be included within the scope of the present invention.

Fig. 2A, 2B, 3A, 3B, 4-7, 8A, 8B, 8C, 8D, 8E, 9, 10A, and 10B illustrate various views (e.g., perspective, cross-sectional, and/or top views) of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device 200 at various stages of fabrication in an embodiment. For ease of discussion, in the discussion herein, a 3D FeRAM device may also be referred to as a 3D memory device, or simply a memory device. The 3D memory device 200 is a three-dimensional memory device having a ferroelectric material. The 3D memory device 200 may be used as the memory devices 123A and/or 123B in fig. 1. Note that all components of the 3D memory device 200 are not shown in the drawings for simplicity.

Referring now to fig. 2A, a perspective view of a memory device 200 at an early stage of fabrication is shown. Fig. 2B shows a cross-sectional view of the memory device 200 of fig. 2A along section a-a. As shown in fig. 2A and 2B, layer stacks 202A, 202B, 202C, and 202D are formed in sequence on substrate 50. The layer stacks 202A, 202B, 202C, and 202D may be collectively referred to herein as a layer stack 202. In the illustrated embodiment, the layer stacks 202A, 202B, 202C and 202D have the same layered structure. For example, each layer stack 202 includes a dielectric layer 201 and a conductive layer 203 over the dielectric layer 201. Note that the substrate 50 is shown in fig. 2A and 2B to illustrate that the memory device 200 is formed over the substrate 50, and the substrate 50 may not be considered part of the memory device 200. For simplicity, the substrate 50 may not be shown in subsequent figures.

In some embodiments, to form the layer stack 202A, first, the dielectric layer 201 is formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable deposition method, such as PVD, CVD, Atomic Layer Deposition (ALD), or the like. Next, a conductive layer 203 is formed over the dielectric layer 201. In some embodiments, conductive layer 203 is formed from a conductive material, such as a metal or metal-containing material. Example materials of the conductive layer 203 include Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, and the like. Conductive layer 203 can be formed by, for example, PVD, CVD, ALD, combinations thereof, and the like.

As shown in fig. 1, after forming the layer stack 202A, the process of forming the layer stack 202A may be repeated to successively form the layer stacks 202B, 202C, and 202D over the layer stack 202A. After forming the layer stacks 202A, 202B, 202C and 202D, a dielectric layer 201T is formed over the topmost layer stack, which in the embodiment shown is layer stack 202D. In an example embodiment, the dielectric layer 201T is formed of the same dielectric material as the dielectric layer 201 of the layer stack 202, and thus may also be referred to as the dielectric layer 201 in the discussion that follows.

Next, as shown in fig. 3A and 3B, a plurality of etching processes are performed to pattern the layer stack 202 and the dielectric layer 201T, thereby forming a stepped region 231. In addition, the patterned dielectric layer 201T defines a memory array region 233 after multiple etching processes. For example, the memory array region 233 is defined by sidewalls of the patterned dielectric layer 201T. In subsequent processing, an array of memory cells will be formed in the memory array region 233. Fig. 3A shows a perspective view of the memory device 200, and fig. 3B shows a cross-sectional view of the memory device 200 in fig. 3A along section B-B.

As shown in fig. 3A and 3B, in the stepped region 231, the layer stack 202D extends beyond the lateral extent of the dielectric layer 201T, for example, in the direction of the cross-section B-B. Additionally, for any two vertically adjacent layer stacks (e.g., 202A and 202B), the lower layer stack (e.g., 202A) closer to the substrate 50 extends beyond the lateral extent of the upper layer stack (e.g., 202B) further from the substrate 50 along the direction of cross-section B-B. In other words, the width of the lower layer stack (e.g., 202A) as measured in the direction of section B-B between opposite side walls of the lower layer stack is greater than the width of the upper layer stack (e.g., 202B) as measured in the direction of section B-B between opposite side walls of the upper layer stack. In addition, the width of the layer stack 202D is greater than the width of the dielectric layer 201T measured in the direction of the cross-section B-B. In the embodiment shown, the layer stack 202 and the dielectric layer 201T have the same width W, measured in a direction perpendicular to the cross-section B-B.

Note that in the discussion herein, the sidewalls of a layer stack 202A, 202B, 202C, or 202D include corresponding sidewalls of all of the constituent layers (e.g., 201 and 203) of the layer stack. For example, the sidewalls of layer stack 202A exposed by trench 206 (see fig. 5) include respective sidewalls of dielectric layer 201 and respective sidewalls of conductive layer 203. In the illustrated embodiment, the etching process performed on each layer stack 202 to form the stepped region 231 is anisotropic, and thus, the sidewalls of the dielectric layer 201 and the corresponding sidewalls of the conductive layer 203 in the same layer stack 202 (e.g., 202A, 202B, 202C, or 202D) are aligned along the same vertical plane.

Still referring to fig. 3A and 3B, in the stepped region 231, a portion of each layer stack 202 at a laterally distal end of the memory array region 233 is removed. The further up the layer stack 202 (e.g., the further away from the substrate 50), the greater the width of the removed portion of the layer stack (e.g., measured in the direction of cross-section B-B). As a result, for each layer stack 202, a portion of conductive layer 203 that is lateral to the far side of memory array region 233 is exposed by the overlying layer stack. Thus, the stepped region 231 provides a channel that readily reaches the conductive layer 203 of each layer stack 202, for example, during subsequent formation of the contact 227 (see fig. 10B).

In some embodiments, to form the stepped region 231, a patterned photoresist having a first width (e.g., along the direction of the cross-section BB) is formed over the dielectric layer 201T, and a first anisotropic etch process is performed to pattern the dielectric layer 201T and expose the layer stack 202D. In other words, the first anisotropic etch process stops when the upper surface of conductive layer 203 of layer stack 202D is exposed. Next, the width of the patterned photoresist is reduced (e.g., by a photoresist trimming process), and a second anisotropic etch process is performed to pattern the layer stack 202D and expose the layer stack 202C. In other words, when the layer stack 202CThe second anisotropic etching process is stopped when the upper surface of the conductive layer 203 is exposed. The second anisotropic etch process also removes the exposed portions of the dielectric layer 201T, thus reducing the width of the dielectric layer 201T. The above process is repeated, wherein for each additional anisotropic etch process, the width of the patterned photoresist is reduced until the upper surface of the conductive layer 203 of the layer stack 202A is exposed by the patterned layer stack 202B. The patterned photoresist may then be removed, for example, by an ashing or stripping process. In some embodiments, the usage includes CF₄、C₄F₈、BCl₃、Cl₂、CCl₄、SiCl₄、CH₂F₂The gas source, the like, or a combination thereof performs an anisotropic etch process (e.g., a dry etch process, such as a plasma etch process).

In the present invention, the stepped region 23 is formed early in the manufacturing process before the memory cells are formed in the memory array region 233. This fabrication process is referred to as step-first post-processing, which is different from step-last post-processing in which the stepped region is formed after the memory cell is formed. By initially forming the stepped region 231, the anisotropic etching process that forms the stepped region 231 has less material (e.g., 201 and 203) to etch, and thus, an etchant (e.g., etching gas) that can achieve a target etch selectivity and a target etch profile (e.g., post-etch sidewall profile) is easily selected. As a result of the stair-step process being performed first, process problems such as multi-film etch challenges (e.g., due to more material to be etched, such as ferroelectric material 213, channel material 207, and additional dielectric material 209/212) and defects (e.g., stair-step pattern failures due to non-volatile byproducts in the etch process) that are subsequently performed are reduced or avoided. Thus, the disclosed step-look-ahead process achieves better process control and etch profile while reducing defects and improving yield and device performance.

Next, in fig. 4, a dielectric material 205 is formed over the dielectric layer 201T and over the layer stack 202. A planarization process, such as Chemical and Mechanical Planarization (CMP), may be performed so that the upper surface of dielectric material 205 is flush with the upper surface of dielectric layer 201T. In some embodiments, dielectric material 205 is formed by depositing a suitable dielectric material such as silicon oxide, silicon nitride, or the like using a suitable deposition method such as PVD, CVD, or the like.

Next, in fig. 5, a trench 206 is formed. A trench 206 (which may also be referred to as an opening, recess, or trench) is formed to extend through dielectric layer 201T, dielectric material 205, and layer stack 202 (remainder). In the example of fig. 5, the longitudinal axis of the trench 206 extends in the direction of the cross-section B-B (see fig. 3A). The trench 206 extends continuously between opposing sidewalls of the layer stack 202A such that the trench 206 passes through the structure of fig. 4 and separates the structure of fig. 4 into multiple slices that are separated (e.g., spaced apart) from each other.

Next, in fig. 6, ferroelectric material 213 is formed (e.g., conformally) in trench 206 along the sidewalls and bottom of trench 206, and channel material 207 is formed (e.g., conformally) over ferroelectric material 213. A dielectric material 209 is then formed over the channel material 207 to fill the trench 206. A planarization process such as CMP may be performed to remove excess portions of ferroelectric material 213, excess portions of channel material 207, and excess portions of dielectric material 209 from the upper surface of dielectric layer 201T and the surface of dielectric material 205. The remaining ferroelectric material 213 in the trench 206 may be referred to as a ferroelectric film 213 and the remaining channel material 207 in the trench 206 may be referred to as a channel layer 207.

In some embodiments, the ferroelectric material 213 comprises BaTiO₃、PbTiO₃、PbZrO₃、LiNbO₃、NaNbO₃、KNbO₃、KTaO₃、BiScO₃、BiFeO₃、Hf_1-xEr_xO、Hf_1-xLa_xO、Hf_1-xY_xO、Hf_1-xGd_xO、Hf_1-xGd_xO、Hf_1-xTi_xO、Hf_{1- x}Ta_xO, AlScN, etc., combinations thereof, or multilayers thereof, and may be formed by suitable formation methods such as PVD, CVD, ALD, and the like. In some embodiments, the channel material 207 is a semiconductor material, such as amorphous silicon (a-Si), polysilicon (pol)y-Si), a semiconductor oxide (e.g., Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Tin Oxide (ITO), or indium tungsten oxide (IWO)), or the like. The channel layer 207 may be formed, for example, by PVD, CVD, ALD, combinations thereof, and the like. In some embodiments, the dielectric material 209 is formed by depositing a suitable dielectric material such as silicon oxide, silicon nitride, or the like using a suitable deposition method such as PVD, CVD, ALD, or the like.

Next, in fig. 7, conductive lines 216 are formed in the memory array region 233 and extend vertically through the dielectric layer 201T and the layer stack 202. The conductive lines 216 are conductive columns (which may also be referred to as metal columns or metal lines) that extend vertically (e.g., perpendicular to the upper surface of the substrate 50) through the memory array region 233 and are electrically coupled to the conductive layers 203 of the layer stacks 202A, 202B, 202C, and 202D. To form the conductive lines 216, openings are formed in the dielectric material 209 in the memory array region 233 (e.g., by photolithography and etching techniques), the openings extending from an upper surface of the dielectric layer 201T to a lower surface of the layer stack 202A facing the substrate 50. Next, one or more conductive materials, such as Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, etc., are formed to fill the openings, thereby forming the conductive lines 216.

Next, in fig. 8A, an isolation region 212 is formed in each of the conductive lines 216 to divide each of the conductive lines 216 into pairs of conductive lines 215A and 215B. For ease of discussion, conductive lines 215A and 215B may be collectively referred to as conductive lines 215. The isolation regions 212 may be formed by performing an anisotropic etch process to form openings in each of the conductive lines 216, and then filling the openings with a dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable formation method, such as CVD, PVD, ALD, or the like.

Fig. 8B shows a top view of a portion of the memory array region 233 of the memory device 200 of fig. 8A. Fig. 8C, 8D, and 8E show cross-sectional views of portions of the memory device 200 in fig. 8B along section C-C, section D-D, and section E-E, respectively. As shown in the top view of fig. 8B, each isolation region 212 continuously extends from a first sidewall of the ferroelectric material 213 to a second sidewall of the ferroelectric material 213 facing the first sidewall of the ferroelectric material. In other words, the width of the isolation region 212 measured along the horizontal direction of fig. 8B is the same as the distance between the inner sidewalls of the ferroelectric material 213 in the trench and facing each other. In addition, each conductive line 215 extends continuously from a first sidewall of the channel material 207 to a second sidewall of the channel material 207 that faces the first sidewall of the channel material. In other words, the width of the conductive line 215 as measured along the horizontal direction of fig. 8B is the same as the distance between the inner sidewalls of the channel material 207 in the trench and facing each other.

In FIG. 8B, some, but not all, of the memory cells 223 (e.g., 223A, 223B, 223C) formed in the memory array region are highlighted with dashed boxes. In fig. 8C and 8D, memory cell 223 is also highlighted by a dashed box. As shown in fig. 8A to 8E, each memory cell 223 is a transistor having an embedded ferroelectric film 213. Within each memory cell 223, conductive layer 203 (see, e.g., fig. 8C and 8D) serves as a gate electrode of the transistor, conductive lines 215A and 215B serve as source/drain regions of the transistor, and channel material 207 serves as a channel layer between the source/drain regions. Dashed line 221 in fig. 8B (see also fig. 8C and 8D) shows a channel region formed in channel material 207 during operation of memory device 200 (e.g., when a voltage is applied at the gate of a transistor and the transistor is turned on). The direction of electrical polarization of ferroelectric film 213 in each memory cell 223 is indicative of the digital information (e.g., "0" or "1") stored in memory cell 223 and determines the threshold voltage of the transistor of memory cell 223, as will be discussed in more detail below.

In the case of a memory device, the conductive layer 203 (e.g., gate electrode) in each memory cell 223 is referred to as a Word Line (WL) of the memory cell, and the conductive lines 215A and 215B (e.g., source/drain regions) may be referred to as a Source Line (SL) and a Bit Line (BL) of the memory cell. The source lines may also be referred to as scan lines.

As shown in fig. 8A, each conductive layer 203 (e.g., WL) of the memory device 200 electrically connects a plurality of memory cells formed along the same horizontal plane (e.g., the same vertical distance from the substrate 50). Further, as shown in fig. 8C-8D, each SL or BL215 electrically connects a plurality of vertically stacked memory cells 223. Accordingly, the disclosed 3D memory device 200 enables efficient sharing of WL, BL, and SL among a plurality of memory cells 223, and the 3D structure of the memory cells 223 allows the multi-layered memory cells 223 to be easily stacked together to form a high-density memory array.

Next, in fig. 9, the channel material 207 disposed in the stepped region 231 is removed, and a dielectric material 208 is formed to fill the space left by the removed channel material 207. In some embodiments, to remove channel material 207 in the stepped region 231, a patterned masking layer (e.g., a patterned photoresist) is formed over the memory device 200 to cover the memory array region 233 and expose the stepped region 231. Next, an etch process using an etchant that is selective to the channel material 207 (e.g., has a higher etch rate) is performed to selectively remove the exposed channel material 207. Next, a dielectric material 208 is formed to fill the space left by the removed portion of the channel material 207. Dielectric material 208 may be formed of the same or similar material as dielectric material 205 and therefore will not be described in detail herein. The interface between dielectric material 208 and dielectric material 209 is represented by the dashed line in fig. 9, which may or may not be visible in the final product.

Next, in fig. 10A, contacts 225 are formed over the memory array region 233 and electrically connected to the corresponding SL/BL215, and contacts 227 are formed over the stepped region 231 and electrically connected to the corresponding WL 203. The contact 227 may be formed by forming an opening in the dielectric material 205 and filling the opening with a conductive material. The contact 225 may be formed by forming a dielectric layer (not shown) over the upper surface of the dielectric material 205, forming an opening in the dielectric layer, and filling the opening with a conductive material. Fig. 10B illustrates a cross-sectional view of the 3D memory device 200 of fig. 10A along section F-F. As shown in fig. 10B, contacts 227 are formed to extend through dielectric material 205, and each contact 227 is electrically coupled to a respective conductive layer 203 (e.g., WL 203). The stepped region allows WL203 to easily contact 227 as shown in fig. 10B. The contacts 225 and 227 may be connected, for example, to underlying electrical components or circuits in the substrate 50 (see fig. 1) and/or the interconnect structure 140 through, for example, vias 124 and conductive lines 125.

Referring to fig. 8A-8E and 10A, to perform a write operation on a particular memory cell 223, a write voltage is applied across a portion of the ferroelectric material 213 within the memory cell 223. For example, the write voltage may be applied by applying a first voltage to the gate electrode 203 of the memory cell 223 (through contact 227) and a second voltage to the source/drain regions 215A/215B (through contact 225). The voltage difference between the first voltage and the second voltage sets the polarization direction of the ferroelectric material 213. Depending on the polarization direction of the ferroelectric material 213, the threshold voltage VT of the respective transistor of the memory cell 223 may be switched from the low threshold voltage VL to the high threshold voltage VH and vice versa. The threshold voltage value (VL or VH) of the transistor may be used to indicate a bit "0" or "1" stored in the memory cell.

To perform a read operation on memory cell 223, a read voltage that is a voltage between low threshold voltage VL and high threshold voltage VH is applied to gate electrode 203. Depending on the polarization direction of the ferroelectric material 213 (or the threshold voltage VT of the transistor), the transistor of the memory cell 223 may be conductive or non-conductive. As a result, when a voltage is applied between the source/drain regions 215A and 215B, for example, a current may or may not flow between the source/drain regions 215A and 215B. The current can be sensed to determine the digital bit stored in the memory cell.

Fig. 11 and 12 show perspective views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device 200A at various stages of fabrication in another embodiment. The 3D FeRAM device 200A is similar to the 3D FeRAM device 200 of fig. 10A, but the channel material 207 and ferroelectric material 213 are removed from the stepped region 231. For example, the 3D FeRAM device 200A may be formed by following the processes shown in fig. 2A, fig. 2B, fig. 3A, fig. 3B, fig. 4 to fig. 7, fig. 8A, fig. 8B, fig. 8C, fig. 8D, and fig. 8E. Then, in the processing step of fig. 9, the channel material 207 and the ferroelectric material 213 are removed from the stepped region 231, for example, using one or more selective etch processes. Dielectric material 208 may then be formed to fill the space left by the removed portion of channel material 207 and the removed portion of ferroelectric material 213. Next, in fig. 12, contacts 225 and 227 are formed in accordance with the same or similar process as fig. 10A.

Fig. 13-19 show perspective views of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device 200B at various stages of fabrication in yet another embodiment. The 3D FeRAM device 200B is similar to the 3D FeRAM device 200 of fig. 10A, but with the ferroelectric material 213 and the channel material 207 formed only in the memory array region 233. In particular, the process in fig. 13 follows the process steps of fig. 2A, 2B, 3A, 3B, and 4. After the process of fig. 4, trenches 232 are formed in memory array region 233. The trench 232 extends through the dielectric layer 201T and the layer stack 202. In the illustrated embodiment, the length of trench 232 (see FIG. 3A) measured along the direction of cross-section B-B is the same as the length of memory array region 233. Thus, in the example of fig. 13, the trench 232 does not extend into the stepped region 231. In other embodiments, the length of the trench 232, measured along the direction of cross-section B-B, is less than or greater than the length of the memory array region 233.

Next, in fig. 14, ferroelectric material 213 is formed (e.g., conformally) along the sidewalls and bottom of trench 232, and channel material 207 is formed (e.g., conformally) on ferroelectric material 213. A dielectric material 209 is then formed over the channel material 207 to fill the trenches 232. A planarization process such as CMP may be performed to remove excess portions of ferroelectric material 213, excess portions of channel material 207, and excess portions of dielectric material 209 from the upper surface of dielectric layer 201T and the surface of dielectric material 205. The remaining ferroelectric material 213 in the trench 232 may be referred to as a ferroelectric film 213, and the remaining channel material 207 in the trench 232 may be referred to as a channel layer 207.

Next, in fig. 15, conductive lines 216 are formed in the dielectric material 209. Next, in fig. 16, an isolation region 212 is formed in each of the conductive lines 216 to separate each of the conductive lines 216 into pairs of conductive lines 215A and 215B. The processing is the same or similar to that discussed above with reference to fig. 7 and 8A-8E, and therefore, details are not repeated.

Next, in fig. 17, a trench 234 is formed in the stepped region 231. The trench 234 extends through the dielectric layer 201T and the layer stack 202. In some embodiments, the trench 234 is formed by forming a patterned photoresist over the memory device 200B, wherein a pattern (e.g., an opening) of the patterned photoresist exposes a region of the stepped region 231 where the trench 234 is to be formed. Next, an anisotropic etching process is performed using the patterned photoresist as an etching mask to remove the exposed portion of the 3D memory device 200B. As shown in fig. 17, the trench 234 exposes the sidewall 213S of the ferroelectric material 213. Note that regardless of the length of trench 232 in fig. 13, the dimensions of trench 234 are adjusted to accommodate the length of trench 232 in fig. 13 so that sidewalls 213S of ferroelectric material 213 are exposed by trench 234. After the etching process, the patterned photoresist may be removed, for example, by an ashing or stripping process.

Next, in fig. 18, a dielectric material is formed to fill the trench 234. In the illustrated embodiment, the dielectric material filling trench 234 is the same as dielectric material 205, and thus dielectric material 205 in fig. 17 and the dielectric material filling trench 234 may be collectively referred to as dielectric material 205 in fig. 18. A planarization process such as CMP may be performed to expose the upper surface of dielectric layer 201T and achieve a coplanar upper surface between dielectric material 205 and dielectric layer 201T.

Next, in fig. 19, contacts 225 are formed over memory array region 233 and electrically coupled to corresponding SL/BLs 215, and contacts 227 are formed over staircase region 231 and electrically coupled to corresponding WLs 203.

Fig. 20 shows an equivalent circuit diagram 300 of a three-dimensional (3D) ferroelectric random access memory (FeRAM) device in an embodiment. The circuit diagram 300 may correspond to a portion of a 3D memory device disclosed herein, such as 200, 200A, or 200B.

Fig. 20 shows three horizontally extending WLs (e.g., WL0, WL1, and WL2) at three vertical levels, which correspond to three different WLs 203 of the 3D FeRAM device 200, 200A, or 200B. The memory cells at each vertical level are shown as transistors. The gate electrodes of the transistors at the same vertical level are connected to the same WL. Fig. 20 also shows vertically extending BL (e.g., BL0, BL 1.., BL5) and SL (e.g., SL0, SL 1.., SL 5). BL and SL correspond to BL215A and SL215B of, for example, example 3D FeRAM device 200/200A/200B. Each of the BL and SL is connected to a plurality of vertically stacked memory cells.

In some embodiments, fig. 21 shows a flow diagram of a method 1000 of forming a three-dimensional (3D) ferroelectric random access memory (FeRAM) device. It should be understood that the embodiment method shown in FIG. 21 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in FIG. 21 may be added, removed, replaced, rearranged, or repeated.

Referring to fig. 21, at block 1010, a first layer stack and a second layer stack are continuously formed over a substrate, wherein the first layer stack and the second layer stack have a same layer structure comprising a conductive material on a first layer of a dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack. At block 1020, a trench is formed that extends through the first layer stack and the second layer stack. At block 1030, the sidewalls and bottom of the trench are lined with a ferroelectric material. At block 1040, channel material is conformally formed in the trench over the ferroelectric material. At block 1050, the trench is filled with a second dielectric material. At block 1060, a first opening and a second opening are formed in the second dielectric material. At block 1070, the first opening and the second opening are filled with a second conductive material.

Variations and modifications to the disclosed embodiments are possible, and are intended to be fully included within the scope of the invention. For example, as a non-limiting example, four layer stacks 202 (e.g., 202A, 202B, 202C, and 200D) are shown in the 3D memory devices 200, 200A, and 200B. As will be readily understood by a person skilled in the art, the number of layer stacks 202 in the 3D memory device may be any suitable number, such as one, two, three or more than four. As another example, the number of trenches formed (e.g., 206 in fig. 5 or 232 in fig. 13) may be any suitable number other than the three trenches shown. As yet another example, the number of conductive lines 215 formed in each row of dielectric material 209 (e.g., each row formed in a trench) may be any suitable number. As yet another example, in the illustrated embodiment, as a non-limiting example, the staircase shape regions 231 are formed on opposite sides of the memory array region 233. The memory devices 200, 200A, and 200B may be formed by forming only one stepped region 231 adjacent to the memory array region 233.

Embodiments may realize advantages. The disclosed step-first process avoids or reduces problems associated with step-after-processes, such as multi-film etch challenges and defects (e.g., step pattern failure caused by non-volatile byproducts such as etch modes). As a result, the disclosed step advance process achieves better process control and etch profile while reducing defects and improving yield and device performance. The disclosed 3D memory device can be easily integrated into existing semiconductor devices during BEOL processing. The area under the 3D memory device may still be used to form various circuits, such as logic circuits, I/O circuits, or ESD circuits, during FEOL processing. Therefore, there is little loss in the footprint of integrating the disclosed 3D memory device, except for the peripheral circuits (e.g., decoders, amplifiers) and routing circuits for the 3D memory device. In addition, the disclosed 3D memory device has an efficient structure to reduce its memory cell size. For example, each BL or SL is shared by a plurality of vertically stacked memory cells. Each WL is shared by a plurality of horizontally aligned memory cells formed at the same vertical distance from the substrate. As described above, the disclosed 3D memory devices have a structure that can be easily scaled to allow high density memory arrays to be formed, which is important for emerging applications such as internet of things (IoT) and machine learning. By integrating the 3D memory array on-chip during BEOL processing, problems such as power bottlenecks due to off-chip memory accesses can be avoided. As a result, semiconductor devices incorporating the disclosed 3D memory devices may be made smaller, less expensive, while operating at faster speeds and consuming less power.

According to an embodiment, a method of forming a ferroelectric random access memory (FeRAM) device includes: successively forming a first layer stack and a second layer stack over a substrate, wherein the first layer stack and the second layer stack have a first dielectric layer and a conductive layer formed over the first dielectric layer, respectively; forming a second dielectric layer over the second layer stack; patterning the first layer stack, the second layer stack, and the second dielectric layer, wherein the patterning forms a stepped region, wherein in the stepped region, the second layer stack extends beyond a lateral extent of the second dielectric layer, and the first layer stack extends beyond a lateral extent of the second layer stack, wherein after the patterning, the conductive layers of the first layer stack and the second layer stack form a first word line and a second word line, respectively; after patterning, forming a trench extending through the first layer stack, the second layer stack, and the second dielectric layer; lining the sidewalls and bottom of the trench with a ferroelectric material; forming a channel material on the ferroelectric material; filling the trench by forming a dielectric material over the channel material; source and bit lines are formed in the dielectric material, wherein the source and bit lines extend through the second dielectric layer, the second layer stack, and the first layer stack. In an embodiment, in the stepped region, the second layer stack extends beyond a lateral extent of the second dielectric layer along the first direction, and the first layer stack extends beyond a lateral extent of the second layer stack along the first direction. In an embodiment, the groove is formed with a longitudinal axis along the first direction. In an embodiment, after patterning, sidewalls of the patterned second dielectric layer define a memory array region adjacent to the stepped region. In an embodiment, a trench is formed to extend through the memory array region and the stepped region. In an embodiment, the method further includes removing channel material from the stepped region after forming the source line and the bit line. In an embodiment, the method further includes removing the channel material and the ferroelectric material from the stepped region after forming the source line and the bit line. In an embodiment, a trench is formed within a memory array region. In an embodiment, the bit lines and the source lines are formed within a memory array region, wherein the method further comprises: forming a first contact over the memory array region and electrically coupled to a bit line and a source line; and forming a second contact on the stepped region and electrically connected to the first word line and the second word line. In an embodiment, the source lines and the bit lines are formed of a conductive material, wherein longitudinal axes of the source lines and the bit lines are perpendicular to an upper surface of the substrate. In an embodiment, in a top view, the source line and the bit line extend continuously from a first sidewall of the channel material to a second sidewall of the channel material facing the first sidewall of the channel material. In an embodiment, the method further comprises: forming another source line in the dielectric material adjacent to the bit line; and forming an isolation region between and in contact with the bit line and another source line, wherein, in a top view, the isolation region extends continuously from a first sidewall of the ferroelectric material to a second sidewall of the ferroelectric material facing the first sidewall of the ferroelectric material.

According to an embodiment, a method of forming a ferroelectric random access memory (FeRAM) device includes: successively forming a first layer stack and a second layer stack over the substrate, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material on a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack; forming a trench extending through the first layer stack and the second layer stack; lining the sidewalls and bottom of the trench with a ferroelectric material; forming channel material conformally in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in a second dielectric material; and filling the first opening and the second opening with a second conductive material. In an embodiment, the first layer stack extends in a first direction beyond a lateral extent of the second layer stack, wherein a longitudinal axis of the groove is formed to extend along the first direction. In an embodiment, the trench divides each of the first layer stack and the second layer stack into two separate portions. In an embodiment, the method further comprises removing at least a portion of the ferroelectric material disposed outside the boundaries of the second layer stack after filling the first opening and the second opening. In an embodiment, the trench is formed within a region defined by sidewalls of the second layer stack.

According to an embodiment, a ferroelectric random access memory (FeRAM) device includes: a first layer stack; a second layer stack on the first layer stack, wherein the first layer stack and the second layer stack have the same layer structure comprising a first layer of conductive material over a first layer of dielectric material, wherein the first layer stack extends beyond a lateral extent of the second layer stack; a second dielectric material embedded in the first layer stack and the second layer stack, the second dielectric material extending through the first layer stack and the second layer stack; a ferroelectric material between the second dielectric material and the first layer stack and between the second dielectric material and the second layer stack; a channel material between the ferroelectric material and the second dielectric material; and a conductive line embedded in the second dielectric material, wherein the conductive line extends through the first layer stack and the second layer stack. In an embodiment, the FeRAM device further comprises: a first dielectric layer over the second layer stack, wherein the second layer stack extends beyond a lateral extent of the first dielectric layer; and a second dielectric layer on the first layer stack and the second layer stack, wherein an upper surface of the second dielectric layer is flush with an upper surface of the first dielectric layer. In an embodiment, the FeRAM device further comprises an isolation region embedded in the second dielectric material, wherein the isolation region extends through the first layer stack and the second layer stack, wherein, in a top view, the isolation region extends continuously from a first sidewall of the insulating layer to a second sidewall of the ferroelectric material facing the first sidewall.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is, therefore, intended that the appended claims encompass any such modifications or embodiments.