阅读说明：本技术 一种基于磁性隧道结的位元结构 (Bit structure based on magnetic tunnel junction ) 是由 毛欣 张源梁 于 2020-06-10 设计创作，主要内容包括：本发明公开了一种基于磁性隧道结的位元结构,该位元结构包括两个MOS管、两个磁性隧道结、一条字线、两条源线以及两条位线；进行数据写入时,字线有效,位元结构中的两个MOS管共享源线与位线,两个磁性隧道结MTJ上经过稳定的电流并持续一段时间；选取某一个MTJ作为存储单元(另外一个作为参考单元),将数据写入；进行数据读出时,源线接地,两个位线偏置电压将两端位线分别上拉,产生作为存储单元的MTJ上电压V<Sub>MTJ1</Sub>和作为参考单元的MTJ上电压V<Sub>MTJ2</Sub>,将V<Sub>MTJ1</Sub>和V<Sub>MTJ2</Sub>接入比较器进行比较；得到数据读出结果。本发明的一种基于磁性隧道结的位元电路及其读出电路,具有实现简单,读出速度快的优点。(The invention discloses a bit structure based on a magnetic tunnel junction, which comprises two MOS (metal oxide semiconductor) tubes, two magnetic tunnel junctions, a word line, two source lines and two bit lines; when data is written, the word line is effective, two MOS tubes in the bit structure share a source line and a bit line, and stable current passes through the two Magnetic Tunnel Junctions (MTJ) and lasts for a period of time; selecting one MTJ as a storage unit (the other MTJ is used as a reference unit) and writing data; when data is read, the source line is grounded, two bit line bias voltages respectively pull up bit lines at two ends to generate a voltage V on the MTJ as a storage unit MTJ1 And a voltage V on the MTJ as a reference cell MTJ2 Will V MTJ1 And V MTJ2 Accessing a comparator for comparison; and obtaining a data reading result. The bit cell circuit based on the magnetic tunnel junction and the reading circuit thereof have the advantages of simple realization and high reading speed.)

1. A bit cell structure based on a magnetic tunnel junction is characterized in that the bit cell structure comprises two MOS tubes, two magnetic tunnel junctions, a word line, two source lines and a bit line;

wherein, the grid of the first MOS tube (4) is connected with the word line (1), the source is connected with the first source line (2), and the drain is connected with the reference layer (61) of the first magnetic tunnel junction MTJ 1; the grid electrode of the second MOS tube (5) is connected with the word line (1), the source electrode is connected with the second source line (3), and the drain electrode is connected with the free layer (71) of the second magnetic tunnel junction MTJ 2; the free layer (62) of the second magnetic tunnel junction MTJ2 is coupled to the first bit line (8), and the reference layer (72) of the second magnetic tunnel junction MTJ2 is coupled to the second bit line (9); the first and second bit lines (8) and (9) are respectively connected with the top metal layer (10), the free layer (62) of the first magnetic tunnel junction MTJ1 and the free layer (71) of the second magnetic tunnel junction MTJ2 are respectively connected with the bottom metal layer and are connected with the first and second MOS tubes (4) and (5), or the first and second bit lines (8) and (9) are respectively connected with the bottom metal layer (10), and the free layer (62) of the first magnetic tunnel junction MTJ1 and the free layer (71) of the second magnetic tunnel junction MTJ2 are respectively connected with the top metal layer and are connected with the first and second MOS tubes (4) and (5).

When data is written, the gates of the first and second MOS transistors (4) and (5) in the bit structure are opened simultaneously, and the same-direction current flows through the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2(6) and (7), so that two states of an anti-parallel state and a parallel state are written into the two magnetic tunnel junctions oppositely, namely, one magnetic tunnel junction is in an anti-parallel state, one magnetic tunnel junction is in a parallel state, or one magnetic tunnel junction is in a parallel state, and one magnetic tunnel junction is in an anti-parallel state; when data is read, the first source line (2) and the second source line (3) are grounded, bias voltages are applied to the first bit line (8) and the second bit line (9) corresponding to the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2(6) and (7), the bias voltages respectively act on the two magnetic tunnel junctions MTJ1 and MTJ2 through two circuits respectively composed of two MOS tubes connected in series, the voltages obtained by pulling up are a parallel voltage and an anti-parallel voltage or an anti-parallel voltage and a parallel voltage, and the parallel voltage is denoted as V_pThe voltage in the antiparallel state is denoted as V_APSelecting one magnetic tunnel junction as a storage unit and the other magnetic tunnel junction as a reference unit, and writing data into the storage unit; when data is read, the first and second source lines (2, 3) are grounded, and the first and second bit lines (8, 9) are pulled up by bias voltages to generate a magnetic tunnel junction upper voltage V as a memory cell_MTJ1Or V_MTJ2And a voltage V across the magnetic tunnel junction as a reference cell_MTJ2Or V_MTJ1Will V_MTJ1And V_MTJ2And accessing a comparator for comparison:

if the first magnetic tunnel junction MTJ1(6) is selected as the memory cell, then V_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2When the result is 0, the read data is 0; v_MTJ1＝V_P，V_MTJ2＝V_AP，V_MTJ1>V_MTJ2When the result is 1, the read data is 1;

v if the second magnetic tunnel junction MTJ2(7) is selected as the memory cell_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2If the result is 1, the read data is 1; v_MTJ1＝V_P，V_MTJ2＝V_AP，M_TJ1>V_MTJ2The result is 0, and the read data is 0.

Technical Field

The present invention relates to the field of integrated circuit design, and more particularly, to a bit cell (MTJBit cell) of a magnetic tunnel junction in an integrated circuit design.

Background

MRAM is a type of non-volatile random access memory. Unlike conventional memories, MRAM uses the magnetoresistive effect of materials to achieve the storage of data, and its core memory cell is a Magnetic Tunnel Junction (MTJ).

As shown in FIG. 1, is a typical magnetic tunnel junction (M)TJ) structural diagram. The Magnetic Tunnel Junction (MTJ) is primarily composed of a reference layer 100, an insulating barrier layer 200, and a free layer 300. The direction of the magnetic moment of the reference layer 100 remains unchanged and only the direction of the magnetic moment of the free layer 300 is changed to be either the same direction or opposite direction as the reference layer. MTJs rely on quantum tunneling effects to pass electrons through barrier layer 200. The tunneling probability of the polarized electrons is related to the relative orientation of the reference layer 100 and the free layer 300. When the magnetization directions of the reference layer 100 and the free layer 300 are the same, the tunneling probability of electrons is high, and the MTJ represents a low resistance state (Rp); when the magnetization directions of the reference layer 100 and the free layer 300 are opposite, the tunneling probability of electrons is low, and the MTJ represents a high resistance state (Rap). MRAM uses the Rp and Rap states of MTJ to represent logic states "0" and "1", respectively, to achieve data storage. When reading data, it is common practice to compare the read data with an internal reference cell by using an SA sense amplifier, and the comparison voltage generated by the reference bit is one-half V_P+V_AP. And reading data after comparing the difference value of the reference comparison voltage of the reading voltage domain through a sensitive amplifier.

Disclosure of Invention

The invention aims to provide a bit cell structure based on a magnetic tunnel junction, wherein an improved bit cell structure with two Magnetic Tunnel Junctions (MTJ) is utilized in a circuit, each writing and reading operation is simultaneously realized by the two MTJ, and a fast reading speed is realized by utilizing the principle that the voltage difference is larger than that of a traditional reading circuit.

The invention relates to a bit structure based on a magnetic tunnel junction, which is realized by the following technical scheme:

a bit structure based on magnetic tunnel junctions comprises two MOS tubes, two magnetic tunnel junctions, a word line, two source lines and two bit lines; wherein the content of the first and second substances,

wherein, the grid of the first MOS tube 4 is connected with the word line 1, the source is connected with the first source line 2, and the drain is connected with the reference layer 61 of the first magnetic tunnel junction MTJ 1; the gate of the second MOS transistor 5 is connected with the word line 1, the source is connected with the second source line 3, and the drain is connected with the free layer 71 of the second magnetic tunnel junction MTJ 2; the free layer 62 of the second magnetic tunnel junction MTJ2 is coupled to the first bit line 8, and the reference layer 72 of the second magnetic tunnel junction MTJ2 is coupled to the second bit line 9; the first and second bit lines 8 and 9 are connected to the top metal layer 10, respectively, and the free layer 62 of the first magnetic tunnel junction MTJ1 and the free layer 71 of the second magnetic tunnel junction MTJ2 are connected to the bottom metal layer and connected to the first and second MOS transistors 4 and 5, respectively; alternatively, the first and second bit lines 8 and 9 are connected to the bottom metal layer 10, respectively, and the free layer 62 of the first magnetic tunnel junction MTJ1 and the free layer 71 of the second magnetic tunnel junction MTJ2 are connected to the top metal layer and the first and second MOS transistors 4 and 5, respectively.

When data is written, the gates of the first and second MOS transistors 4 and 5 in the bit structure are simultaneously opened, and a current in the same direction flows through the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ26 and 7, so that two states of an antiparallel state and a parallel state are oppositely written into two magnetic tunnel junctions, that is, one magnetic tunnel junction is an antiparallel state, one magnetic tunnel junction is a parallel state, or one magnetic tunnel junction is a parallel state, and one magnetic tunnel junction is an antiparallel state; when data is read, the first and second source lines 2 and 3 are grounded, bias voltages are applied to the first and second bit lines 8 and 9 corresponding to the first and second magnetic tunnel junctions MTJ1 and MTJ26 and 7, the bias voltages are applied to the two magnetic tunnel junctions MTJ1 and MTJ2 through two circuits each composed of two MOS transistors connected in series, the voltages obtained by pulling up are a parallel voltage and an anti-parallel voltage or an anti-parallel voltage and a parallel voltage, and the parallel voltage is denoted as V_pThe voltage in the antiparallel state is denoted as V_APSelecting one magnetic tunnel junction as a storage unit and the other magnetic tunnel junction as a reference unit, and writing data into the storage unit; in data reading, the first and second source lines 2 and 3 are grounded, and the first and second bit lines 8 and 9 are biased to pull up the bit lines at both ends, respectively, to generate a magnetic tunnel junction upper voltage V as a memory cell_MTJ1Or V_MTJ2And a voltage V across the magnetic tunnel junction as a reference cell_MTJ2Or V_MTJ1Will V_MTJ1And V_MTJ2And accessing a comparator for comparison:

if the first magnetic tunnel junction MTJ1(6) is selected as the memory cell, then V_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2When the result is 0, the read data is 0; v_MTJ1＝V_P，V_MTJ2＝V_AP，V_MTJ1>V_MTJ2When the result is 1, the read data is 1;

v if the second magnetic tunnel junction MTJ2(7) is selected as the memory cell_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2If the result is 1, the read data is 1; v_MTJ1＝V_P，V_MTJ2＝V_AP，M_TJ1>V_MTJ2The result is 0, and the read data is 0.

Compared with the prior art, the bit cell circuit based on the magnetic tunnel junction has the advantages of being simple to implement and high in reading speed.

Drawings

FIG. 1 is a schematic diagram of a typical Magnetic Tunnel Junction (MTJ) structure;

FIG. 2 is a schematic diagram of a bit cell structure based on a magnetic tunnel junction according to the present invention;

FIG. 3 is a reference diagram of an embodiment of a readout circuit implemented using a magnetic tunnel junction based bit cell structure according to the present invention;

FIG. 4 is a schematic diagram of the working flow of the readout circuit implemented by using the bit cell structure based on the magnetic tunnel junction of the present invention.

Reference numerals:

1. the memory cell comprises a word line, 2, a first source line, 3, a second source line, 4, a first MOS (metal oxide semiconductor) transistor, 5, a second MOS transistor, 6, a first magnetic tunnel junction, 7, a second magnetic tunnel junction, 8, a first bit line, 9, a second bit line, 10, a top metal layer, 11 and a bottom metal layer; 61. a reference layer of the first magnetic tunnel junction, 62, a free layer of the first magnetic tunnel junction, 71, a free layer of the second magnetic tunnel junction, 72, a reference layer of the second magnetic tunnel junction, 100, a free layer, 200, a barrier layer, 300, a reference layer.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and examples.

FIG. 2 is a schematic diagram of a bit cell structure based on a magnetic tunnel junction according to the present invention. The MOS transistor comprises two MOS transistors (namely, a first MOS transistor 4 and a second MOS transistor 5), two magnetic tunnel junctions (namely, a first magnetic tunnel junction 6 and a second magnetic tunnel junction 7), a word line, two source lines and two bit lines, wherein the grid electrode of the first MOS transistor 4 is connected with the word line 1, the source electrode is connected with the first source line 2, and the drain electrode is connected with the reference layer 61 of the first magnetic tunnel junction MTJ 1; the gate of the second MOS transistor 5 is connected with the word line 1, the source is connected with the second source line 3, and the drain is connected with the free layer 71 of the second magnetic tunnel junction MTJ 2; the free layer 62 of the second magnetic tunnel junction is coupled to the first bit line 8 and the reference layer 72 of the second magnetic tunnel junction is coupled to the second bit line 9.

Referring to FIG. 3, a diagram of an embodiment of a sensing circuit implemented with a magnetic tunnel junction based bit cell structure according to the present invention is shown. The reading circuit comprises a bit structure based on a magnetic tunnel junction, two circuits which are connected with the first bit line and the second bit line of the bit structure and are respectively composed of two MOS tubes connected in series, and a comparator. The MOS tubes connected in series in pairs are connected in a mode that the source electrode is connected with the drain electrode. When data is written, the gates of the first and second MOS transistors 4 and 5 are simultaneously turned on, and currents in the same direction flow through the two Magnetic Tunnel Junctions (MTJ)6 and 7, and since the two Magnetic Tunnel Junctions (MTJ)6 and 7 are connected in the opposite manner, the states of the two Magnetic Tunnel Junctions (MTJ) after being written are opposite, for example, one is an anti-parallel state and one is a parallel state or one is a parallel state and one is an anti-parallel state. When data is read, the first and second source lines 2 and 3 are grounded, bias voltages are applied to the first and second bit lines 8 and 9 corresponding to the two Magnetic Tunnel Junctions (MTJ)6 and 7, the bias voltages are applied to the two Magnetic Tunnel Junctions (MTJ)6 and 7 through two circuits each including three MOS transistors connected in series, and the voltages obtained by pulling up are a parallel voltage and an anti-parallel voltage or an anti-parallel voltage and a parallel voltage due to the fact that the states of the two Magnetic Tunnel Junctions (MTJ)6 and 7 are opposite. The voltage across these terminals is denoted V_pAnd V_APThey are used as the input of a comparator for comparison and amplification, the conventional design using a reference MTJ as the comparison voltage, the reference voltage generatedVoltage is one-half potential of parallel state and antiparallel state, and the present invention is used as a comparative voltage difference (V) between both ends_p-V_AP) Larger, larger voltage differentials can increase the comparison speed of the comparator, and the additional reference MTJ array is also eliminated.

FIG. 4 is a schematic diagram of a working flow of a readout circuit implemented by using a bit cell structure based on a magnetic tunnel junction according to the present invention. The specific process is as follows:

when data writing is carried out, a word line is effective (opened), two MOS tubes in a bit structure share a source line and a bit line, and two Magnetic Tunnel Junctions (MTJ) pass through stable current and last for a period of time;

selecting one MTJ as a storage unit (the other MTJ is used as a reference unit) and writing data;

when data is read, the source line is grounded, two bit line bias voltages respectively pull up bit lines at two ends to generate a voltage V on the MTJ as a storage unit_MTJ1And a voltage V on the MTJ as a reference cell_MTJ2Will V_MTJ1And V_MTJ2Accessing a comparator for comparison;

if MTJ1 is selected as the memory cell, then V_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2When the result is 0, the read data is 0; v_MTJ1＝V_P，V_MTJ2＝V_AP，V_MTJ1>V_MTJ2When the result is 1, the read data is 1;

if MTJ2 is selected as the memory cell, V_MTJ1＝V_AP，V_MTJ2＝V_P，V_MTJ1<V_MTJ2If the result is 1, the read data is 1; v_MTJ1＝V_P，V_MTJ2＝V_AP，M_TJ1>V_MTJ2The result is 0, and the read data is 0.

The bit structure is suitable for being integrated into one-time programming devices such as mobile phones, computers, embedded chips, automobile electronic chips, industrial control chips, independent memories, handheld devices, radio frequency tags and the like.