Control circuit, chip and control method for controlling clock gating unit
阅读说明：本技术 用于控制时钟门控单元的控制电路、芯片及控制方法 (Control circuit, chip and control method for controlling clock gating unit ) 是由 刘君 于 2020-05-22 设计创作，主要内容包括：一种用于控制时钟门控单元的控制电路、芯片及控制方法,该控制电路包括第一控制模块和第二控制模块；第一控制模块包括第一功能逻辑电路、第一用户定义寄存器和第一逻辑门,第二控制模块包括扫描寄存器、第二用户定义寄存器、第三用户定义寄存器、多路选择器和第二逻辑门；在扫描寄存器与第一功能逻辑电路或第二功能逻辑电路存在线性相关性的情况下,第二控制模块通过用户定义向量配置第三用户定义寄存器的输出端的电平,以使多路选择器选择第二输入端作为输入,第二控制模块通过ATPG工具产生的增量向量对第一功能逻辑电路或第二功能逻辑电路进行测试。本申请实施例可以增加第一功能逻辑电路和第二功能逻辑电路的测试覆盖率。(A control circuit, a chip and a control method for controlling a clock gating unit are provided, wherein the control circuit comprises a first control module and a second control module; the first control module comprises a first functional logic circuit, a first user-defined register and a first logic gate, and the second control module comprises a scanning register, a second user-defined register, a third user-defined register, a multiplexer and a second logic gate; under the condition that the scanning register has linear correlation with the first functional logic circuit or the second functional logic circuit, the second control module configures the level of the output end of the third user-defined register through the user-defined vector so that the multiplexer selects the second input end as input, and the second control module tests the first functional logic circuit or the second functional logic circuit through the increment vector generated by the ATPG tool. The test coverage rate of the first functional logic circuit and the second functional logic circuit can be increased.)
1. A control circuit for controlling a clock gating cell, the control circuit comprising a first control module and a second control module; the first control module comprises a first functional logic circuit, a first user-defined register and a first logic gate, the second control module comprises a scanning register, a second user-defined register, a third user-defined register, a multiplexer and a second logic gate, and the clock gating unit drives the second functional logic circuit;
the output end of the first functional logic circuit is connected with the first input end of the first logic gate, the output end of the first user-defined register is connected with the second input end of the first logic gate, and the output end of the first logic gate is connected with the gate control enabling end of the clock gate control unit;
the output end of the scanning register is connected with the first input end of the multiplexer, the output end of the second user-defined register is connected with the second input end of the multiplexer, the output end of the third user-defined register is connected with the control end of the multiplexer, the output end of the multiplexer is connected with the first input end of the second logic gate, the control end of the scanning register is connected with the second input end of the second logic gate, the second input end of the second logic gate is connected with a scanning enabling signal, and the output end of the second logic gate is connected with the test enabling end of the clock gating unit; the enabling clock output end of the clock gating unit is connected with the clock input end of the second functional logic circuit;
and under the condition that the scanning register has linear correlation with the first functional logic circuit or the scanning register has linear correlation with the second functional logic circuit, the second control module configures the level of the output end of the third user-defined register through a user-defined vector so that the multiplexer selects the second input end of the multiplexer as an input, and the second control module tests the first functional logic circuit or the second functional logic circuit through an increment vector generated by an automatic test vector generation (ATPG) tool.
2. The control circuit of claim 1 wherein the second control module configures the level of the output of the third user-defined register with a user-defined vector to cause the multiplexer to select the first input of the multiplexer as the input in the absence of a linear correlation of the scan register with the first functional logic circuit and the scan register with the second functional logic circuit, the second control module testing the first functional logic circuit or the second functional logic circuit with a test vector generated by an ATPG tool.
3. The control circuit of claim 2, wherein the scan registers are serially connected into a scan chain, the first input of the scan register is connected to the output of the last scan register of the scan chain, and the output of the scan register is connected to the first input of the next scan register of the scan chain; and the second input end of the scanning register is connected with the output end of the scanning register.
4. The control circuit of claim 3 wherein the test vector generated by the ATPG tool is input to the first input of the scan register.
5. The control circuit of claim 4, wherein in the case where the second functional logic circuit comprises a first register, the first control module further comprises a fourth user-defined register, the second control module further comprises a fifth user-defined register;
the output end of the fourth user-defined register is connected with the third input end of the first logic gate, and the output end of the fifth user-defined register is connected with the third input end of the second logic gate.
6. The control circuit of claim 5, wherein the first logic gate comprises a first AND gate, a first NOT gate, and a second NOT gate, wherein a first input terminal of the first AND gate is a first input terminal of the first logic gate, a second input terminal of the first AND gate is connected to an output terminal of the first NOT gate, an input terminal of the first NOT gate is a second input terminal of the first logic gate, a third input terminal of the first AND gate is connected to an output terminal of the second NOT gate, and an input terminal of the second NOT gate is a third input terminal of the first logic gate;
the second logic gate comprises a first OR gate and a second AND gate, wherein a first input end of the first OR gate is a first input end of the second logic gate, a second input end of the first OR gate is a second input end of the second logic gate, an output end of the first OR gate is connected with a first input end of the second AND gate, a second input end of the second AND gate is a third input end of the second logic gate, and an output end of the second AND gate is an output end of the second logic gate.
7. The control circuit of claim 6, wherein an input of the fifth user-defined register is coupled to a Joint test action group, JTAG, test data input, an output of the fifth user-defined register is coupled to an input of the second user-defined register, an output of the second user-defined register is coupled to an input of the third user-defined register, an output of the third user-defined register is coupled to an input of the fourth user-defined register, an output of the fourth user-defined register is coupled to an input of the first user-defined register, and an output of the first user-defined register is coupled to a JTAG test data output.
8. The control circuit of claim 7,
when the scan test is performed on the scan chain, under the condition that the scan register has no linear correlation with the first functional logic circuit and the scan register has no linear correlation with the second functional logic circuit, the first control module configures the output of the fourth user-defined register to be at a low level and configures the output of the first user-defined register to be at a low level through a user-defined vector; the second control module configures the output of the fifth user-defined register to be a high level and configures the output of the third user-defined register to be a low level through a user-defined vector to control the multiplexer to select the first input end of the multiplexer as an input;
under the scan chain displacement mode of the scan test, the scan enable signal is at a high level, and the clock gating unit is conducted;
in a scan chain capturing mode of the scan test, the scan enable signal is at a low level, and whether to turn on the clock gating unit is determined by a level held by an output end of the scan register and a level output by the first logic gate.
9. The control circuit of claim 4, wherein in the case where the second functional logic circuit comprises a second register, a first memory, and a next level clock gating cell, the second control module further comprises a sixth user defined register and a seventh user defined register;
an output terminal of the sixth user-defined register is connected to the third input terminal of the second logic gate, and an output terminal of the seventh user-defined register is connected to the fourth input terminal of the second logic gate.
10. The control circuit of claim 9, wherein the first logic gate comprises a third and gate and a third not gate, a first input terminal of the third and gate is a first input terminal of the first logic gate, a second input terminal of the third and gate is connected to an output terminal of the third not gate, and an input terminal of the third not gate is a second input terminal of the first logic gate;
the second logic gate comprises a second or gate, a third or gate and a fourth and gate, a first input end of the second or gate is a first input end of the second logic gate, a second input end of the second or gate is a second input end of the second logic gate, an output end of the second or gate is connected with a first input end of the third or gate, a second input end of the third or gate is a third input end of the second logic gate, an output end of the third or gate is connected with a first input end of the fourth and gate, a second input end of the fourth and gate is a fourth input end of the second logic gate, and an output end of the fourth and gate is an output end of the second logic gate.
11. The control circuit of claim 10, wherein an input of the sixth user-defined register is coupled to a JTAG test data input, an output of the sixth user-defined register is coupled to an input of the second user-defined register, an output of the second user-defined register is coupled to an input of the third user-defined register, an output of the third user-defined register is coupled to an input of the seventh user-defined register, an output of the seventh user-defined register is coupled to an input of the first user-defined register, and an output of the first user-defined register is coupled to a JTAG test data output.
12. The control circuit of claim 11,
when the scan chain is subjected to scan test, the first control module configures the output of the first user-defined register to be low level through a user-defined vector under the condition that the scan register has no linear correlation with the first functional logic circuit and the scan register has no linear correlation with the second functional logic circuit; the second control module configures the output of the sixth user-defined register to be a low level, configures the output of the seventh user-defined register to be a high level, and configures the output of the third user-defined register to be a low level through a user-defined vector, so as to control the multiplexer to select the first input end of the multiplexer as an input;
under the scan chain displacement mode of the scan test, the scan enable signal is at a high level, and the clock gating unit is conducted;
in a scan chain capturing mode of the scan test, the scan enable signal is at a low level, and whether to turn on the clock gating unit is determined by a level held by an output end of the scan register and a level output by the first logic gate.
13. The control circuit of claim 11,
when the memory built-in self test is carried out, the second control module configures the output of the sixth user-defined register to be high level and configures the output of the seventh user-defined register to be high and low level through the user-defined vector.
14. The control circuit of claim 13,
and if the first memory does not need to carry out memory built-in self test, the second control module configures the output of the seventh user-defined register to be low level through a user-defined vector, and the first control module configures the output of the first user-defined register to be high level through the user-defined vector.
15. The control circuit of claim 4, wherein in the case where the second functional logic circuit comprises a second memory and a next level clock gating cell, the second control module further comprises an eighth user defined register;
the output end of the eighth user-defined register is connected with the third input end of the second logic gate, and the fourth input end of the second logic gate is connected with a test mode signal.
16. The control circuit of claim 15, wherein the first logic gate comprises a fifth and gate and a fourth not gate, a first input terminal of the fifth and gate is a first input terminal of the first logic gate, a second input terminal of the fifth and gate is connected to an output terminal of the fourth not gate, and an input terminal of the fourth not gate is a second input terminal of the first logic gate;
the second logic gate comprises a fourth or gate, a fifth or gate and a sixth and gate, a first input end of the fourth or gate is a first input end of the second logic gate, a second input end of the fourth or gate is a second input end of the second logic gate, an output end of the fourth or gate is connected with a first input end of the fifth or gate, a second input end of the fifth or gate is a third input end of the second logic gate, an output end of the fifth or gate is connected with a first input end of the sixth and gate, a second input end of the sixth and gate is a fourth input end of the second logic gate, and an output end of the sixth and gate is an output end of the second logic gate.
17. The control circuit of claim 16, wherein an input of the eighth user-defined register is coupled to a JTAG test data input, an output of the eighth user-defined register is coupled to an input of the second user-defined register, an output of the second user-defined register is coupled to an input of the third user-defined register, an output of the third user-defined register is coupled to an input of the first user-defined register, and an output of the first user-defined register is coupled to a JTAG test data output.
18. The control circuit of claim 17,
when the scan chain is subjected to scan test, the test mode signal is at high level, and the first control module configures the output of the first user-defined register to be at low level through a user-defined vector under the condition that the scan register does not have linear correlation with the first functional logic circuit and the scan register does not have linear correlation with the second functional logic circuit; the second control module configures the output of the eighth user-defined register to be a low level and configures the output of the third user-defined register to be a low level through a user-defined vector, so as to control the multiplexer to select the first input end of the multiplexer as an input;
under the scan chain displacement mode of the scan test, the scan enable signal is at a high level, and the clock gating unit is conducted;
in a scan chain capturing mode of the scan test, the scan enable signal is at a low level, and whether to turn on the clock gating unit is determined by a level held by an output end of the scan register and a level output by the first logic gate.
19. The control circuit of claim 17,
when the memory built-in self test is carried out, the test mode signal is at a high level, and the second control module configures the output of the eighth user-defined register to be at the high level through the user-defined vector.
20. The control circuit of claim 19,
and if the second memory does not need to carry out memory built-in self test, the second control module configures the output of the eighth user-defined register to be low level through a user-defined vector, and the first control module configures the output of the first user-defined register to be high level through the user-defined vector.
21. The control circuit according to any one of claims 4 to 20, wherein the scan chain is connected in series with an on-chip clock OCC chain; alternatively, the first and second electrodes may be,
the scan chain is directly connected with the input and output pins of the chip through a test machine channel.
22. The control circuit according to any one of claims 1 to 21, wherein in a case where the clock gating cell does not need to operate, the first control module configures a level of an output terminal of the first user-defined register by a user-defined vector so that the first logic gate outputs a low level, and the second control module controls a logic level of a test enable terminal of the clock gating cell to be a low level.
23. The control circuit according to any one of claims 1 to 22,
under the condition of testing the first functional logic circuit, the second control module controls the logic level of the test enabling end of the clock gating unit to be low level, and the first control module configures the level of the output end of the first user-defined register through a user-defined vector, so that the level of the output end of the first user-defined register does not influence the output of the first logic gate.
24. The control circuit according to any one of claims 1 to 22,
under the condition of testing the second functional logic circuit, the second control module controls the logic level of the test enabling end of the clock gating unit to be high level, or the first control module configures the level of the output end of the first user-defined register through a user-defined vector, so that the output of the first logic gate is high level.
25. The control circuit according to any one of claims 1 to 22, wherein the second control module controls the logic level of the test enable terminal of the clock gating cell to be low level in case that the second functional logic circuit does not need to be tested, and the first control module configures the level of the output terminal of the first user-defined register by a user-defined vector so that the output of the first logic gate is low level.
26. A chip comprising logic function circuitry, clock gating cells and a control circuit as claimed in any one of claims 1 to 25, the control circuit being arranged to control whether the clock gating cells are conducting when the chip is tested.
27. A control method for controlling a clock gating cell, the method being applied to a control circuit according to any one of claims 1 to 25, the control circuit comprising a first control module and a second control module; the first control module comprises a first functional logic circuit, a first user-defined register and a first logic gate, the second control module comprises a scanning register, a second user-defined register, a third user-defined register, a multiplexer and a second logic gate, and the clock gating unit drives the second functional logic circuit;
the output end of the first functional logic circuit is connected with the first input end of the first logic gate, the output end of the first user-defined register is connected with the second input end of the first logic gate, and the output end of the first logic gate is connected with the gate control enabling end of the clock gate control unit;
the output end of the scanning register is connected with the first input end of the multiplexer, the output end of the second user-defined register is connected with the second input end of the multiplexer, the output end of the third user-defined register is connected with the control end of the multiplexer, the output end of the multiplexer is connected with the first input end of the second logic gate, the control end of the scanning register is connected with the second input end of the second logic gate, the second input end of the second logic gate is connected with a scanning enabling signal, and the output end of the second logic gate is connected with the test enabling end of the clock gating unit; the enabling clock output end of the clock gating unit is connected with the clock input end of the second functional logic circuit;
the method comprises the following steps:
and under the condition that the scanning register has linear correlation with the first functional logic circuit or the scanning register has linear correlation with the second functional logic circuit, configuring the level of the output end of the third user-defined register through a user-defined vector so that the multiplexer selects the second input end of the multiplexer as input, and testing the first functional logic circuit or the second functional logic circuit through an increment vector generated by an automatic test vector generation (ATPG) tool.
Technical Field
The application relates to the technical field of chips, in particular to a control circuit, a chip and a control method for controlling a clock gating unit.
Background
In chip technology, clock gating units, especially Integrated Clock Gating (ICG) units, are used in large numbers to control the switching of clocks and thus to reduce power consumption. FIG. 1 is an integrated clock gating cell for a rising edge active clock. The CK terminal is a clock input terminal, and the ECK terminal is an enable clock output terminal. The E terminal is a gating enable terminal, and the TE terminal is a test enable terminal. The E-side is typically controlled by functional logic, and the TE-side is typically controlled by design for test (DFT) logic. When the E end or the TE end has more than one level value which is 1, the gating is conducted, and when the two level values are both 0, the gating is closed.
At present, the TE terminal is generally controlled by a scan enable signal and a logical phase or a subsequent value of a register, and in different test modes, the TE terminal is controlled to be 1 or 0, and when the TE terminal is 0, whether to turn on gating is determined by the value of the register and the value of the gating E terminal. And when the TE end is 1, controlling the clock gating unit to be conducted. When the TE terminal is 0, whether to turn on the gate control is determined by the value of the register and the value of the gate control E terminal, but whether the register is connected in series with the scan chain and its position is not determined.
Disclosure of Invention
The embodiment of the application provides a control circuit, a chip and a control method for controlling a clock gating unit, which can increase the test coverage rate of a first functional logic circuit and a second functional logic circuit.
A first aspect of an embodiment of the present application provides a control circuit for controlling a clock gating cell, the control circuit including a first control module and a second control module; the first control module comprises a first functional logic circuit, a first user-defined register and a first logic gate, the second control module comprises a scanning register, a second user-defined register, a third user-defined register, a multiplexer and a second logic gate, and the clock gating unit drives the second functional logic circuit;
the output end of the first functional logic circuit is connected with the first input end of the first logic gate, the output end of the first user-defined register is connected with the second input end of the first logic gate, and the output end of the first logic gate is connected with the gate control enabling end of the clock gate control unit;
the output end of the scanning register is connected with the first input end of the multiplexer, the output end of the second user-defined register is connected with the second input end of the multiplexer, the output end of the third user-defined register is connected with the control end of the multiplexer, the output end of the multiplexer is connected with the first input end of the second logic gate, the control end of the scanning register is connected with the second input end of the second logic gate, the second input end of the second logic gate is connected with a scanning enabling signal, and the output end of the second logic gate is connected with the test enabling end of the clock gating unit; the enabling clock output end of the clock gating unit is connected with the clock input end of the second functional logic circuit;
and under the condition that the scanning register has linear correlation with the first functional logic circuit or the scanning register has linear correlation with the second functional logic circuit, the second control module configures the level of the output end of the third user-defined register through a user-defined vector so that the multiplexer selects the second input end of the multiplexer as an input, and the second control module tests the first functional logic circuit or the second functional logic circuit through an increment vector generated by an automatic test vector generation (ATPG) tool.
A second aspect of the embodiments of the present application provides a chip, including a logic function circuit, a clock gating unit, and the control circuit of the first aspect of the embodiments of the present application, where the control circuit is used to control whether the clock gating unit is turned on when the chip is tested.
A third aspect of the embodiments of the present application provides a control method for controlling a clock gating unit, where the method is applied to the control circuit according to the first aspect of the embodiments of the present application, and the control circuit includes a first control module and a second control module; the first control module comprises a first functional logic circuit, a first user-defined register and a first logic gate, the second control module comprises a scanning register, a second user-defined register, a third user-defined register, a multiplexer and a second logic gate, and the clock gating unit drives the second functional logic circuit;
the output end of the first functional logic circuit is connected with the first input end of the first logic gate, the output end of the first user-defined register is connected with the second input end of the first logic gate, and the output end of the first logic gate is connected with the gate control enabling end of the clock gate control unit;
the output end of the scanning register is connected with the first input end of the multiplexer, the output end of the second user-defined register is connected with the second input end of the multiplexer, the output end of the third user-defined register is connected with the control end of the multiplexer, the output end of the multiplexer is connected with the first input end of the second logic gate, the control end of the scanning register is connected with the second input end of the second logic gate, the second input end of the second logic gate is connected with a scanning enabling signal, and the output end of the second logic gate is connected with the test enabling end of the clock gating unit; the enabling clock output end of the clock gating unit is connected with the clock input end of the second functional logic circuit;
the method comprises the following steps:
and under the condition that the scanning register has linear correlation with the first functional logic circuit or the scanning register has linear correlation with the second functional logic circuit, configuring the level of the output end of the third user-defined register through a user-defined vector so that the multiplexer selects the second input end of the multiplexer as input, and testing the first functional logic circuit or the second functional logic circuit through an increment vector generated by an automatic test vector generation (ATPG) tool.
In the control circuit in the embodiment of the application, when the scan register has a linear correlation with the first functional logic circuit or the scan register has a linear correlation with the second functional logic circuit, the second control module configures the level of the output end of the third user-defined register through the user-defined vector, so that the multiplexer selects the second input end of the multiplexer as an input, and the second control module generates the increment vector generated by the ATPG tool through the automatic test vector to test the first functional logic circuit or the second functional logic circuit. Because the output of the scanning register does not act on the test enabling end for controlling the clock gating unit, the linear correlation between the scanning register and the first functional logic circuit or the second functional logic circuit is eliminated, the increment vector generated by the ATPG tool can test the fault point which is not detected in the first functional logic circuit or the second functional logic circuit due to the linear correlation, and the test coverage rate of the first functional logic circuit and the second functional logic circuit can be increased.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an integrated clock gating cell provided in the prior art;
FIG. 2 is a control circuit for controlling a clock gating cell according to an embodiment of the present disclosure;
FIG. 3 is a diagram of another control circuit for controlling a clock gating cell according to an embodiment of the present disclosure;
FIG. 4 is a diagram of another control circuit for controlling a clock gating cell according to an embodiment of the present disclosure;
FIG. 5 is a diagram of another control circuit for controlling a clock gating cell according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a chip provided in an embodiment of the present application;
fig. 7 is a flowchart illustrating a control method for controlling a clock gating unit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a structure of an integrated clock gating unit according to the prior art. As shown in fig. 1, the integrated clock gating cell is an integrated clock gating cell for a rising edge active clock. The integrated clock gating cell may be comprised of a latch, an AND gate, and an OR gate. The CK (clock) terminal is a clock input terminal, and the ECK (enableclock) terminal is an enable clock output terminal. The E (enable) terminal is a gating enable terminal, and the TE terminal is a test enable terminal. The E-side is typically controlled by functional logic, and the TE-side is typically controlled by design for test (DFT) logic. When the E end or the TE end has more than one level value which is 1, the gating is conducted, and when the two level values are both 0, the gating is closed. When the gate control is conducted, the clock signal of the CK end is transmitted to the ECK end, and when the gate control is closed, the clock signal of the CK end cannot be transmitted to the ECK end.
Design for test (DFT) is the process of adding testability logic to the chip design. The DFT technology is to add DFT logic into chip design, then wait for the chip to make back, check the chip through the DFT logic added in advance, select qualified chip.
Referring to fig. 2, fig. 2 is a control circuit for controlling a clock gating unit according to an embodiment of the present disclosure. The control circuit comprises a
the output end of the first functional logic circuit 11 is connected to the first input end of the
an output terminal of the scan register 21 is connected to a first input terminal of the multiplexer 51 (the terminal 0 of the
in the case that the scan register 21 has a linear correlation with the first functional logic circuit 11 or the scan register 21 has a linear correlation with the second
In the embodiment of the present application, the User-defined Register may also be referred to as a User-defined Test Data Register (UDTR), where the UDTR is a User-defined Test Data Register conforming to an institute of Electrical and Electronics Engineers (IEEE std)1149.1 protocol, and has a clock signal of j tag _ clk and a power-on reset value of 0. The user-defined register may be composed of a D flip-flop, and the input terminal of the user-defined register is a D terminal, the output terminal is a Q terminal, and the clock terminal is CLK. The CLK terminal is clocked by the clock signal jtag _ CLK. When the CLK terminal has no level pulse, no matter what the value of the D terminal is, the state of the Q terminal of the user-defined register remains unchanged, when the CLK terminal has a pulse effect (i.e., a rising edge or a falling edge), if the current value of the Q terminal is the same as the value input by the D terminal, the Q terminal remains unchanged, and if the current value of the Q terminal is different from the value input by the D terminal, the Q terminal is inverted.
The first user-defined
The user-defined vector, which is user-preconfigured, is used to control the level of the output of the user-defined register in the jtag chain. Different user-defined vectors may correspond to different test patterns. After the configured levels of the outputs of the user-defined registers in the jtag chain, the ATPG tool can calculate and generate ATPG vectors for testing according to the levels of the outputs of the respective user-defined registers in the jtag chain and the circuit structure of the module to be tested.
The
In the embodiment of the present application, a scan register (SDFF) is a register for performing scan test. The scan register 21 in fig. 2 is labeled SDFF 0. Scan register 21 may be chained into a scan chain. The scanning registers in the scanning chain are sequentially connected, and the output end of the previous scanning register is connected with the first input end of the next scanning register. The scan register 21 may be composed of a D flip-flop and a multiplexer. The SCAN register 21 comprises two input terminals (a first input terminal SI and a second input terminal D), an output terminal Q, a control terminal SE and a clock terminal CLK, wherein the control terminal SE is connected to the SCAN enable SCAN _ EN signal, and the clock terminal CLK is connected to the clock signal Func _ CLK. When the SE terminal is at a high level, the scan register 21 selects the SI terminal as an input, and enters a scan mode, which is equivalent to a shift register; when the SE terminal is at a low level, the scan register 21 selects the D terminal as an input, which corresponds to a normal register.
In digital circuits, a low level is used to represent a logic "0" and a high level is used to represent a logic "1".
In scan mode, the first input SI of scan register 21 may be connected to a chip input pin input through a tester channel. The string of values input to the first input SI of the scan register 21 is called an Automatic Test Pattern Generation (ATPG) vector. The ATPG vector is derived and calculated by ATPG tool.
The ATPG tool is a software program with an ATPG function, can generate an ATPG vector and output the ATPG vector to a tested device, and obtains a test result by comparing an output result of the tested device with the generated ATPG vector. ATPG is a process in which test pattern vectors used in a semiconductor electrical appliance test are automatically generated by a program. The test vectors are sequentially loaded onto the input pins of the device, and the output signals are collected and compared with the predicted test vectors to determine the results of the test. ATPG effectiveness is an important indicator for measuring test error coverage.
With the continuous development of modern industrial technologies, the integration level of digital circuits is higher and higher, and more Intellectual Property cores (IPs) are integrated on System-on-a-chips (SOCs), and the functions are more and more complex. In the testing process, in order to ensure higher test fault coverage rate, the increasing complexity of the chip greatly increases the test data volume, and the length of the scan chain for testing is also increased, thereby increasing the test workload of the ATPG tool. In order to reduce the workload of testing and improve the testing efficiency, the scan chain needs to be compressed. However, compression of the scan chain may cause scan register 21 to have a linear dependence on the register in the functional logic circuit to be tested.
The linear correlation between registers means that in some vectors generated by the ATPG tool, two registers cannot output (load) the required value at the same time. For example, if a fault point in the first functional logic circuit 11 needs to be tested, the test enable of the
In this embodiment, when there is a linear correlation between the scan register 21 and the first functional logic circuit 11 or there is a linear correlation between the scan register 21 and the second
In the embodiment of the present application, since the output of the scan register 21 does not act on the TE terminal of the control
Optionally, in a case that there is no linear correlation between the scan register 21 and the first functional logic circuit 11 and there is no linear correlation between the scan register 21 and the second
In the embodiment of the present application, in the case that there is no linear correlation between the scan register 21 and the first functional logic circuit 11 and there is no linear correlation between the scan register 21 and the second
Optionally, the scan register 21 is serially connected into a scan chain, a first input end of the scan register 21 is connected with an output end of a previous scan register 21 of the scan chain, and an output end of the scan register 21 is connected with a first input end of a next scan register 21 of the scan chain; a second input of the scan register 21 is connected to an output of the scan register 21. Of course, if scan register 21 is the first scan register of a scan chain, its first input is not connected to other scan registers, and if scan register is the last scanner of a scan chain, its output is not connected to other scan registers.
Optionally, the test vector generated by the ATPG tool is input to a first input terminal (SI terminal) of the scan register 21. The increment vector generated by the ATPG tool is input to a first input (SI terminal) of the scan register 21.
Optionally, the scan chain is connected in series with an on-chip clock OCC chain; alternatively, the first and second electrodes may be,
the scan chain is directly connected with the input and output pins of the chip through a test machine channel.
In the embodiment of the present application, the scan chain and the on-chip clock (OCC) chain are used to reduce linear correlation, and the OCC chain is used to control the clock signal and has a relatively high priority. The scan chain is directly connected with the chip input and output pins through the tester channel, a pair of chip input and output pins can be independently provided for the scan chain to be directly connected with the tester channel, and the linear correlation between the scan chain and other scan chains can be reduced.
Optionally, in a case that the
In the embodiment of the present application, to turn off the
Optionally, in a case of testing the first functional logic circuit 11, the
In the embodiment of the present application, when the first functional logic circuit 11 is tested, it is necessary to avoid the influence of the
Optionally, in the case of testing the second
In the embodiment of the present application, in the case of testing the second
Optionally, in a case that the second
In this embodiment, the
Alternatively, the clock gating cell controlling the first functional logic 11 may be turned off in case the first functional logic 11 does not need to be tested.
Referring to fig. 3, fig. 3 is a diagram illustrating another control circuit for controlling a clock gating unit according to an embodiment of the present disclosure. Fig. 3 is further optimized on the basis of fig. 2, the clock gating cell of fig. 3 being used to drive a second
The second
The
the
The not gate may also be referred to as an inverter. The high level (1) may be converted to the low level (0), and the low level (0) may be converted to the high level (1).
Wherein, the input terminal of the fifth user-defined register 35 is connected to the JTAG test data input terminal JTAG _ tdi of the joint test action group, the output terminal of the fifth user-defined register 35 is connected to the input terminal of the second user-defined
When performing a scan test on the scan chain, in the case that there is no linear correlation between the scan register 21 and the first functional logic circuit 11 and there is no linear correlation between the scan register 21 and the second
in the SCAN chain shift mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a high level, and the
in the SCAN chain capture mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a low level, and whether to turn on the
In the embodiment of the present application, during the scan test, the signal of the built-in self-test mode (mbist _ mode) output by the fourth user-defined register 34 is 0, and the signal of the low-power mode (low _ power _ mode) output by the first user-defined register 31(UTDR reg1) is 0, which does not affect the output of the first functional logic 11. The fifth user defined register 35(UTDR reg5) is configured to output a scan mode (scan _ mode) signal of 1. The third user defined register 33(UTDR reg3) resets the value to 0 and selects the 0 terminal of the
In scan chain shift mode, the scan registers on the scan chain now become shift registers. Every clock beat, a new scan register is added to the scan chain to output (load) value.
When the E terminal and the preceding first functional logic circuit 11 need to be tested, the ATPG tool can input the scan register 21 with the test vector to make the value of the output (load) of the scan register 21 be 0, so that whether the clock gating unit is turned on or not is determined by the E terminal, and whether the value of the E terminal is correct or not is determined by whether the clock gating unit outputs the clock or not. When the clock gating unit needs to be turned on, the ATPG tool can make the value of the output (load) of the scan register 21 be 1, so that the first functional logic circuit 11 does not need to be derived to make the end E be 1, the vector efficiency is improved, the vector quantity is reduced, and the test time is shortened.
In the scan test process, two test phases are generally included: the method comprises a scan chain shift mode and a scan chain capture mode, wherein in the scan chain shift mode, each scan register on a scan chain can load a required value, and in the scan chain capture mode, the value output by each scan register is kept unchanged so as to test whether the output of a logic circuit is correct or not and test whether a connection between the logic circuits is disconnected or not. The scan chain shift mode and the scan chain capture mode may be alternated to complete the scan test. The value of scan register 21 output (load) refers to the value after completion of the scan chain shift pattern. I.e., the value at the Q terminal of scan register 21, is scanned for the last beat of the scan chain shift pattern. The number of clock beats sustained for a scan chain shift pattern may be greater than or equal to the number of scan registers in the scan chain, and the scan chain capture pattern may be maintained for greater than or equal to one beat.
In scan chain compression mode, there may also be an effect of linear dependency of scan register 21 and the register of first functional logic circuit 11 or the register of second
When the second
Since the power-on reset value of scan _ mode, mbist _ mode and low _ power _ mode is 0, the control of the clock gating unit by the E end in the normal functional mode of the chip is not influenced.
Optionally, when performing a Memory built-In Self Test (MBIST), the
At the time of MBIST testing, the memory may be turned off since such a clock gating cell of fig. 3 is not driven behind it. The scan _ mode is configured to be 0 and the mbist _ mode is configured to be 1, so that the clock gating unit can be turned off to reduce the power consumption of the register.
Referring to fig. 4, fig. 4 is a diagram illustrating another control circuit for controlling a clock gating unit according to an embodiment of the present disclosure. Fig. 4 is further optimized on the basis of fig. 2, the clock gating cell of fig. 4 being used to drive a second
The
the
Wherein, the input terminal of the sixth user-defined
Wherein, when performing scan test on the scan chain, in the case that there is no linear correlation between the scan register 21 and the first functional logic circuit 11 and there is no linear correlation between the scan register 21 and the second
in the SCAN chain shift mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a high level, and the
in the SCAN chain capture mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a low level, and whether to turn on the
The scheme of fig. 4 is applicable to a scenario where the clock gating cell is followed by a driving memory, a register, and a next level clock gating cell. The control circuit differs from the arrangement of fig. 3 in that the mbist _ mode signal, the test mode (test _ mode) signal and the scan _ mode signal are omitted from the
During scan test, a test _ mode is configured to be 1, and a mbist _ mode is configured to be 0. When the E terminal and the preceding first functional logic circuit 11 need to be tested, the ATPG tool can input the scan register 21 with the test vector to make the value of the output (load) of the scan register 21 be 0, so that whether the clock gating unit is turned on or not is determined by the E terminal, and whether the value of the E terminal is correct or not is determined by whether the clock gating unit outputs the clock or not. When the clock gating unit needs to be turned on, the ATPG tool can make the value of the output (load) of the scan register 21 be 1, so that the first functional logic circuit 11 does not need to be derived to make the end E be 1, the vector efficiency is improved, the vector quantity is reduced, and the test time is shortened.
When the second
Optionally, when the memory built-in self-test is performed, the
In performing memory built-in self-tests, the
Optionally, if the
Referring to fig. 5, fig. 5 is a diagram illustrating another control circuit for controlling a clock gating unit according to an embodiment of the present disclosure. Fig. 5 is further optimized on the basis of fig. 2, the clock gating cell of fig. 5 being used to drive a second
The
the
Wherein, the input terminal of the eighth user-defined register 38 is connected to the JTAG test data input terminal, the output terminal of the eighth user-defined register 38 is connected to the input terminal of the second user-defined
Wherein, when performing scan test on the scan chain, the test mode test _ mode signal is high level, and the
in the SCAN chain shift mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a high level, and the
in the SCAN chain capture mode of the SCAN test, the SCAN enable signal SCAN _ EN is at a low level, and whether to turn on the
The scheme of fig. 5 is applicable to the scenario of registers behind the clock gating cell and the next level of clock gating cell. The control circuit differs from the arrangement of fig. 4 in that the first control circuit replaces the test _ mode signal output from the seventh user defined
The scheme of fig. 5 is also applicable to the control of the clock gating cell of the first stage. The test mode test _ mode signal of the first-stage clock gating unit is configured as a global signal and cannot be controlled by a user-defined register, and only after the first-stage clock gating unit is opened, the following clock gating unit has a clock. The clock-gated test mode test _ mode signal following the first level of clock gating may be controlled by a user-defined register.
During scan test, a test _ mode is configured to be 1, and a mbist _ mode is configured to be 0. When the E terminal and the preceding first functional logic circuit 11 need to be tested, the ATPG tool can input the scan register 21 with the test vector to make the value of the output (load) of the scan register 21 be 0, so that whether the clock gating unit is turned on or not is determined by the E terminal, and whether the value of the E terminal is correct or not is determined by whether the clock gating unit outputs the clock or not. When the clock gating unit needs to be turned on, the ATPG tool can make the value of the output (load) of the scan register 21 be 1, so that the first functional logic circuit 11 does not need to be derived to make the end E be 1, the vector efficiency is improved, the vector quantity is reduced, and the test time is shortened.
When the second
Optionally, when performing the memory built-in self test, the test mode test _ mode signal is at a high level, and the
In performing memory built-in self-tests, the second memory 125 may be tested by the ATPG tool generating a memory test (ramserial) vector. The memory test vector requires several iterations of the scan chain shift pattern and the scan chain capture pattern to determine if a bit in the second memory 125 has a problem. During SCAN (SCAN) test, only one SCAN chain displacement mode and one SCAN chain capture mode are needed for testing.
Optionally, if the second memory 125 does not need to perform the memory built-in self-test, the
The clock gating cells in fig. 2-5 may be integrated clock gating or non-integrated clock gating. The clock gating units in fig. 2 to 5 may be clock gating units of rising edge valid clocks or clock gating units of falling edge valid clocks. The control circuits of fig. 2-5 may control one clock gating cell or multiple clock gating cells of the same type simultaneously. The control circuits in fig. 2-5 may be one level of clock gating cells or a cascade of multiple levels of clock gating cells.
The user defined registers in fig. 2 to 5 may be data registers of IEEE std 1500 or IEEE std 1149.1. The user-defined registers in fig. 2-5 may be controlled via chip input pins.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present disclosure. As shown in fig. 6, the chip 600 includes at least one logic function circuit 61, at least one
The chip in the embodiment of the application can be an SOC chip and can be applied to mobile terminals such as mobile phones.
Referring to fig. 7, fig. 7 is a flowchart illustrating a control method for controlling a clock gating unit according to an embodiment of the present disclosure. The method shown in fig. 7 is applied to any one of the control circuits in fig. 2 to 5, and comprises the following steps:
701, under the condition that the scanning register has linear correlation with the first functional logic circuit or the scanning register has linear correlation with the second functional logic circuit, configuring the level of the output end of the third user-defined register through the user-defined vector so that the multiplexer selects the second input end of the multiplexer as the input;
the first functional logic circuit or the second functional logic circuit is tested 702 by the incremental vector generated by the automatic test vector generation ATPG tool.
In the embodiment of the application, because the output of the scan register does not act on the test enabling end for controlling the clock gating unit, the linear correlation between the scan register and the first functional logic circuit or the second functional logic circuit is eliminated, the increment vector generated by the ATPG tool can test the fault point which is not detected in the first functional logic circuit or the second functional logic circuit due to the linear correlation, and the test coverage rate of the first functional logic circuit and the second functional logic circuit can be increased.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.
The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a read-only memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and the like.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash memory disks, read-only memory, random access memory, magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
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