Data processing method, data processing device, terminal device and storage medium

文档序号：1201540 发布日期：2020-09-01 浏览：16次中文

阅读说明：本技术 数据处理方法、数据处理装置、终端设备及存储介质 (Data processing method, data processing device, terminal device and storage medium ) 是由余豪路姚丽丽于 2020-04-23 设计创作，主要内容包括：本申请公开了一种数据处理方法、数据处理装置、终端设备及存储介质,用于集成电路版图的寄生参数处理。数据处理方法包括读取工艺表格、提取表格和标准表格,所述提取表格包括由第一寄生参数提取工具从所述集成电路版图提取的第一工艺参数和第一寄生参数,所述工艺表格包括第二工艺参数,所述标准表格包括由第二寄生参数提取工具提取的第三工艺参数和第二寄生参数确认所述第一工艺参数与所述第二工艺参数相同,确认所述第一工艺参数与所述第三工艺参数相同,输出所述第二寄生参数,计算对应的所述第一寄生参数与输出的所述第二寄生参数之间误差,输出所述误差。(The application discloses a data processing method, a data processing device, a terminal device and a storage medium, which are used for processing parasitic parameters of an integrated circuit layout. The data processing method comprises the steps of reading a process table, extracting the table and a standard table, wherein the extracted table comprises a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table comprises a second process parameter, the standard table comprises a third process parameter and a second parasitic parameter extracted by a second parasitic parameter extraction tool, the first process parameter is confirmed to be the same as the second process parameter, the first process parameter is confirmed to be the same as the third process parameter, the second parasitic parameter is output, an error between the corresponding first parasitic parameter and the output second parasitic parameter is calculated, and the error is output.)

1. A data processing method for parasitic parameter processing of an integrated circuit layout, comprising:

reading a process table, an extraction table and a standard table;

the extraction table comprises a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool;

the process table includes a second process parameter;

the standard table comprises a third process parameter and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

confirming that the first process parameter is the same as the second process parameter;

confirming that the first process parameter is the same as the third process parameter, and outputting the second parasitic parameter;

and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

2. The data processing method of claim 1, wherein the first process parameter comprises a first process corner and a first metal layer name;

the second process parameter comprises a second process corner and a second metal layer name;

the third process parameter includes a third process corner and a third metal layer name.

3. The data processing method of claim 1, wherein the extracted table further comprises a first extraction parameter extracted from the integrated circuit layout by the first parasitic parameter extraction tool;

the process table further comprises a second extraction parameter;

the criteria table further includes a third extraction parameter extracted by the second parasitic parameter extraction tool.

4. The data processing method of claim 3, wherein after confirming that the first process parameter is the same as the second process parameter, the data processing method further comprises: converting the corresponding first extraction parameters into corresponding second extraction parameters;

after confirming that the first process parameter is the same as the third process parameter, the data processing method further includes: confirming that the corresponding converted first extraction parameter is the same as the corresponding third extraction parameter, and outputting the corresponding second parasitic parameter.

5. The data processing method of claim 4, wherein after reading the process table, the extraction table, and the standard table, the data processing method further comprises: splitting the extraction table into a plurality of sub-extraction tables, and splitting the process table into a plurality of sub-process tables;

confirming that the first process parameter is the same as the second process parameter, and converting the corresponding first extraction parameter into the corresponding second extraction parameter, specifically comprising: confirming that the first process parameter of the sub-extraction table is the same as the second process parameter of the sub-process table, and converting the corresponding first extraction parameter of the corresponding sub-extraction table into the corresponding second extraction parameter of the corresponding sub-process table.

6. The data processing method according to claim 5, wherein splitting the extracted table into a plurality of sub-extracted tables and splitting the process table into a plurality of sub-process tables specifically comprises: and splitting the extraction table into a plurality of sub-extraction tables according to different first process parameters, and splitting the process table into a plurality of sub-process tables according to different second process parameters.

7. The data processing method of claim 5, wherein after splitting the extracted table into a plurality of sub-extracted tables and splitting the technical table into a plurality of sub-technical tables, the data processing method further comprises: splitting the standard table into a plurality of sub-standard tables;

confirming that the first process parameter is the same as the third process parameter, confirming that the corresponding converted first extraction parameter is the same as the corresponding third extraction parameter, and outputting the second parasitic parameter, specifically comprising: confirming that the first process parameter of the sub extraction table is the same as the third process parameter of the sub standard table, confirming that the corresponding converted first extraction parameter of the corresponding sub extraction table is the same as the corresponding third extraction parameter of the corresponding sub standard table, and outputting the second parasitic parameter.

8. The data processing method according to claim 7, wherein splitting the standard table into a plurality of sub-standard tables specifically comprises: and splitting the standard table into a plurality of sub-standard tables according to different third process parameters.

9. The data processing method according to any one of claims 3 to 8, wherein the first extraction parameter comprises a first line width and a first pitch;

the second extraction parameter comprises a second line width and a second distance;

the third extraction parameter includes a third line width and a third pitch.

10. The data processing method of claim 9,

the first line width and the first interval both reserve three decimal places, and the third line width and the third interval both reserve three decimal places.

11. The data processing method according to any one of claims 1 to 8,

the process table, the extraction table, and the standard table are in xls format or xlsx format.

12. The data processing method according to any one of claims 1 to 8, wherein the first parasitic parameter extraction tool is Quantus QRC;

and/or the second parasitic parameter extraction tool is Rapheal starRC.

13. A data processing method for parasitic parameter processing of an integrated circuit layout, comprising:

reading a process table, an extraction table and a standard table, wherein the extraction table comprises a first process corner, a first metal layer name, a first line width, a first spacing and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table comprises a second process corner, a second metal layer name, a second line width and a second spacing, and the standard table comprises a third process corner, a third metal layer name, a third line width, a third spacing and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

confirming that the first process corner is the same as the second process corner, the name of the first metal layer is the same as the name of the second metal layer, the corresponding first line width is converted into the corresponding second line width, and the corresponding first space is converted into the corresponding second space;

confirming that the first process corner is the same as the third process corner, the name of the first metal layer is the same as the name of the third metal layer, the corresponding converted first line width is the same as the corresponding third line width, the corresponding converted first spacing is the same as the corresponding third spacing, and the second parasitic parameter is output;

and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

14. The data processing method of claim 13, wherein after reading the process table, the extraction table, and the standard table, the data processing method further comprises: splitting the extraction table into a plurality of sub-extraction tables according to different first process corners, and splitting the process table into a plurality of sub-process tables according to different second metal layer names;

confirming that the first process corner is the same as the second process corner, confirming that the name of the first metal layer is the same as the name of the second metal layer, converting the corresponding first line width into the corresponding second line width, and converting the corresponding first space into the corresponding second space, specifically comprising: confirming that the first metal layer name of the sub extraction table is the same as the second metal layer name corresponding to the sub process table, confirming that the first process corner corresponding to the corresponding sub extraction table is the same as the second process corner corresponding to the sub process table, converting the corresponding first line width of the corresponding sub extraction table into the corresponding second line width of the corresponding sub process table, and converting the corresponding first pitch of the corresponding sub extraction table into the corresponding second pitch of the corresponding sub process table.

15. The data processing method according to claim 14, wherein after the extracted table is split into a plurality of sub-extracted tables according to different first process corners and the process table is split into a plurality of sub-process tables according to different second metal layer names, the data processing method further comprises: splitting the standard table into a plurality of sub-standard tables according to different names of the third metal layer;

confirming that the first process corner is the same as the third process corner, confirming that the first metal layer name is the same as the third metal layer name, confirming that the corresponding converted first line width is the same as the corresponding third line width, confirming that the corresponding converted first spacing is the same as the corresponding third spacing, and outputting the second parasitic parameter, specifically comprising: confirming that the first metal layer name of the sub extraction table is the same as the third metal layer name of the sub standard table, confirming that the first process corner corresponding to the corresponding sub extraction table is the same as the third process corner corresponding to the sub standard table, confirming that the corresponding converted first line width of the corresponding sub extraction table is the same as the corresponding third line width of the corresponding sub process table, confirming that the corresponding converted first pitch of the corresponding sub extraction table is the same as the corresponding third pitch of the corresponding sub process table, and outputting the second parasitic parameter.

16. A data processing apparatus for parasitic parameter processing of an integrated circuit layout, comprising:

a reading module configured to read a process table, an extraction table, and a standard table, the extraction table including a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table including a second process parameter, the standard table including a third process parameter and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

a parasitic parameter output module configured to confirm that the first process parameter is the same as the second process parameter, confirm that the first process parameter is the same as the third process parameter, and output the second parasitic parameter; and

an error calculation module configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

17. The data processing apparatus of claim 16, wherein the first process parameter comprises a first process corner and a first metal layer name, the second process parameter comprises a second process corner and a second metal layer name, and the third process parameter comprises a third process corner and a third metal layer name.

18. The data processing apparatus according to claim 16, wherein said extracted table further comprises a first extracted parameter extracted from said integrated circuit layout by said first parasitic parameter extraction tool;

the process table further comprises a second extraction parameter;

the criteria table further includes a third extraction parameter extracted by the second parasitic parameter extraction tool.

19. The data processing apparatus of claim 18, wherein the data processing apparatus further comprises:

a data conversion module configured to convert the corresponding first extraction parameter into the corresponding second extraction parameter.

20. The data processing apparatus of claim 19, wherein the data processing apparatus further comprises:

the first splitting module is configured to split the extraction table into a plurality of sub-extraction tables and split the process table into a plurality of sub-process tables.

21. The data processing apparatus according to claim 20, wherein the extraction table is split into the plurality of sub-extraction tables according to the different first process parameters, and the process table is split into the plurality of sub-process tables according to the different second process parameters.

22. The data processing apparatus of claim 20, wherein the data processing apparatus further comprises:

a second splitting module configured to split the standard table into a plurality of sub-standard tables.

23. The data processing apparatus according to claim 22, wherein the standard table is split into a plurality of the sub-standard tables according to different third process parameters.

24. The data processing apparatus according to any of claims 18 to 23, wherein the first extraction parameter comprises a first line width and a first pitch;

the second extraction parameter comprises a second line width and a second distance;

the third extraction parameter includes a third line width and a third pitch.

25. The data processing apparatus of claim 24, wherein the first linewidth and the first spacing each reserve three decimals, and wherein the third linewidth and the third spacing each reserve three decimals.

26. The data processing apparatus of any one of claims 16 to 23, wherein the process table, the extraction table, and the standard table are in xls format or xlsx format.

27. The data processing apparatus according to any of claims 16 to 23, wherein the first parasitic parameter extraction tool is Quantus QRC;

and/or the second parasitic parameter extraction tool is Rapheal starRC.

28. A data processing apparatus for parasitic parameter processing of an integrated circuit layout, comprising:

a reading module configured to read a process table, an extraction table, and a standard table, the extraction table including a first process corner, a first metal layer name, a first line width, a first spacing, and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table including a second process corner, a second metal layer name, a second line width, and a second spacing, the standard table including a third process corner, a third metal layer name, a third line width, a third spacing, and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

a data conversion module configured to confirm that the first process corner is the same as the second process corner, confirm that the first metal layer name is the same as the second metal layer name, convert the corresponding first line width into the corresponding second line width, and convert the corresponding first pitch into the corresponding second pitch;

a parasitic parameter output module configured to confirm that the first process corner is the same as the third process corner, confirm that the first metal layer name is the same as the third metal layer name, confirm that the corresponding converted first line width is the same as the corresponding third line width, confirm that the corresponding converted first pitch is the same as the corresponding third pitch, and output the second parasitic parameter;

an error calculation module configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

29. The data processing apparatus of claim 28, wherein the data processing apparatus further comprises:

the first splitting module is configured to split the extraction table into a plurality of sub-extraction tables according to different first process corners, and split the process table into a plurality of sub-process tables according to different second metal layer names.

30. The data processing apparatus of claim 29, wherein the data processing apparatus further comprises:

a second splitting module configured to split the standard table into a plurality of sub-standard tables according to different third metal layer names.

31. A terminal device comprising a processor and a memory for storing a computer program operable on the processor, wherein the processor is configured to carry out the steps of the data processing method according to any one of claims 1 to 15 when the computer program is run by the processor.

32. A storage medium having a computer program stored thereon, the computer program being executable by a processor to perform steps of implementing a data processing method according to any one of claims 1 to 15.

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a data processing method, a data processing apparatus, a terminal device, and a storage medium.

Background

In the extraction of the parasitic parameters of the integrated circuit layout, a Quantus QRC parasitic parameter extraction tool of Cadence company is usually adopted for extraction, and the extracted parasitic parameters are used for creating an accurate simulation model of the integrated circuit, so that the accuracy of the extracted parasitic parameters greatly influences the accuracy of the simulation model.

Disclosure of Invention

In view of this, embodiments of the present application provide a data processing method, a data processing apparatus, a terminal device, and a storage medium to solve at least one problem in the background art.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

the embodiment of the application provides a data processing method, which is used for processing parasitic parameters of an integrated circuit layout and comprises the following steps:

reading a process table, an extraction table and a standard table;

the extraction table comprises a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool;

the process table includes a second process parameter;

the standard table comprises a third process parameter and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

confirming that the first process parameter is the same as the second process parameter;

confirming that the first process parameter is the same as the third process parameter, and outputting the second parasitic parameter;

and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

Further, the first process parameter comprises a first process corner and a first metal layer name;

the second process parameter comprises a second process corner and a second metal layer name;

the third process parameter includes a third process corner and a third metal layer name.

Further, the extracted table further comprises a first extracted parameter extracted from the integrated circuit layout by the first parasitic parameter extraction tool;

the process table further comprises a second extraction parameter;

the criteria table further includes a third extraction parameter extracted by the second parasitic parameter extraction tool.

Further, after confirming that the first process parameter is the same as the second process parameter, the data processing method further includes: converting the corresponding first extraction parameters into corresponding second extraction parameters;

Further, after reading the process table, the extraction table and the standard table, the data processing method further includes: splitting the extraction table into a plurality of sub-extraction tables, and splitting the process table into a plurality of sub-process tables;

Further, splitting the extraction table into a plurality of sub-extraction tables, and splitting the process table into a plurality of sub-process tables specifically includes: and splitting the extraction table into a plurality of sub-extraction tables according to different first process parameters, and splitting the process table into a plurality of sub-process tables according to different second process parameters.

Further, after the extracting table is split into a plurality of sub-extracting tables and the process table is split into a plurality of sub-process tables, the data processing method further includes: splitting the standard table into a plurality of sub-standard tables;

Further, splitting the standard table into a plurality of sub-standard tables specifically includes: and splitting the standard table into a plurality of sub-standard tables according to different third process parameters.

Further, the first extraction parameter includes a first line width and a first pitch;

the second extraction parameter comprises a second line width and a second distance;

the third extraction parameter includes a third line width and a third pitch.

Further, the first line width and the first interval both reserve three decimals, and the third line width and the third interval both reserve three decimals.

Further, the process table, the extraction table, and the standard table are all in xls format or xlsx format.

Further, the first parasitic parameter extraction tool is Quantus QRC;

and/or the second parasitic parameter extraction tool is Rapheal starRC.

The embodiment of the present application further provides another data processing method, which is used for processing parasitic parameters of an integrated circuit layout, and includes:

and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

Further, after the steps of reading the process table, the extraction table, and the standard table, the data processing method further includes: splitting the extraction table into a plurality of sub-extraction tables according to different first process corners, and splitting the process table into a plurality of sub-process tables according to different second metal layer names;

confirming that the first process corner is the same as the second process corner, confirming that the first metal layer name is the same as the second metal layer name, converting the corresponding first line width into the corresponding second line width, and converting the corresponding first space into the corresponding second space, specifically comprising: confirming that the first metal layer name of the sub extraction table is the same as the second metal layer name corresponding to the sub process table, confirming that the first process corner corresponding to the corresponding sub extraction table is the same as the second process corner corresponding to the sub process table, converting the first line width of the corresponding sub extraction table into the corresponding second line width of the corresponding sub process table, and converting the corresponding first pitch of the corresponding sub extraction table into the corresponding second pitch of the corresponding sub process table.

Further, after the extracted table is split into a plurality of sub-extracted tables according to the different first process corners and the process table is split into a plurality of sub-process tables according to the different second metal layer names, the data processing method further includes: splitting the standard table into a plurality of sub-standard tables according to different names of the third metal layer;

An embodiment of the present application further provides a data processing apparatus, configured to process parasitic parameters of an integrated circuit layout, including:

an error calculation module configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

Further, the first process parameter includes a first process corner and a first metal layer name, the second process parameter includes a second process corner and a second metal layer name, and the third process parameter includes a third process corner and a third metal layer name.

Further, the extracted table further comprises a first extracted parameter extracted from the integrated circuit layout by the first parasitic parameter extraction tool;

the process table further comprises a second extraction parameter;

the criteria table further includes a third extraction parameter extracted by the second parasitic parameter extraction tool.

Further, the data processing apparatus further includes:

a data conversion module configured to convert the corresponding first extraction parameter into the corresponding second extraction parameter.

Further, the data processing apparatus further includes:

the first splitting module is configured to split the extraction table into a plurality of sub-extraction tables and split the process table into a plurality of sub-process tables.

Further, the extraction table is split into a plurality of sub-extraction tables according to different first process parameters, and the process table is split into a plurality of sub-process tables according to different second process parameters.

Further, the data processing apparatus further includes:

a second splitting module configured to split the standard table into a plurality of sub-standard tables.

Further, the standard table is divided into a plurality of sub-standard tables according to the different third process parameters.

Further, the first extraction parameter includes a first line width and a first pitch;

the second extraction parameter comprises a second line width and a second distance;

the third extraction parameter includes a third line width and a third pitch.

Further, the first line width and the first interval both reserve three decimals, and the third line width and the third interval both reserve three decimals.

Further, the process table, the extraction table, and the standard table are all in xls format or xlsx format.

Further, the first parasitic parameter extraction tool is Quantus QRC;

and/or the second parasitic parameter extraction tool is Rapheal starRC.

The embodiment of the present application further provides another data processing apparatus, configured to process parasitic parameters of an integrated circuit layout, including:

an error calculation module configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

Further, the data processing apparatus further includes:

a second splitting module configured to split the standard table into a plurality of sub-standard tables according to different third metal layer names.

Another aspect of the embodiments of the present application provides a terminal device, including a processor and a memory, where the memory is used for storing a computer program that can be executed on the processor, and when the processor is used for executing the computer program, the method implements the steps of any one of the data processing methods described above.

In another aspect, the embodiment of the present application provides a storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the steps of the data processing method described in any one of the above.

According to the data processing method provided by the embodiment of the application, the error calculation is carried out on the first parasitic parameter and the second parasitic parameter in the extraction table, so that whether the first parasitic parameter exceeds the error allowable range is judged, the accuracy of the first parasitic parameter extracted by the first parasitic parameter extraction tool is verified, and therefore the first parasitic parameter extraction error is avoided through the added quality verification program, and the influence of the overlarge error of the first parasitic parameter on the accuracy of the simulation model is avoided. In addition, the process table is read through the program, the extraction table and the standard table are compared, the second parasitic parameter is selected and output, and the error between the corresponding first parasitic parameter and the output second parasitic parameter is calculated and output, so that the efficiency is improved, the working hours are saved, the manual searching of the output second parasitic parameter and the error rate caused by calculation error can be avoided. The data processing apparatus, the terminal device, and the storage medium provided in the embodiments of the present application implement the steps of the data processing method, and have the same advantageous effects as the data processing method provided in the embodiments of the present application.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

Fig. 1 is a flowchart of a data processing method according to an embodiment of the present application;

fig. 2 is a schematic diagram of an extracted table obtained by QRC according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a process table provided in an embodiment of the present application;

FIG. 4 is a diagram illustrating a standard table obtained by StarRC according to an embodiment of the present disclosure;

FIG. 5 is a flow chart of another data processing method provided by the embodiments of the present application;

fig. 6 is a block diagram of a data processing apparatus according to an embodiment of the present application;

FIG. 7 is a block diagram of another data processing apparatus provided in an embodiment of the present application;

fig. 8 is a block diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions. And should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Referring to fig. 1, an aspect of the present application provides a data processing method for processing parasitic parameters of an integrated circuit layout, where the data processing method includes:

s100: reading a process table, an extraction table and a standard table.

The extracted table includes a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool. The process table includes a second process parameter. The criteria table includes the third process parameter and the second parasitic parameter extracted by the second parasitic parameter extraction tool. As will be appreciated by those skilled in the art, an integrated circuit layout is a planar geometric description of the physical conditions of a real integrated circuit. The integrated circuit layout is a graph containing relevant physical information of the integrated circuit, such as device types, device sizes, relative positions between devices, connection relations between devices, and the like, and the graphs are formed by graphs positioned on different drawing layers. The metal layer, i.e. the metal interconnection layer, is used as a signal interconnection line, a power supply line or a ground line, etc. Process Corner (Corner for short) refers to the range of device performance. And the designer controls the expected parameter change according to the range limited by the process angle, and discards the chips beyond the range limited by the process angle, so that the design difficulty of the layout is reduced. Typical Corner refers to the corresponding process angle when the drive current is averaged. Integrated circuit layouts typically include multiple metal layers thereon. In the embodiment of the present application, the line width refers to the width of the metal layer. Pitch refers to the distance between different metal layers. Layout Parasitic parameter Extraction (LEP) refers to extracting Parasitic parameters such as Parasitic capacitance and Parasitic resistance generated by internal interconnection on a Layout by a Parasitic parameter Extraction tool, and further obtaining real time sequence information after the Layout is realized. The parasitic parameters such as the parasitic capacitance and the parasitic resistance are not set by the designer, but are generated due to the physical properties of the structure and the material.

That is, under the condition that the production process is determined to be completed, a corresponding process table is generated, and the second process parameter is included in the process table. And generating a corresponding integrated circuit layout under the determined production process, wherein the first parasitic parameter extraction tool extracts a first parasitic parameter and a first process parameter from the integrated circuit layout and outputs the first parasitic parameter and the first process parameter to an extraction table because of process deviation between actual production and design, the first parasitic parameter is generated correspondingly to the first process parameter, and the first parasitic parameter corresponds to each first process parameter. In order to facilitate checking of the deviation in the production process, the third process parameters and the second parasitic parameters extracted from the standard integrated circuit layout by the second parasitic parameter extraction tool are output to the standard table, that is, the second parasitic parameters correspond to each third process parameter. It will be appreciated that a standard integrated circuit layout refers to an integrated circuit layout generated using process conditions that are infinitely close to those in the process table.

It should be noted that the integrated circuit layout for extracting the first parasitic parameter by the first parasitic parameter extraction tool is the actual integrated circuit layout. The standard integrated circuit layout for extracting the second parasitic parameter by the second parasitic parameter extraction tool is the integrated circuit layout for reference. The standard integrated circuit layout and the actual integrated circuit board diagram adopt the same process. The first process parameter, the second process parameter and the third process parameter are names corresponding to the metal layer structure.

In one embodiment, the first process parameter includes a first process corner and a first metal layer name. The second process parameter includes a second process corner and a second metal layer name. The third process parameter includes a third process corner and a third metal layer name.

S200: confirming that the first process parameter is the same as the second process parameter.

S300: and confirming that the first process parameter is the same as the third process parameter, and outputting the second parasitic parameter.

As can be seen from the above, the first process parameters in the extracted table, the second process parameters in the process table, and the third process parameters in the standard table are determined, and each first process parameter corresponds to one first parasitic parameter, and each third process parameter corresponds to one second process parameter, so that the second parasitic parameter corresponding to the first parasitic parameter is found in the standard table.

In a specific embodiment, the first process corner is the same as the second process corner, the first metal layer name is the same as the second metal layer name, and the first process corner is the same as the third process corner, and the first metal layer name is the same as the third metal layer name.

S400: and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

According to the data processing method provided by the embodiment of the application, the first parasitic parameter and the second parasitic parameter in the extraction table are subjected to error calculation to judge whether the first parasitic parameter exceeds an error allowable range, so that the accuracy of the first parasitic parameter extracted by the first parasitic parameter extraction tool is verified, and thus, the first parasitic parameter extraction error is avoided through an added quality verification program, and the influence of the overlarge error of the first parasitic parameter on the accuracy of the simulation model is avoided. In addition, the process table is read through the program, the extraction table and the standard table are compared, the second parasitic parameter is selected and output, and the error between the corresponding first parasitic parameter and the output second parasitic parameter is calculated and output, so that the efficiency is improved, the working hours are saved, the manual searching of the output second parasitic parameter and the error rate caused by calculation error can be avoided.

It is understood that the error between the first parasitic parameter and the output second parasitic parameter means that the difference between the first parasitic parameter and the output second parasitic parameter is larger than the output second parasitic parameter.

In an embodiment, extracting the table further comprises extracting a first extraction parameter from the integrated circuit layout by a first parasitic parameter extraction tool. The process table also includes a second extraction parameter. The criteria table further includes a third extraction parameter extracted by the second parasitic parameter extraction tool. The first extraction parameter, the second extraction parameter and the third extraction parameter are data of corresponding metal layer structures.

In one embodiment, S200: after confirming that the first process parameter is the same as the second process parameter, the data processing method further includes S500: converting the corresponding first extraction parameters into corresponding second extraction parameters;

s300: after confirming that the first process parameter is the same as the third process parameter, the data processing method further includes S600: confirming that the corresponding converted first extraction parameter is the same as the corresponding third extraction parameter, and outputting the corresponding second parasitic parameter.

Due to process deviation, the first extraction parameter is different from the second extraction parameter and the third extraction parameter, and since the third provided parameter is extracted data of the standard integrated circuit layout, the second extraction parameter is infinitely close to the third extraction parameter, the corresponding first extraction parameter is converted into the corresponding second extraction parameter, and then the step S600 is performed: confirming that the corresponding converted first extraction parameters are the same as the corresponding third extraction parameters, and outputting the corresponding second parasitic parameters, so that the accuracy of the output corresponding second parasitic parameters is improved.

In one embodiment, S100: after reading the process table, extracting the table and the standard table, the data processing method further includes S700: splitting the extraction table into a plurality of sub-extraction tables, and splitting the process table into a plurality of sub-process tables;

Therefore, multithreading processing is realized through the sub-extraction table and the sub-process table, and the data processing speed is improved.

In an embodiment, splitting the extraction table into a plurality of sub-extraction tables, and splitting the process table into a plurality of sub-process tables specifically includes: and splitting the extraction table into a plurality of sub-extraction tables according to different first process parameters, and splitting the process table into a plurality of sub-process tables according to different second process parameters.

In a specific embodiment, the extraction table is divided into a plurality of sub-extraction tables according to different first process corners, and the process table is divided into a plurality of sub-process tables according to different second metal layer names. In another embodiment, the extraction table is divided into a plurality of sub-extraction tables according to different first metal layer names, and the process table is divided into a plurality of sub-process tables according to different second metal layer names. In yet another embodiment, the extraction table is split into a plurality of sub-extraction tables according to different first process angles, and the process table is split into a plurality of sub-process tables according to different second process angles.

In one embodiment, S700: splitting the extraction table into a plurality of sub-extraction tables, and after splitting the process table into a plurality of sub-process tables, the data processing method further includes S800: splitting the standard table into a plurality of sub-standard tables;

Therefore, multithreading processing is realized through the sub-standard table, and the data processing speed is improved.

In an embodiment, splitting the standard table into a plurality of sub-standard tables specifically includes: and splitting the standard table into a plurality of sub-standard tables according to different third process parameters.

In one embodiment, the standard table is split into a plurality of sub-standard tables according to different third metal layer names. In another embodiment, the standard table is split into a plurality of sub-standard tables according to different third process corners.

In an embodiment, the first extraction parameter includes a first line width and a first pitch. The second extraction parameter includes a second line width and a second pitch. The third extraction parameter includes a third line width and a third pitch.

In one embodiment, the first line width and the first spacing each retain three decimal places, and the third line width and the third spacing each retain three decimal places. Therefore, judgment errors caused by inconsistency of the decimal places of the first line width, the third line width, the first distance and the third distance are avoided.

Because the extraction speed of QRC is higher than that of starRC, the QRC is adopted to extract parasitic parameters, so that the production efficiency is greatly improved in industrial production. In addition, QA (quality assessment) is carried out on the first parasitic parameter extracted by QRC to ensure the accuracy of the first parasitic parameter extraction. In the embodiment of the application, the corresponding second parasitic parameter is searched and output in the standard table generated by the starRC through a program, the error between the first parasitic parameter extracted by the QRC and the output second parasitic parameter is calculated, and if the error between the first parasitic parameter extracted by the corresponding QRC and the output second parasitic parameter is less than or equal to 10%, the first parasitic parameter extracted by the QRC is within the allowable error range, and no error is extracted.

In some embodiments, the first parasitic parameter extraction tool may also be QuickCap, Calibre xACT3D, fastCAP, or CapEXT, among others.

In one embodiment, the process table, the extraction table, and the standard table are in xls format or xlsx format. Because the xls format or the xlsx format is easy to read and has high compatibility, in addition, the tools such as QRC, starRC and the like can directly generate the xls format or the xlsx format, and thus, the operation processing of the unified data format is convenient.

Referring to fig. 5, another data processing method for parasitic parameter processing of an integrated circuit layout is provided in the embodiments of the present application. The data processing method comprises the following steps:

s01: reading a process table, extracting a table and a standard table, wherein the extracted table comprises a first process corner, a first metal layer name, a first line width, a first spacing and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table comprises a second process corner, a second metal layer name, a second line width and a second spacing, and the standard table comprises a third process corner, a third metal layer name, a third line width, a third spacing and a second parasitic parameter extracted by a second parasitic parameter extraction tool.

S02: and confirming that the first process corner is the same as the second process corner, the name of the first metal layer is the same as the name of the second metal layer, the corresponding first line width is converted into the corresponding second line width, and the corresponding first space is converted into the corresponding second space.

And comparing the first process corner with the second process corner, and comparing the first metal layer name with the second metal layer name, confirming that the first process corner is the same as the second process corner, confirming that the first metal layer name is the same as the second metal layer name, converting the corresponding first line width into the corresponding second line width, and converting the corresponding first interval into the corresponding second interval.

As can be seen from the above, the first process corner and the second process corner are the same, and the name of the first metal layer is the same as that of the second metal layer, the corresponding first line width may be different from the corresponding second line width, and the corresponding first spacing may be different from the corresponding second spacing, however, the corresponding third line width may be the same as the corresponding second line width, and the corresponding third spacing may be the same as the corresponding second spacing.

It should be noted that, the first process corner and the second process corner may be determined to be the same, and then the name of the first metal layer and the name of the second metal layer may be determined to be the same; or the first metal layer name and the second metal layer name are confirmed to be the same, and then the first process corner and the second process corner are confirmed to be the same. The corresponding first line width may be converted into the corresponding second line width, and then the corresponding first interval may be converted into the corresponding second interval; or converting the corresponding first interval into the corresponding second interval, and then converting the corresponding first line width into the corresponding second line width; the corresponding first pitch may be converted into the corresponding second pitch, and the corresponding first line width may be converted into the second line width.

To better illustrate the embodiments of the present application, fig. 2 to 4 show specific process tables, extraction tables and standard tables, which are specifically illustrated below:

the process table (see fig. 3) is a table for recording a second process parameter corresponding to the integrated circuit layout design. Fig. 3 shows a process table under the layout design process condition, and in fig. 3, TM refers to the name of the second metal layer. The Rmin process corner refers to a second process corner corresponding to the minimum parasitic resistance. The Rmax process corner refers to the second process corner corresponding to the maximum parasitic resistance. The Cmin process corner refers to a second process corner corresponding to the minimum parasitic capacitance. Cmax, i.e., the Cmax process corner, refers to the second process corner corresponding to the maximum parasitic capacitance. Wherein, Max _ width refers to the maximum second line width corresponding to Cmax and Rmin. Min spacing refers to the minimum second pitch corresponding to Cmax and Rmin. That is, Cmax and Rmin correspond to the same maximum second line width and minimum second pitch. Min _ width refers to the minimum second line width corresponding to Rmax and Cmin. Max _ spacing refers to the maximum second pitch corresponding to Cmin and Rmax. That is, Cmin and Rmax correspond to the same minimum second line width and maximum second pitch. Width refers to the average second line Width corresponding to Typical Corner. Spacing refers to the average second Spacing for a Typical Corner.

The extraction table (see fig. 2) refers to a table output by the first parasitic parameter extraction tool after extracting parasitic parameters from the integrated circuit layout. Fig. 2 illustrates an extracted table, the integrated circuit layout being made using the process parameters in the process table of fig. 3, in fig. 2, the header qrtechfile _ ALL _ type _ sq _ QAreport (c section) refers to the QA report of which the table is a QRC table. QA, Quality assessment, refers to Quality testing. The metal name is the first metal layer name. P2(above sub) refers to the name of the first metal layer located on the substrate. (M1 above) P2(above sub) refers to the first metal layer located on P2(above sub). Width refers to the first line Width. Spacing refers to the first pitch. QRC value refers to the value of the first parasitic parameter extracted by QRC. The Star RC value refers to the value of the second parasitic capacitance output in step S03. That is, step S03 can be output to a set position in the extraction table (fig. 3), which facilitates not only searching and comparing the corresponding first parasitic capacitance and second parasitic capacitance, but also implementing step S04.

The standard table (see fig. 4) is a table output by the second parasitic parameter extraction tool after extracting parasitic parameters on the integrated circuit layout, and the parasitic parameters and related data obtained by the second parasitic parameter extraction tool are used as standard data. That is, the first parasitic parameter extraction tool is used for extracting parasitic parameters on different integrated circuit layouts for multiple times, and data obtained by the second parasitic parameter extraction tool is repeatedly used as a standard table for checking the accuracy of the data extracted by the first parasitic parameter. In FIG. 4, the header Generic Structure Name is arr _ btwn _ gps, which is the Generic Structure Name, and the actual Structure Name is the actual Structure Name, where A _ PSUBAM1AM2 is the actual Structure Name named by the designer. Width means the third line Width. Spacing refers to the third pitch. C toal refers to the total capacitance.

It is to be understood that the nomenclature and nomenclature references in fig. 2-4 can be referred to by different nomenclature, and the nomenclature, data in fig. 2-4 are used merely for explanation and understanding in the embodiments of the present application, and are not limiting on the present application.

It should be noted that, in the embodiment of the present application, the name of the first metal layer, the name of the second metal layer, and the name of the third metal layer are used to refer to corresponding metal layer structures in the integrated circuit layout. The first metal layer name, the second metal layer name, the third metal layer name, the first process corner, the second process corner, and the third process corner in the present application do not refer to the structure itself, but only refer to the name. The first line width, the second line width, the third line width, the first distance, the second distance and the third distance are all data. Wherein the first line width and the first space may be null values, that is, the first line width and the first space may be unknown data or data to be added later; the first line width and the first spacing may also be zero or a specific value; the second line width, the third line width, the second distance and the third distance are specific numerical values.

Referring to fig. 2-4, in one embodiment, the first parasitic parameter extraction tool is Quantus QRC (hereinafter, QRC) of Cadence, and the second parasitic parameter extraction tool is Rapheal starRC (hereinafter, starRC) of Synopsys. An extraction table is generated by extracting the first process corner, the first metal layer name, the first line width and the first parasitic parameter from the integrated circuit layout by QRC (see fig. 2). The process table (see fig. 3) includes a second process corner, a second metal layer name, a second line width, and a second pitch. And extracting a third process corner, a third metal layer name, a third line width, a third distance and a second parasitic parameter from the standard integrated circuit layout through the starRC to generate a standard table (see figure 4), and reading the process table, the extraction table and the standard table after the three tables are obtained.

Illustratively, a first process corner and a first metal layer name in the extracted table of QRC (see fig. 2) are compared with a second process corner and a second metal layer name in the extracted table of QRC (see fig. 3), the same first process corner and second process corner, first metal layer name and second metal layer name in the extracted table of QRC and the process table are found, and then, the corresponding first line width, second line width, first spacing and second spacing are found through the same first process corner and second process corner, first metal layer name and second metal layer name, wherein the corresponding first line width is converted into the corresponding second line width, and the corresponding first spacing is converted into the corresponding second spacing.

S03: confirming that the first process corner is the same as the third process corner, confirming that the name of the first metal layer is the same as the name of the third metal layer, confirming that the corresponding converted first line width is the same as the corresponding third line width, confirming that the corresponding converted first spacing is the same as the corresponding third spacing, and outputting the second parasitic parameter.

Comparing the first process corner with the third process corner, the first metal layer name with the third metal layer name, confirming that the first process corner is the same as the third process corner, confirming that the first metal layer name is the same as the third metal layer name, comparing a converted first line width corresponding to the first process corner and the first metal layer name, a third process corner same as the first process corner and the first metal layer name and a third line width corresponding to the third metal layer name, and confirming that the corresponding converted first line width is the same as the third line width; and comparing the converted first pitch corresponding to the first process corner and the first metal layer name, and a third process corner and a third pitch corresponding to a third metal layer name, which are the same as the first process corner and the first metal layer name, to confirm that the corresponding converted first pitch and third pitch are the same, and thus, outputting second parasitic parameters corresponding to the third metal layer name, the third process corner, the third pitch, and the third line width.

It should be noted that, the first process corner and the third process corner may be determined to be the same, and then the first metal layer name and the third metal layer name may be determined to be the same; the name of the first metal layer and the name of the third metal layer can be confirmed to be the same, and then the name of the first process corner and the name of the third process corner are confirmed to be the same. The corresponding converted first line width and the corresponding third line width may be determined first, and then the corresponding converted first interval and the corresponding third interval may be determined; or, the corresponding converted first pitch and the corresponding third pitch may be determined to be the same, and then the corresponding converted first line width and the corresponding third line width may be determined to be the same.

Illustratively, the first process corner and the first metal layer name in the extracted table of QRC (see fig. 2) are compared with the third process corner and the third metal layer name in the standard table (see fig. 3), the same first process corner and third process corner, first metal layer name and third metal layer name in the extracted table of QRC and the standard table are found, then, finding out the corresponding converted first line width and third line width through the same first process corner and third process corner, the first metal layer name and the third metal layer name, and comparing the corresponding converted first line width with the corresponding converted third line width, confirming that the corresponding converted first line width is the same as the corresponding converted third line width, comparing the corresponding converted first distance with the corresponding converted third distance, confirming that the corresponding converted first distance is the same as the corresponding converted third distance, and outputting a corresponding second parasitic parameter.

S04: and calculating an error between the corresponding first parasitic parameter and the output second parasitic parameter, and outputting the error.

After the first step, error calculation is carried out on the first parasitic parameters corresponding to the first metal layer name, the first process angle, the first distance and the first line width and the output second parasitic parameters, and errors between the first parasitic parameters and the output second parasitic parameters are output.

Illustratively, the error between the corresponding first parasitic parameter in the extracted table of QRC (see fig. 2) and the corresponding second parasitic parameter in the standard table of starRC (see fig. 3) is calculated and output.

In one embodiment, after the steps of reading the process table, the extraction table, and the standard table, the data processing method further includes: s05, splitting the extraction table into a plurality of sub-extraction tables according to different first process corners, and splitting the process table into a plurality of sub-process tables according to different second metal layer names;

s02, confirming that the first process corner is the same as the second process corner, confirming that the first metal layer name is the same as the second metal layer name, converting the corresponding first line width into the corresponding second line width, and converting the corresponding first pitch into the corresponding second pitch, specifically comprising: confirming that the first metal layer name in the sub-extraction table is the same as the second metal layer name corresponding to the sub-process table, confirming that the first process corner corresponding to the corresponding sub-extraction table is the same as the second process corner in the corresponding sub-process table, converting the first line width in the corresponding sub-extraction table into the second line width in the corresponding sub-process table, and converting the first pitch in the corresponding sub-extraction table into the second pitch in the corresponding sub-process table.

Because different first metal layer names and second metal layer names may correspond to the same first line width and second line width, first spacing and second spacing, the same first metal layer name and second metal layer name are confirmed in the program running process, and thus, the situation that the wrong first line width and second line width, first spacing and second spacing are found and the output wrong second parasitic capacitance is caused is avoided. In the embodiment of the application, the extraction table is split into a plurality of sub-extraction tables according to different first process corners, so that the whole extraction table is split into the sub-extraction tables to heap the data. And splitting the process table into a plurality of sub-process tables according to different second metal layer names, so that the whole process table is split into the sub-process tables to stack the data. The corresponding sub-process table is confirmed by comparing and matching the same first metal layer name and the same second metal layer name, and the same first process corner and the same second process corner are confirmed in the corresponding sub-process table, so that the data are further conveniently searched, the efficiency is improved, and the search error is further avoided.

In an embodiment, after the step of splitting the extracted table into a plurality of sub-extracted tables according to different first process corners and splitting the process table into a plurality of sub-process tables according to different second metal layer names S05, the data processing method further includes: and S06, splitting the standard table into a plurality of sub-standard tables according to different names of the third metal layer.

S03, confirming that the first process corner is the same as the third process corner, confirming that the first metal layer name is the same as the third metal layer name, confirming that the corresponding converted first line width is the same as the corresponding third line width, confirming that the corresponding converted first pitch is the same as the corresponding third pitch, and outputting the second parasitic parameter specifically includes: confirming that the first metal layer name of the sub extraction table is the same as the third metal layer name of the sub standard table, confirming that the first process corner corresponding to the corresponding sub extraction table is the same as the third process corner in the corresponding sub standard table, confirming that the converted first line width corresponding to the corresponding sub extraction table is the same as the corresponding third line width of the corresponding sub process table, confirming that the converted first pitch of the corresponding sub extraction table is the same as the corresponding third pitch of the corresponding sub process table, and outputting the second parasitic parameter.

Since different first metal layer names and third metal layer names may correspond to the same converted first line width and third line width, and the same converted first interval and third interval, the same first metal layer name and third metal layer name need to be confirmed in the program running process, so that the wrong converted first line width and third line width, and the converted first interval and third interval are avoided being found. In the embodiment of the application, the extraction table is split into a plurality of sub-extraction tables according to different first process corners, so that the whole extraction table is split into the sub-extraction tables to heap the data. And splitting the standard table into a plurality of sub-standard tables according to different third metal layer names, so that the whole standard table is split into the sub-standard tables to heap the data. The corresponding sub-standard table is confirmed by comparing and matching the same first metal layer name and the same third metal layer name, and the same first process corner and the same third process corner are confirmed in the corresponding sub-standard table, so that the data are further conveniently searched, the efficiency is improved, and the search error is further avoided.

Referring to fig. 6, another aspect of the present invention provides a data processing apparatus 1 for processing parasitic parameters of an integrated circuit layout. The data processing device comprises a reading module 11, a parasitic parameter output module 12 and an error calculation module 13.

The reading module 11 is configured to read a process table, an extraction table and a standard table, the extraction table including a first process parameter and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool, the process table including a second process parameter, the standard table including a third process parameter and a second parasitic parameter extracted by a second parasitic parameter extraction tool;

the parasitic parameter output module 12 is configured to confirm that the first process parameter is the same as the second process parameter, confirm that the first process parameter is the same as the third process parameter, and output the second parasitic parameter;

the error calculation module 13 is configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

In an embodiment, the first process parameter includes a first process corner and a first metal layer name, the second process parameter includes a second process corner and a second metal layer name, and the third process parameter includes a third process corner and a third metal layer name.

In an embodiment, extracting the table further comprises extracting a first extraction parameter from the integrated circuit layout by the first parasitic parameter extraction tool. The process table also includes a second extraction parameter. The criteria table includes a third extraction parameter extracted by the second parasitic parameter extraction tool.

In an embodiment, the data processing apparatus further comprises a data conversion module configured to convert the corresponding first extraction parameter into the corresponding second extraction parameter.

In an embodiment, the data processing apparatus further includes a first splitting module configured to split the extraction table into a plurality of sub-extraction tables and split the process table into a plurality of sub-process tables.

In an embodiment, the extraction table is divided into a plurality of sub-extraction tables according to different first process parameters, and the process table is divided into a plurality of sub-process tables according to different second process parameters.

In an embodiment, the data processing apparatus further comprises a second splitting module configured to split the standard table into a plurality of sub-standard tables.

In an embodiment, the standard table is split into a plurality of sub-standard tables according to different third process parameters.

In one embodiment, the first line width and the first spacing each retain three decimal places, and the third line width and the third spacing each retain three decimal places.

In one embodiment, the process table, the extraction table, and the standard table are in xls format or xlsx format.

In one embodiment, the first parasitic parameter extraction tool is Quantus QRC. And/or the second parasitic parameter extraction tool is Rapheal starRC.

Referring to fig. 7, another data processing apparatus 100 for parasitic parameter processing of an integrated circuit layout is provided in an embodiment of the present application. The data processing device comprises a reading module 10, a data conversion module 20, a parasitic parameter output module 30 and an error calculation module 40.

The reading module 10 is configured to read the process table, the extraction table, and the standard table. The extracted table includes a first process corner, a first metal layer name, a first line width, a first pitch, and a first parasitic parameter extracted from the integrated circuit layout by a first parasitic parameter extraction tool. The process table includes a second process corner, a second metal layer name, a second line width, and a second spacing. The standard table includes a third process corner, a third metal layer name, a third line width, a third pitch, and a second parasitic parameter extracted by the second parasitic parameter extraction tool.

The data conversion module 20 is configured to determine that the first process corner is the same as the second process corner, and that the first metal layer name is the same as the second metal layer name, and that the corresponding first line width is converted into a corresponding second line width, and that the corresponding first pitch is converted into a corresponding second pitch.

The parasitic parameter output module 30 is configured to confirm that the first process corner is the same as the third process corner, confirm that the first metal layer name is the same as the third metal layer name, confirm that the corresponding converted first line width is the same as the corresponding third line width, confirm that the corresponding converted first pitch is the same as the corresponding third pitch, and output the second parasitic parameter.

The error calculation module 40 is configured to calculate an error between the corresponding first parasitic parameter and the output second parasitic parameter, and output the error.

In an embodiment, the data processing apparatus further comprises a first splitting module. The first splitting module is configured to split the extraction table into a plurality of sub-extraction tables according to different first process angles, and split the process table into a plurality of sub-process tables according to different second process angles.

In an embodiment, the data processing apparatus further comprises a second splitting module. The second splitting module is configured to split the standard table into a plurality of sub-standard tables according to different third metal layer names.

With regard to the data processing apparatus in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

Referring to fig. 8, another embodiment of the present application provides a terminal device 1000, which includes a processor 1001 and a memory 1002 for storing a computer program capable of running on the processor 1001, where the processor 1001 is configured to implement the steps of the data processing method in any one of the above embodiments when running the computer program.

Regarding the terminal device 1000 in the foregoing embodiment, when the processor 1001 is configured to run a computer program, the steps of the data processing method in any one of the foregoing embodiments are implemented, and the steps of the data processing method in any one of the foregoing embodiments have been described above in detail, and are not described again here.

The terminal device in the embodiment of the application can be a mobile terminal or a fixed terminal, wherein the mobile terminal includes but is not limited to a mobile phone, a tablet computer or a notebook computer; fixed terminals include, but are not limited to, desktop computers. The method can be applied to any device capable of running a computer program and capable of displaying.

Another aspect of the present application provides a storage medium, on which a computer program is stored, the computer program being executed by a processor to implement the steps of the data processing method in any one of the above embodiments.

Optionally, the storage medium may be applied to the terminal device in the embodiment of the present application, and the computer program enables the computer to execute corresponding steps in each data processing method in the embodiment of the present application, which is not described herein again for brevity.

The above description of the embodiments of the storage medium and the terminal device 1000 is similar to the description of any one of the embodiments of the data processing method described above, and has the same beneficial effects as the embodiments of the same data processing method. For technical details that are not disclosed in the embodiments of the storage medium and the terminal device 1000 in the embodiments of the present application, please refer to the description of the embodiments of the data processing method in the embodiments of the present application for understanding.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only exemplary of the present application and should not be taken as limiting the scope of the present application, as any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

26页详细技术资料下载

Data processing method, data processing device, terminal device and storage medium

相关技术

网友询问留言