阅读说明：本技术 具有浮栅晶体管的物理不可克隆功能的器件及其制造方法 (Device with physical unclonable function of floating gate transistor and manufacturing method thereof ) 是由 F·拉罗萨 于 2020-02-21 设计创作，主要内容包括：本文描述了具有浮栅晶体管的物理不可克隆功能的器件及其制造方法。根据一个实施例,一种物理不可克隆功能器件包括：浮栅晶体管对集合,浮栅晶体管对集合中的浮栅晶体管具有属于共同随机分布的经随机分布的有效阈值电压；差分读取电路,被配置为测量浮栅晶体管对集合中的浮栅晶体管对的浮栅晶体管的有效阈值电压之间的阈值差,并且将其中所测量的阈值差小于裕度值的浮栅晶体管对标识为不可靠的浮栅晶体管对；以及写入电路,被配置为将不可靠的浮栅晶体管对的浮栅晶体管的有效阈值电压移位到共同随机分布内。(Described herein are devices having a physically unclonable function of floating gate transistors and methods of making the same. According to one embodiment, a physically unclonable function device comprises: a floating gate transistor pair set, the floating gate transistors in the floating gate transistor pair set having randomly distributed effective threshold voltages belonging to a common random distribution; differential read circuitry configured to measure threshold differences between effective threshold voltages of floating-gate transistors of floating-gate transistor pairs in the set of floating-gate transistor pairs, and identify floating-gate transistor pairs in which the measured threshold differences are less than a margin value as unreliable floating-gate transistor pairs; and a write circuit configured to shift effective threshold voltages of floating gate transistors of unreliable floating gate transistor pairs into a common random distribution.)

1. A physically unclonable function device, comprising:

a set of floating gate transistor pairs, the floating gate transistors in the set of floating gate transistor pairs having randomly distributed effective threshold voltages belonging to a common random distribution;

differential read circuitry configured to measure threshold differences between the effective threshold voltages of floating-gate transistors of floating-gate transistor pairs of the set of floating-gate transistor pairs, and identify floating-gate transistor pairs in which the measured threshold differences are less than a margin value as unreliable floating-gate transistor pairs; and

write circuitry configured to shift the effective threshold voltages of floating-gate transistors of the unreliable floating-gate transistor pair into the common random distribution.

2. The device of claim 1, wherein the common random distribution is a distribution of threshold voltages of floating-gate transistors that have never been written.

3. The device of claim 1, wherein the write circuit is configured to shift the effective threshold voltage of the floating gate transistor by generating conditions for hot carrier injection to trap charge in a gate dielectric of the floating gate transistor.

4. The device of claim 3, wherein the write circuitry is configured to generate the condition for hot carrier injection by applying a series of write pulses, each of the write pulses configured to inject a substantial amount of charge into a floating gate of the floating gate transistor.

5. The device of claim 4, wherein the differential read circuit is configured to perform margin verification after at least one write pulse in the series of write pulses, wherein performing the margin verification comprises comparing the measured threshold difference to the margin value.

6. The device of claim 1, wherein the differential read circuit is further configured to read a logic state of a floating-gate transistor pair of the set of floating-gate transistor pairs, wherein the logic state is defined by a voltage difference between the effective threshold voltages of the floating-gate transistors of the floating-gate transistor pair when the voltage difference exceeds the margin value.

7. The device of claim 6, wherein the logic states of the set of floating-gate transistor pairs form a random data sequence.

8. An integrated circuit, comprising:

a physically unclonable function device according to claim 7; and

an encryption device configured to encrypt data using a key, wherein the key comprises the random data sequence.

9. A method, comprising:

providing a set of floating-gate transistor pairs, wherein the effective threshold voltages of the floating-gate transistors in the set of floating-gate transistor pairs are randomly distributed according to a common random distribution;

measuring threshold differences between effective threshold voltages of floating gate transistors in the set of floating gate transistor pairs and identifying floating gate transistor pairs in the set of floating gate transistor pairs for which the measured threshold differences are less than a margin value as unreliable floating gate transistor pairs; and

shifting the effective threshold voltages of floating gate transistors in the unreliable floating gate transistor pair into the common random distribution.

10. The method of claim 9, wherein the shifting comprises: increasing the threshold difference of the unreliable floating gate transistor pair above the margin value.

11. The method of claim 9, wherein shifting the effective threshold voltage of the floating gate transistor comprises: applying a series of write pulses that each injects a substantial amount of charge into a floating gate of the floating gate transistor.

12. The method of claim 11, further comprising: performing margin verification after at least one write pulse in the series of write pulses, wherein performing the margin verification comprises comparing the measured threshold difference to the margin value.

13. The method of claim 9, further comprising: reading a logic state of a floating-gate transistor pair of the set of floating-gate transistor pairs, wherein the logic state is defined by the threshold difference when the threshold difference exceeds a margin value.

14. The method of claim 13, wherein logic states of the set of floating-gate transistor pairs form a random data sequence.

15. The method of claim 14, further comprising: encrypting data using a key, wherein the key comprises the random data sequence.

16. The method of claim 9, further comprising: fabricating the set of floating-gate transistor pairs, wherein each transistor in the set of floating-gate transistor pairs is fabricated to have the same nominal threshold voltage.

17. The method of claim 16, wherein the common random distribution is a distribution of threshold voltages of floating gate transistors that have never been written.

18. An integrated circuit, comprising:

a plurality of floating-gate transistor pairs, wherein a first floating-gate transistor of each floating-gate transistor pair of the plurality of floating-gate transistor pairs is coupled to a first bit line and a second floating-gate transistor of each floating-gate transistor pair of the plurality of floating-gate transistor pairs is coupled to a second bit line, and the floating-gate transistors of the plurality of floating-gate transistor pairs have randomly distributed effective threshold voltages according to a common random distribution;

a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to measure a threshold difference between the first floating-gate transistor and the second floating-gate transistor of each of the plurality of floating-gate transistor pairs and compare the measured threshold difference to a predetermined threshold; and

a write circuit coupled to gates of the first and second floating-gate transistors of each floating-gate transistor pair of the plurality of floating-gate transistor pairs, wherein the write circuit is configured to shift the effective threshold voltages of the first and second floating-gate transistors of each floating-gate transistor pair such that the measured threshold difference is greater than the predetermined threshold and within the common random distribution.

19. The integrated circuit of claim 18, wherein the read circuit comprises:

a read amplifier coupled to the first input and the second input of the read circuit; and

a reference current generator coupled to the first input or the second input, wherein the reading circuit is configured to compare the measured threshold difference to the predetermined threshold by activating the reference current generator and measuring a voltage difference between the first input and the second input.

20. The integrated circuit of claim 18, wherein the write circuitry is configured to shift the effective threshold voltage of the first or second floating-gate transistor of each floating-gate transistor pair by applying at least one write pulse to the respective first or second floating-gate transistor.

21. The integrated circuit of claim 18, wherein:

a first set of floating-gate transistor pairs of the plurality of floating-gate transistor pairs comprises a logic state;

each logic state is one of a first logic state or a second logic state;

the read circuit is configured to detect the first logic state when an effective threshold of the first floating-gate transistor is greater than a sum of an effective threshold of the second floating-gate transistor and the predetermined threshold; and is

The read circuit is configured to detect the second logic state when the effective threshold of the second floating-gate transistor is greater than a sum of the effective threshold of the first floating-gate transistor and the predetermined threshold.

22. The integrated circuit of claim 21, further comprising encryption circuitry coupled to the plurality of floating-gate transistor pairs, wherein the encryption circuitry is configured to use the logic states of the plurality of floating-gate transistor pairs as encryption keys.

Technical Field

Implementations and embodiments of the present invention relate to Physical Unclonable Functions (PUFs), particularly in structures that include floating gate transistors.

Background

The physically unclonable function allows for the automatic generation of unique unpredictable code that relies on random physical properties. Thus, even if cloning of this function is not impossible, it is very difficult.

On the one hand, it is desirable that the physically unclonable functions are sufficiently robust that they do not change over time, especially after repeated use or in the case of temperature changes. On the other hand, it is desirable to easily identifiable random variations of physical attributes so as to be able to unambiguously distinguish between various data. Furthermore, it is desirable that the generation of the physically unclonable function requires no or only few dedicated manufacturing steps.

The unique unpredictable code typically comprises a random sequence of data and is used primarily as an encryption key. These data are typically secret.

The fact is that there are some technologies, in particular those employing Scanning Capacitance Microscopy (SCM) or Scanning Electron Microscopy (SEM), which are able to extract secret data, i.e. to read the data by measurement, inspection and/or analysis.

This is especially true for conventional structures intended to achieve robust data retention and data readability. In particular, conventional techniques that increase the ability to retain and distinguish data for readout also typically increase the ability of extraction techniques to distinguish data.

Disclosure of Invention

According to one embodiment, a physically unclonable function device comprises: a floating gate transistor pair set, the floating gate transistors in the floating gate transistor pair set having randomly distributed effective threshold voltages belonging to a common random distribution; differential read circuitry configured to measure threshold differences between effective threshold voltages of floating-gate transistors of floating-gate transistor pairs in the set of floating-gate transistor pairs, and identify floating-gate transistor pairs in which the measured threshold differences are less than a margin value as unreliable floating-gate transistor pairs; and a write circuit configured to shift effective threshold voltages of floating gate transistors of unreliable floating gate transistor pairs into a common random distribution.

According to another embodiment, a method comprises: providing a set of floating gate transistor pairs, wherein the effective threshold voltages of the floating gate transistors in the set of floating gate transistor pairs are randomly distributed according to a common random distribution; measuring a threshold difference between effective threshold voltages of floating gate transistors in the set of floating gate transistor pairs, and identifying floating gate transistor pairs in the set of floating gate transistor pairs for which the measured threshold difference is less than a margin value as unreliable floating gate transistor pairs; and shifting effective threshold voltages of floating gate transistors in unreliable floating gate transistor pairs into a common random distribution.

According to yet another embodiment, an integrated circuit includes: a plurality of floating gate transistor pairs, wherein a first floating gate transistor of each floating gate transistor pair of the plurality of floating gate transistor pairs is coupled to a first bit line and a second floating gate transistor of each floating gate transistor pair of the plurality of floating gate transistor pairs is coupled to a second bit line, and the floating gate transistors of the plurality of floating gate transistor pairs have randomly distributed effective threshold voltages according to a common random distribution; a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to measure a threshold difference between the first floating-gate transistor and the second floating-gate transistor of each of the plurality of floating-gate transistor pairs and compare the measured threshold difference to a predetermined threshold; and a write circuit coupled to the gates of the first floating gate transistor and the second floating gate transistor of each of the plurality of floating gate transistor pairs, wherein the write circuit is configured to shift the effective threshold voltage of the first floating gate transistor and the second floating gate transistor of each floating gate transistor pair such that the measured threshold difference is greater than a predetermined threshold and within a common random distribution.

Drawings

Further advantages and features of the invention will become apparent from an examination of the detailed description of a purely non-limiting implementation and embodiment and the accompanying drawings, in which:

FIG. 1A illustrates threshold distributions for a memory;

FIG. 1B illustrates a scanning capacitance micrograph SC of a transistor storing data;

FIG. 2 illustrates an example embodiment of the present invention;

FIG. 3 illustrates an example embodiment of the present invention;

FIG. 4 illustrates an example embodiment of the present invention;

FIG. 5 illustrates an example embodiment of the present invention;

FIG. 6 illustrates an example embodiment of the present invention;

FIG. 7 illustrates an example embodiment of the present invention;

FIG. 8 illustrates an example implementation of the present invention;

FIG. 9 illustrates an example implementation of the present invention;

fig. 10 illustrates an example embodiment of the present invention.

Detailed Description

Implementations and embodiments of the present invention relate to Physical Unclonable Functions (PUFs), particularly in structures that include floating gate transistors.

According to one embodiment, the differential read circuit is further configured to read a logic state of a pair of floating-gate transistors, the logic state being defined by a difference between values of effective threshold voltages of the pair of floating-gate transistors that is greater than the margin value.

According to one embodiment, the write circuit is configured to shift the effective threshold voltage of each unreliable pair of floating gate transistors so as to increase the difference between the effective threshold voltages above a margin value.

According to one embodiment, a write circuit for shifting an effective threshold voltage of a floating gate transistor is configured to generate a series of write pulses, each of which injects a substantial amount of charge into a floating gate of the floating gate transistor.

According to one embodiment, the differential read circuit is configured to perform margin verification between at least some of the write pulses, the margin verification including comparing a difference between values of effective threshold voltages of the pair of floating-gate transistors to a margin value.

According to one embodiment, the logic states of the set of pairs of floating gate transistors are intended to form a random data sequence.

An integrated circuit may comprise a physically unclonable function device, such as defined in the latter embodiments, and an encryption device configured to encrypt data using a key, the key advantageously comprising a random sequence of data.

According to another aspect, there is provided a process comprising generating a physically unclonable function, the generating comprising: manufacturing a set of paired floating gate transistors intended to have the same threshold voltage; the random dispersion of the effective values of the threshold voltages of the floating gate transistors forms the common random distribution of the threshold voltages of the floating gate transistors; measuring the difference between the effective threshold voltages of the pairs of floating gate transistors and identifying so-called unreliable pairs of floating gate transistors whose difference between the effective threshold voltages is smaller than a margin value; the effective threshold voltages of the floating gate transistors in each unreliable pair are shifted in a controlled and limited manner so that the shifted threshold voltages remain within a common random distribution.

According to one implementation, the common random distribution is a distribution of threshold voltages of the original floating-gate transistors that were never written.

According to one implementation, the process further includes reading a logic state of a pair of floating gate transistors, the logic state defined by a difference between values of effective threshold voltages of the pair of floating gate transistors that is greater than a margin value.

For example, the shifting includes increasing the difference between the effective threshold voltages of the floating gate transistors in unreliable pairs above a margin value.

According to one implementation, the shifting of the effective threshold voltage of one of the floating gate transistors in an unreliable pair comprises a series of write pulses, each of which injects a substantial amount of charge into the floating gate of the floating gate transistor.

Advantageously, the shifting comprises margin verification between at least some of the write pulses, the margin verification comprising measuring a difference between values of effective threshold voltages of the pair of floating gate transistors, and comparing the measured difference with a margin value.

According to one implementation, the logic states of the set of paired floating gate transistors are intended to form a random data sequence.

The encryption method may advantageously comprise encrypting the data using a key comprising a random sequence of data obtained using a procedure such as that defined by the latter implementation.

Fig. 1A illustrates a conventional technique aimed at achieving robust data retention and data readability, in which the data is defined by the level of the floating gate transistor threshold voltage Vt. The threshold voltage level is set by injecting positive or negative charge into the floating gate. The first floating gate transistor has a threshold voltage Vt belonging to a low level distribution D1, the low level distribution D1 allowing to define, for example, a first logical value "1". The second floating gate transistor has a threshold voltage Vt belonging to a high level distribution D0, which high level distribution D0 allows to define, for example, a second logical value "0".

FIG. 1B illustrates a scanning capacitance micrograph SC of floating gate transistors using the technique presented with reference to FIG. 1A to store data. The stored data sequence 1010 can be easily extracted if the location of the floating gate transistor is known. Specifically, the channel region of the first floating gate transistor (the threshold voltage of which belongs to the low-level distribution D1) in the black circle and the channel region of the second floating gate transistor (the threshold voltage of which belongs to the high-level distribution D0) in the white circle can be seen in the image SC. This is of course problematic.

Therefore, there is a need to provide a physically unclonable functional structure that is robust against external changes or aging and whose data can be clearly distinguished for readout while being difficult to extract. Furthermore, it would be beneficial in the art to easily manufacture such a structure.

According to one aspect, there is provided a physically unclonable function device, the device comprising: a set of paired floating gate transistors intended to have the same threshold voltage but each having an effective threshold voltage belonging to a common random distribution; differential read circuitry configured to measure a difference between effective threshold voltages of the pairs of floating gate transistors and to identify so-called unreliable pairs of floating gate transistors whose difference between effective threshold voltages is less than a margin value; and a write circuit configured to shift the effective threshold voltage of the floating gate transistors in each unreliable pair in a controlled and limited manner such that the shifted threshold voltages remain within a common random distribution.

Thus, the device according to this aspect benefits from the advantages of floating gate transistor data storage, i.e. very good retention capability, robustness and well characterized manufacturing processes and operating parameters. Since the effective threshold voltages all belong to a common random distribution, the function is not only physically unclonable, but also cannot be extracted using microscopic techniques in the art. In unreliable pairings, the shift of the effective threshold voltage allows to guarantee the feasibility of the technique, in particular the distinction between two effective threshold voltages which may be equal or very close.

The common random distribution is advantageously the distribution of threshold voltages of the original floating gate transistors that have never been written.

Fig. 2 shows an exemplary embodiment of a physically unclonable function device DIS. The device DIS comprises a set ENS of pairs P of floating-gate transistors FGT1, FGT 2.

Conventionally, a floating gate transistor includes: a source region and a drain region implanted in the semiconductor body; a channel region in the body between the source region and the drain region; and a conductive floating gate insulated from the channel region and insulated from the control gate overlying the floating gate. The threshold voltage of the floating gate transistor is a voltage between the source region and the control gate, according to which the channel region is depleted and turned on.

The floating gate transistor is written when charge is injected into the floating gate and trapped therein. The charge modifies the threshold voltage of the transistor being written according to its sign and then either programs or erases it.

The floating-gate transistors FGT1, FGT2 of the set ENS are intended to have the same threshold voltage.

As such, the effective threshold voltage (i.e., the actual value of the threshold voltage) varies slightly according to random dispersion, for example, due to physical manufacturing variables. This type of dispersion is common and known per se. The effective threshold voltage of each pair of floating-gate transistors referenced FGT1 is referenced A1-F1, and the effective threshold voltage of each pair of floating-gate transistors referenced FGT2 is referenced A2-F2.

Thus, the floating-gate transistors FGT1, FGT2 of the set ENS each have an effective threshold voltage belonging to a common random distribution.

In particular, the floating-gate transistors FGT1, FGT2 may advantageously remain in an original state, i.e. without charge being injected into their floating gates. Thus, in this particular case, the common random distribution is the distribution of the threshold voltage Vteff of the original floating gate transistors that have never been written.

Fig. 3 illustrates a scanning capacitance micrograph of floating gate transistors belonging to the set ENS. Each floating gate transistor has an effective threshold voltage that belongs to a common distribution of the original floating gate transistor threshold voltage Vteff. Therefore, it is not possible to see any distinction between the values of the threshold voltages using today's microscopic techniques.

Alternatively, the floating-gate transistors FGT1, FGT2 of the aggregate ENS may optionally be all programmed (i.e. all having negative charge on their floating gates) or erased (i.e. having positive charge injected into their floating gates).

Referring again to fig. 2, the device DIS includes a differential reading circuit LECT configured to measure the difference between the effective threshold voltages of the floating-gate transistors FGT1, FGT2 of the pair P.

The differential read circuit LECT comprises two differential inputs to which each pair P of floating-gate transistors FGT1, FGT2 is coupled, in particular via a respective bit line BL1, BL2, respectively.

In this regard, reference is now made to fig. 4 and 5.

Fig. 4 shows an example of an embodiment of a differential read circuit LECT coupled to one pair of floating-gate transistors FGT1, FGT2 via respective bit lines BL1, BL 2. In this example, the floating-gate transistors FGT1, FGT2 belong to the respective memory cells CEL1, CEL2, wherein the access floating-gate transistors TA1, TA2 are connected via their drains to the sources of the floating-gate transistors FGT1, FGT2 and via their sources to ground GND.

The access floating gate transistors TA1, TA2 are controlled via their gates by signals transmitted on the respective word lines WL1, WL 2. As will become clear below, the word lines WL1, WL2 may optionally be common to one pair, i.e. electrically connected or even formed by the same electrically conductive line. The control gates of the floating-gate transistors FGT1, FGT2 are connected to respective control gate lines CGL1, CGL 2. Likewise, the control gate lines CGL1, CGL2 may optionally be common to one pair of floating gate transistors, i.e. electrically connected or even formed by the same electrically conductive line. The drains of the floating-gate transistors FGT1, FGT2 are connected, for a part thereof, to respective bit lines BL1, BL 2.

The bit line BL1 allows one floating gate transistor FGT1 of the pair to be coupled to the first input E1 of the sense amplifier AMP. The bit line BL2 allows the other floating gate transistor FGT2 of the pair to be coupled to the second input E2 of the sense amplifier AMP.

The other floating gate transistors in the set ENS of pairs P are coupled to the sense amplifier AMP in the same manner, and the respective input switches TBL1, TBL2 allow selection of the desired pair of bit lines BL1, BL 2.

Furthermore, the reading circuit LECT comprises a reference current generator IGEN generating a reference current IREF drawn by the first input E1 or the second input E2 depending on the position of the respective switch SW1, SW 2.

Fig. 5 shows an example of an embodiment of the differential read circuit LECT in operation. The sense amplifier AMP is configured to amplify the difference between the current through its first input E1 and the current through its second input E2. To this end, input switches TBL1, TBL2 are controlled to couple the bitlines BL1, BL2 of the desired pair of floating gate transistors. The access floating gate transistor TA1, TA2 of each floating gate transistor FGT1, FGT2 is turned on by a voltage transmitted on the word line WL1, WL 2. Likewise, the floating gate transistors FGT1, FGT2 are controlled by a control gate voltage transmitted on the control gate lines CGL1, CGL 2.

Thus, the floating-gate transistor FGT1 in the pair is placed such that the read current I1 flows from the first input E1 to ground GND. The other floating-gate transistor FGT2 of the pair is also placed such that the read current I2 flows from the second input E2 to ground GND.

Since the read currents I1, I2 represent the effective threshold voltages of the respective floating-gate transistors FGT1, FGT2, the difference between the currents I1, I2 represents the difference between the effective threshold voltages of the paired floating-gate transistors FGT1, FGT 2.

Thus, the differential read circuit LECT is able to measure the difference between the effective threshold voltages of the paired floating-gate transistors FGT1, FGT 2.

Furthermore, an additional current IREF generated by one of the reference current generators IGEN may be added to one of the currents I1, I2 through the inputs E1, E2 via control of the switches SW1, SW 2. In the example shown, switch SW2 is closed and current IREF is added to current I2 of second input E2.

This allows the difference between the effective threshold voltages to be measured against a certain margin. The value of the margin corresponds to the current IREF, which represents the reference voltage deviation. In particular, the margin value is selected according to the accuracy of the differential read circuit LECT.

Referring now to fig. 6, there is shown an example of various threshold voltage values a1, B1, C1, D1, E1, F1 of one floating gate transistor FGT1 of each pair of the set ENS, and of threshold voltage values a2, B2, C2, D2, E2, F2 of the respective other floating gate transistor FGT2 of each pair. The values a1 to F1, a2 to F2 all belong to a common random distribution DST of the effective threshold voltage Vteff.

The differential read circuit LECT according to an example embodiment (e.g. as described with reference to fig. 4 and 5) is further configured to read the logic state DAT of each pair of floating-gate transistors FGT1, FGT 2. The logical state DAT is defined by a difference between the pair of valid threshold voltage values that is greater than the margin value MRG. For example, if X1> X2+ MRG, DAT is 1, and if X2> X1+ MRG, DAT is 0, where X1 is any of values a1 to F1, and X2 is any of values a2 to F2.

Thus, the logic state is obtained in a physically unclonable manner using random deviations of the values of the effective threshold voltages of the two floating gate transistors in the pair. Assuming that these effective threshold voltages are close and belong to a common random distribution DST, it is not possible to distinguish either of the two stored data by microscopic examination.

It will be noted that in the figure, certain pairs of threshold voltage values C1, C2 and E1, E2 may be close and have deviations less than the margin value MRG. Paired floating gate transistors with these paired values are referred to as unreliable pairs NF.

Referring again to fig. 2, the differential read circuit LECT is configured to identify the floating gate transistors of the pair P belonging to the so-called unreliable pair NF, for example using a differential measurement such as that described above with reference to fig. 4 and 5. The floating-gate transistors FGT1, FGT2 of the pair P are said to be unreliable if the difference between the effective threshold voltages of the floating-gate transistors is less than a margin value (e.g., the margin value MRG as described above with reference to fig. 4 and 5).

The device DIS finally comprises a write circuit ECR which is able in particular to generate the write pulse IMP.

The write pulse IMP is configured to obtain conditions for soft programming the floating gate transistor in order to increase the threshold voltage value of the floating gate transistor via hot carrier injection into the floating gate.

In other words, in contrast to conventional EEPROM memory erase or program pulses in which the drain floating gate voltage is about 8 to 12 volts, the write pulse IMP is limited such that the drain floating gate voltage is, for example, about 4.5 to 5 volts.

Furthermore, the generation of the write pulse is controlled, i.e. this comprises, for example, checking the phase in order to adjust the generation of the pulse. In this regard, reference may be made to the example implementation described below with reference to fig. 9.

Thus, in contrast to conventional programming and erasing of floating gate transistors (e.g., as shown in FIG. 1A) which create two populations of floating gate transistors whose threshold voltages are strictly different, the controlled and limited write pulse IMP allows the threshold voltages to shift slightly so that the newly shifted threshold voltages are reasonably considered to belong to the same common random distribution.

In this regard, referring to fig. 7, which returns to the example shown in fig. 6, the effective threshold voltages C2 and E1 of one floating gate transistor in each unreliable pair NF have been shifted to shifted values C2 ', E1'.

The write circuit ECR is configured to shift the effective threshold voltages C2, E1 of the floating gate transistors in each unreliable pair NF in order to increase the difference between the effective threshold voltages above a margin value MRG.

This allows the logic state DAT defined by the difference between the values of the pair of effective threshold voltages greater than the margin value MRG to be reliably read in the pair identified as an unreliable pair NF.

Of course, theoretically this means that the initial distribution DST is slightly modified to a shifted distribution DST'. In this way, it can be reasonably assumed that the shifted values C2 'and E1' belong to an initial common distribution (i.e., a common random distribution DST obtained at the time of manufacture). In particular, distributions DST and DST' are very similar and considered to be the same as compared to threshold voltage distribution D1 for conventionally programmed transistors and threshold voltage distribution D0 (also corresponding to fig. 1A) for conventionally erased transistors.

In other words, the write circuit ECR is configured to shift the effective threshold voltage of the floating gate transistors in each unreliable pair NF in a controlled and limited manner within a common random distribution DST.

In any case, the shifted threshold voltages can be considered to be within a common random distribution DST as long as their values cannot be distinguished using scanning microscopy techniques.

The populations of programmed and erased transistors of distributions D1, D0 can be distinguished by microscopy, but the populations of floating gate transistors of the initial distribution DST and the shifted distribution DST' cannot be distinguished.

Fig. 8 shows an example of an implementation including in particular a process of generating a physically unclonable function. Some references are related to fig. 2-7 described above.

The process includes step 71: a set ENS of pairs P of floating gate transistors FGT1, FGT2 is manufactured. The fabrication of the floating gate transistors is the same, so that the fabricated floating gate transistors are intended to have the same threshold voltage.

For example, the transistor so fabricated is intended to have the threshold voltage of the original floating gate transistor never written.

This process includes a random dispersion 72 of the effective value of the threshold voltage Vteff of the floating gate transistor. The dispersion is due in particular to physical manufacturing variables and is therefore at least partially done directly in manufacturing step 71. The dispersion of the effective values forms a common random distribution DST of the threshold voltages of the floating gate transistors of the set ENS.

It is contemplated that the conditions of enhanced random dispersion may be achieved in a dedicated step or in manufacturing step 71.

The process includes step 73: the difference between the effective threshold voltages Vteff of the pairs of floating gate transistors is measured and the pairs of floating gate transistors considered as unreliable pairs NF are identified 74, the difference between the effective threshold voltages of the unreliable pairs NF being smaller than the margin value MRG.

Finally, the process includes shifting 75 the effective threshold voltage of the floating gate transistors in each unreliable pair NF in a controlled and limited manner within a common random distribution DST.

The shift 75 is implemented so as to increase the difference between the effective threshold voltages of the floating gate transistors in the unreliable pair NF above the margin value MRG.

Referring now to fig. 9, fig. 9 illustrates an example of an implementation of shift 75. In this example, the shift 75 of the effective threshold voltage comprises a series of write pulses 751. Each write pulse 751 injects a substantial amount of charge into the floating gate of the floating gate transistor whose threshold voltage is to be shifted. In this sequence, margin verification (752, 753) is performed between at least some of the write pulses 751. Margin verification includes measuring 752 a difference between values of effective threshold voltages of the pair of floating gate transistors after one or more write pulses 751, and then comparing 753 the measured difference to a margin value MRG.

If the measured difference 752 is less than the margin value MRG (nok), a new cycle including write pulse 751 and margin verifications 752, 753 is added to the sequence.

When the measured difference 752 is greater than or equal to the margin value mrg (ok), then the shift 75 ends 754. By means of margin verifications 752, 753 in the sequence of write pulses 751, the threshold voltage is shifted in a controlled manner so as not to bring the threshold voltage values outside the common random distribution DST obtained at manufacture.

Referring again to fig. 8, the process may further include step 76: reading a logic state DAT for a pair of floating gate transistors, the logic state defined by a difference between values of the pair of effective threshold voltages Vteff that is greater than a margin value MRG.

The logical states DAT formed in the set ENS of floating-gate transistors FGT1, FGT2 of pairs P may thus for example be intended to form a random data sequence.

Fig. 10 shows an integrated circuit CI obtained, for example, using a process such as described above with reference to fig. 8 and 9, the integrated circuit CI comprising a physically unclonable function device DIS such as described above with reference to fig. 2 to 7.

In the device DIS, the logical states DAT of the set ENS of floating-gate transistors FGT1, FGT2 of pairs P are thus intended to form a random data sequence.

In this example, the integrated circuit CI is able to perform an encryption method comprising encrypting the CFR data DNC using a key K comprising a random sequence of data formed and stored in a set ENS of paired floating gate transistors.

The encryption circuit CFR incorporated in the integrated circuit CI is configured to encrypt the data DNC using the key K.

Furthermore, the integrated circuit CI may comprise a non-volatile memory NVM comprising memory cells each having a floating-gate state transistor advantageously manufactured in the same manufacturing step 71 as the set ENS of floating-gate transistors FGT1, FGT2 of the pair P.

In summary, a physical unclonable function technique has been proposed in which the logical state is defined by the relative difference between two pieces of information belonging to the same distribution. Data cannot be extracted using prior art methods (scanning capacitance microscope (SCM) or Scanning Electron Microscope (SEM)). The technique does not require a specific and dedicated process.

Furthermore, the present invention is not limited to these embodiments, but covers, for example, all variations thereof, even if the example embodiments described above with reference to fig. 4 and 5 relate to a current-mode differential sense amplifier, differential sensing may be performed in voltage mode, or indeed reduction may be achieved by injecting charges of opposite sign even if the shift direction shown in fig. 6 and 7 is increased.