阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 片山明 于 2019-06-27 设计创作，主要内容包括：实施方式提供一种能够抑制误读出的半导体存储装置。一实施方式的半导体存储装置具备存储单元及控制电路。控制电路以如下方式构成：基于存储在存储单元的第1数据将第1电压充电至第1节点,在产生第1电压之后对存储单元写入第2数据,基于第2数据将第2电压充电至第2节点,基于第1电压及第2电压,判定第1数据是否与第2数据不同；且包含：第1开关元件,包含电连接于第1节点的第1端、及电连接于第1节点与第2节点之间的第3节点的第2端；第2开关元件,包含电连接于第1节点的第1端及第2端,且具有与第1开关元件相同的尺寸；及第3开关元件,包含电连接于第2节点的第1端、及电连接于第3节点的第2端。(Embodiments provide a semiconductor memory device capable of suppressing erroneous reading. A semiconductor memory device according to one embodiment includes a memory cell and a control circuit. The control circuit is configured in the following manner: charging a1 st voltage to a1 st node based on a1 st data stored in a memory cell, writing a2 nd data to the memory cell after generating the 1 st voltage, charging a2 nd voltage to a2 nd node based on the 2 nd data, and determining whether the 1 st data is different from the 2 nd data based on the 1 st voltage and the 2 nd voltage; and comprises: a1 st switching element including a1 st terminal electrically connected to the 1 st node and a2 nd terminal electrically connected to a 3 rd node between the 1 st node and the 2 nd node; a2 nd switching element including a1 st terminal and a2 nd terminal electrically connected to the 1 st node, and having the same size as the 1 st switching element; and a 3 rd switching element including a1 st terminal electrically connected to the 2 nd node and a2 nd terminal electrically connected to the 3 rd node.)

1. A semiconductor memory device includes a memory cell and a control circuit,

the control circuit is configured in the following manner:

charging a1 st voltage to a1 st node based on a1 st data stored in the memory cell,

writing 2 nd data to the memory cell after generating the 1 st voltage,

charging a2 nd voltage to a2 nd node based on the 2 nd data,

determining whether the 1 st data is different from the 2 nd data based on the 1 st voltage and the 2 nd voltage; and comprises:

a1 st switching element including a1 st terminal electrically connected to the 1 st node and a2 nd terminal electrically connected to a 3 rd node between the 1 st node and the 2 nd node;

a2 nd switching element including a1 st terminal and a2 nd terminal electrically connected to the 1 st node, and having the same size as the 1 st switching element; and

and a 3 rd switching element including a1 st terminal electrically connected to the 2 nd node and a2 nd terminal electrically connected to the 3 rd node.

2. The semiconductor memory device according to claim 1, wherein

The control circuit is configured in the following manner: after the 1 st switching element is switched to the off state, the 2 nd switching element is switched to the on state.

3. The semiconductor memory device according to claim 2, wherein

The control circuit is configured in the following manner: before switching the 3 rd switching element to the on state, switching the 2 nd switching element to the on state.

4. The semiconductor memory device according to claim 2, wherein

The control circuit is configured in the following manner: after the 3 rd switching element is switched to the on state, the 2 nd switching element is switched to the on state.

5. The semiconductor memory device according to claim 1, wherein

The control circuit further includes a 4 th switching element, the 4 th switching element being connected in parallel between the 1 st node and the 3 rd node with respect to the 1 st switching element,

the 1 st switching element and the 2 nd switching element have a size smaller than the 4 th switching element.

6. The semiconductor memory device according to claim 5, wherein

The control circuit is configured in the following manner:

switching the 1 st switching element to an off state after switching the 4 th switching element to an off state,

after the 1 st switching element is switched to the off state, the 2 nd switching element is switched to the on state.

7. The semiconductor memory device according to claim 1, wherein

The control circuit further includes:

a 4 th switching element connected in parallel between the 1 st node and the 3 rd node with respect to the 1 st switching element; and

a 5 th switching element including a1 st terminal and a2 nd terminal electrically connected to the 1 st node, and having the same size as the 4 th switching element;

the 1 st switching element and the 2 nd switching element have a size smaller than the 4 th switching element and the 5 th switching element.

8. The semiconductor memory device according to claim 7, which

Further comprises a monitoring circuit for monitoring the operating state of the control circuit,

the control circuit is configured in the following manner:

in the case where the information from the monitoring circuit satisfies a condition,

switching the 1 st switching element to an off state after switching the 4 th switching element to an off state,

switching the 2 nd switching element to an on state after switching the 1 st switching element to an off state and before switching the 3 rd switching element to an on state;

in the case where the information does not satisfy the condition,

switching the 4 th switching element to an off state before switching the 1 st switching element to the off state,

after the 1 st switching element is switched to the off state and the 3 rd switching element is switched to the on state, the 2 nd switching element is switched to the on state.

9. The semiconductor memory device according to claim 8, wherein

The action condition includes a voltage of the 3 rd node,

satisfying the condition includes that the voltage of the 3 rd node is a specific value or more.

10. The semiconductor memory device according to claim 1, wherein

The control circuit further comprises a 6 th switching element, wherein the 6 th switching element comprises a1 st end electrically connected to the 3 rd node, a2 nd end grounded, and a gate electrically connected to the 1 st node.

11. The semiconductor memory device according to claim 1, wherein

The memory cell includes a resistance change element.

12. The semiconductor memory device according to claim 11, wherein

The resistance change element is a magnetoresistance effect element.

Technical Field

Background

A semiconductor memory device using a resistance variable element as a memory element is known. For example, a magnetic memory device (MRAM) using a Magnetoresistive element as a resistance variable element is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram illustrating a configuration of a semiconductor memory device according to embodiment 1.

Fig. 2 is a circuit diagram for explaining the configuration of the memory cell array of the semiconductor memory device according to embodiment 1.

Fig. 3 is a cross-sectional view for explaining the structure of the memory cell array of the semiconductor memory device according to embodiment 1.

Fig. 4 is a cross-sectional view for explaining the structure of the memory cell array of the semiconductor memory device according to embodiment 1.

Fig. 5 is a cross-sectional view for explaining the configuration of the magnetoresistive element of the semiconductor memory device according to embodiment 1.

Fig. 6 is a block diagram illustrating the configuration of a column selection circuit of the semiconductor memory device according to embodiment 1.

Fig. 7 is a circuit diagram for explaining the configuration of a preamplifier of the semiconductor memory device according to embodiment 1.

Fig. 8 is a circuit diagram for explaining the configuration of a sense amplifier of the semiconductor memory device according to embodiment 1.

Fig. 9 is a flowchart for explaining a read operation in the semiconductor memory device according to embodiment 1.

Fig. 10 is a timing chart for explaining a read operation in the semiconductor memory device according to embodiment 1.

Fig. 11 is a timing chart for explaining a read operation in the semiconductor memory device of the comparative example.

Fig. 12 is a flowchart for explaining a read operation in the semiconductor memory device according to embodiment 2.

Fig. 13 is a timing chart for explaining a read operation in the semiconductor memory device according to embodiment 2.

Fig. 14 is a circuit diagram for explaining the configuration of a preamplifier of the semiconductor memory device according to embodiment 3.

Fig. 15 is a timing chart for explaining a read operation in the semiconductor memory device according to embodiment 3.

Fig. 16 is a block diagram for explaining the structure of the semiconductor memory device according to embodiment 4.

Fig. 17 is a circuit diagram for explaining the configuration of a preamplifier in the semiconductor memory device according to embodiment 4.

Fig. 18 is a flowchart for explaining a read operation in the semiconductor memory device according to embodiment 4.

Embodiments relate to a semiconductor memory device.