阅读说明：本技术 一种防止闪存比特错误放大的方法和装置以及设备 (Method, device and equipment for preventing error amplification of flash memory bits ) 是由 李虎 陈伟 于 2020-04-28 设计创作，主要内容包括：本发明公开了一种防止闪存比特错误放大的方法和装置以及设备。其中,所述方法包括：给上位机和闪存之间进行数据传输,和在该传输的数据从缓存器中读出到闪存控制器内部的缓冲区空间的过程中,通过闪存控制器检测该传输的数据是否存在比特错误得到检测结果,和根据该得到的检测结果,对关联该检测结果的比特错误数据进行纠错得到正确的数据,以及通过闪存控制器将该正确的数据输送到闪存的缓存器中。通过上述方式,能够实现避免出现闪存比特错误被放大的情况出现。(The invention discloses a method, a device and equipment for preventing error amplification of flash memory bits. Wherein the method comprises the following steps: the method comprises the steps of transmitting data between an upper computer and a flash memory, detecting whether bit errors exist in the transmitted data through the flash memory controller to obtain a detection result in the process that the transmitted data are read out from the buffer memory to a buffer space in the flash memory controller, correcting the bit error data related to the detection result according to the obtained detection result to obtain correct data, and transmitting the correct data to the buffer memory of the flash memory through the flash memory controller. By the method, the situation that the flash memory bit error is amplified can be avoided.)

1. A method for preventing erroneous amplification of flash memory bits, comprising:

data transmission is carried out between the upper computer and the flash memory;

in the process that the transmitted data are read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether bit errors exist in the transmitted data to obtain a detection result;

correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data;

the correct data is transferred to a buffer of the flash memory by the flash memory controller.

2. The method for preventing error amplification of flash memory bits according to claim 1, wherein the data transmission between the host computer and the flash memory comprises:

and data transmission is carried out between the upper computer and the flash memory through the buffer area space inside the flash memory controller.

3. The method as claimed in claim 1, wherein the detecting whether the bit error exists in the transmitted data by the flash memory controller during the process of reading the transmitted data from the buffer into the buffer space inside the flash memory controller to obtain the detection result comprises:

in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold, when the transmitted data is detected to be not less than the preset error threshold, the detection result that the transmitted data is not in the range that the errors can be safely corrected is obtained, and when the transmitted data is detected to be less than the preset error threshold, the detection result that the transmitted data is in the range that the errors can be safely corrected is obtained.

4. The method for preventing flash memory bit error amplification according to claim 1, wherein said error correcting the bit error data associated with the detection result according to the obtained detection result to obtain correct data comprises:

and according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the errors can be safely corrected, the data in the range in which the errors can be safely corrected is not corrected, and when the detection result is that the transmitted data is not in the range in which the errors can be safely corrected, the error correction is carried out on the bit error data to obtain correct data.

5. The method for preventing error amplification of flash memory bits as claimed in claim 1, further comprising, before the data transmission between the host computer and the flash memory:

and paging the data page needing data transmission between the upper computer and the flash memory into at least two DMA.

6. An apparatus for preventing erroneous amplification of flash bits, comprising:

the device comprises a transmission module, a detection module, an error correction module and a conveying module;

the transmission module is used for transmitting data between the upper computer and the flash memory;

the detection module is used for detecting whether bit errors exist in the transmitted data through the flash memory controller to obtain a detection result in the process that the transmitted data are read out from the buffer to the buffer space in the flash memory controller;

the error correction module is used for correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data;

and the transmission module is used for transmitting the correct data to a buffer of the flash memory through the flash memory controller.

7. The apparatus for preventing erroneous amplification of flash bits as claimed in claim 6, wherein the transmission module is specifically configured to:

and data transmission is carried out between the upper computer and the flash memory through the buffer area space inside the flash memory controller.

8. The apparatus for preventing erroneous amplification of flash bits as claimed in claim 6, wherein the detection module is specifically configured to:

in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold, when the transmitted data is detected to be not less than the preset error threshold, the detection result that the transmitted data is not in the range that the errors can be safely corrected is obtained, and when the transmitted data is detected to be less than the preset error threshold, the detection result that the transmitted data is in the range that the errors can be safely corrected is obtained.

9. The apparatus for preventing flash bit error amplification as claimed in claim 6, wherein the error correction module is specifically configured to:

and according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the errors can be safely corrected, the data in the range in which the errors can be safely corrected is not corrected, and when the detection result is that the transmitted data is not in the range in which the errors can be safely corrected, the error correction is carried out on the bit error data to obtain correct data.

10. The apparatus for preventing erroneous amplification of a flash bit of claim 6, wherein the apparatus for preventing erroneous amplification of a flash bit further comprises:

a paging module;

and the paging module is used for paging a data page needing data transmission between the upper computer and the flash memory into at least two DMA.

Technical Field

The present invention relates to the field of flash memory technologies, and in particular, to a method, an apparatus, and a device for preventing error amplification of flash memory bits.

Background

With the development of Nand Flash technology, Flash memory has been developed from SLC (Single-Level Cell) solid state hard disk to QLC (Quad-Level Cell) solid state hard disk, and 1Bit (Bit) data is stored to 4Bit (Bit) data in each memory Cell, which is accompanied by an increase in Bit error probability, so that a Flash memory controller is required to have a stronger and stronger error correction algorithm to ensure the correctness of data.

However, in view of cost, the Flash controller cannot enhance the error correction capability indefinitely, and the controller must have a certain backward compatibility capability, and a certain support capability is required for the new Nand Flash, so that the new Nand Flash is supported as well as possible in the transition period before the new controller is born.

As is well known, after entering a TLC (Triple-Level Cell, three-layer memory Cell) technology, Nand Flash greatly improves the error correction capability of a controller, and on the other hand, due to the continuous increase of capacity, Page Size (Page Size) of Nand Flash is larger and larger. Based on the requirement of the algorithm of the Nand Flash, data transfer between the interiors is very frequent, and controllers carry out transfer by using a Copy-Back (write-Back) command built in the Nand Flash. The write-back type command can move the data of one Page to another specified Page in Nand Flash through a group of read-program commands without any data transmission with a Flash memory controller, thereby improving the speed of data movement.

However, just because the move lacks the participation of the Flash memory controller, due to the great increase of the Bit error probability of the Nand Flash, when the "read" command in the Nand Flash reads data from the storage unit into the internal Register, the Bit error may occur, and when the "program" command in the Nand Flash writes the data into another Page, which is equivalent to that the original data is originally erroneous, the new Bit error may be generated at the same time when the data of the Page is read in the future, so that the Bit error is amplified.

Disclosure of Invention

In view of the above, the present invention provides a method, an apparatus and a device for preventing flash bit error amplification, which can avoid the situation that a flash bit error is amplified.

According to an aspect of the present invention, there is provided a method for preventing error amplification of flash memory bits, comprising: paging a data page needing data transmission between an upper computer and a flash memory into at least two DMA; data transmission is carried out between the upper computer and the flash memory; in the process that the transmitted data are read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether bit errors exist in the transmitted data to obtain a detection result; and correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data.

Wherein, give and carry out data transmission between host computer and the flash memory, include: and data transmission is carried out between the upper computer and the flash memory through the buffer area space inside the flash memory controller.

Wherein, in the process of reading the transmitted data from the buffer into the buffer space inside the flash memory controller, detecting whether the transmitted data has a bit error through the flash memory controller to obtain a detection result, the method includes: in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold, when the transmitted data is detected to be not less than the preset error threshold, the detection result that the transmitted data is not in the range that the errors can be safely corrected is obtained, and when the transmitted data is detected to be less than the preset error threshold, the detection result that the transmitted data is in the range that the errors can be safely corrected is obtained.

Wherein, according to the obtained detection result, performing error correction on the bit error data associated with the detection result to obtain correct data includes: and according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the errors can be safely corrected, the data in the range in which the errors can be safely corrected is not corrected, and when the detection result is that the transmitted data is not in the range in which the errors can be safely corrected, the error correction is carried out on the bit error data to obtain correct data.

Wherein, give before carrying out data transmission between host computer and the flash memory, still include: and paging the data page needing data transmission between the upper computer and the flash memory into at least two DMA.

According to another aspect of the present invention, there is provided an apparatus for preventing erroneous amplification of flash bits, comprising: the device comprises a transmission module, a detection module, an error correction module and a conveying module; the transmission module is used for transmitting data between the upper computer and the flash memory; the detection module is used for detecting whether bit errors exist in the transmitted data through the flash memory controller to obtain a detection result in the process that the transmitted data are read out from the buffer to the buffer space in the flash memory controller; the error correction module is used for correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data; and the transmission module is used for transmitting the correct data to a buffer of the flash memory through the flash memory controller.

Wherein, the transmission module is specifically configured to: and data transmission is carried out between the upper computer and the flash memory through the buffer area space inside the flash memory controller.

Wherein, the detection module is specifically configured to: in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold, when the transmitted data is detected to be not less than the preset error threshold, the detection result that the transmitted data is not in the range that the errors can be safely corrected is obtained, and when the transmitted data is detected to be less than the preset error threshold, the detection result that the transmitted data is in the range that the errors can be safely corrected is obtained.

The error correction module is specifically configured to: and according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the errors can be safely corrected, the data in the range in which the errors can be safely corrected is not corrected, and when the detection result is that the transmitted data is not in the range in which the errors can be safely corrected, the error correction is carried out on the bit error data to obtain correct data.

Wherein, the apparatus for preventing error amplification of flash memory bits further comprises: a paging module; and the paging module is used for paging a data page needing data transmission between the upper computer and the flash memory into at least two DMA.

According to still another aspect of the present invention, there is provided an apparatus for preventing error amplification of flash bits, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any of the above methods for preventing flash bit error magnification.

According to yet another aspect of the present invention, there is provided a computer readable storage medium storing a computer program, which when executed by a processor implements the method for preventing erroneous amplification of flash bits as described in any of the above.

It can be found that, in the above scheme, data transmission can be performed between the upper computer and the flash memory, and in the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller detects whether the transmitted data has a bit error to obtain a detection result, and can correct the bit error data associated with the detection result according to the obtained detection result to obtain correct data, and the flash memory controller can convey the correct data to the buffer of the flash memory, so that the situation that the flash memory bit error is amplified can be avoided.

Furthermore, the above scheme can transmit data between the upper computer and the flash memory through the buffer space inside the flash memory controller, so that the advantage of transferring data between the upper computer and the flash memory through the buffer space inside the flash memory controller can be realized, and the purpose of preventing flash memory bit errors from being amplified can be achieved.

Further, in the above scheme, during the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller may detect whether the transmitted data has a condition that the number of bit errors is not less than the preset error threshold, obtain a detection result that the transmitted data is not within a range in which the errors can be safely corrected when detecting that the number of bit errors is not less than the preset error threshold, and obtain a detection result that the transmitted data is within a range in which the errors can be safely corrected when detecting that the number of bit errors is less than the preset error threshold.

Further, the above-mentioned solution may not perform error correction on the data within the range in which the error can be safely corrected when the detection result is that the transmitted data is within the range in which the error can be safely corrected, and may perform error correction on the bit error data to obtain correct data when the detection result is that the transmitted data is not within the range in which the error can be safely corrected.

Furthermore, the above scheme can divide the data page needing data transmission between the upper computer and the flash memory into at least two DMAs, which has the advantages of realizing the subsequent mode of conveniently performing error correction by randomly inserting error correction data only in the page with flash memory bit errors in the at least two DMAs divided into the pages, and not performing random insertion of error correction data in the page without flash memory bit errors in the at least two DMAs divided into the pages, thereby saving the transmission time of data transmission between the upper computer and the flash memory as much as possible and reducing the data processing speed loss of the flash memory to the minimum.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart illustrating an embodiment of a method for preventing error amplification of flash bits according to the present invention;

FIG. 2 is a flow chart illustrating another embodiment of a method for preventing error amplification of flash bits according to the present invention;

FIG. 3 is a schematic diagram of an apparatus for preventing bit error amplification of a flash memory according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another embodiment of the apparatus for preventing bit error amplification of a flash memory according to the present invention;

FIG. 5 is a schematic diagram of an embodiment of an apparatus for preventing flash bit error amplification according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.

The invention provides a method for preventing error amplification of flash memory bits, which can avoid the situation that the error amplification of the flash memory bits occurs.

Referring to fig. 1, fig. 1 is a flow chart illustrating a method for preventing error amplification of flash bits according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 1 if the results are substantially the same. As shown in fig. 1, the method comprises the steps of:

s101: and data transmission is carried out between the upper computer and the flash memory.

Wherein, should give and carry out data transmission between host computer and the flash memory, can include:

the Buffer space in the flash memory controller is used for data transmission between the upper computer and the flash memory, so that the advantage that the data transmission between the upper computer and the flash memory can be transferred through the Buffer space in the flash memory controller can be realized, and the purpose of preventing flash memory bit errors from being amplified can be achieved.

Wherein, should give before carrying out data transmission between host computer and the flash memory, can also include:

the method has the advantages that the subsequent mode that the error correction data is inserted randomly through the pages with flash memory bit errors only in the at least two DMA pages which are divided into pages is convenient to correct errors, and the pages without flash memory bit errors in the at least two DMA pages which are divided into pages are not inserted randomly into the error correction data is realized, so that the transmission time of data transmission between the upper computer and the flash memory can be saved as much as possible, and the data processing speed loss of the flash memory is reduced to the minimum.

In this embodiment, the flash memory can support random data insertion, because the DMA transfer and error correction of the flash memory controller are mostly based on 512B (Byte) or 1024B, and the Page Size of the flash memory is usually 8KB (Kilobyte) or 16KB, one Page is paged into multiple DMA transfers, so that there will be some DMA data errors and some DMA data errors, so that the whole data transfer process performed between the host computer and the flash memory can be optimized to perform random insertion of error correction data for error correction on a Page with flash memory bit errors, and others can be omitted, thereby saving the transfer time of data transfer performed between the host computer and the flash memory as much as possible, and minimizing the data processing speed loss of the flash memory.

S102: and in the process of reading the transmitted data from the buffer into the buffer space inside the flash memory controller, the flash memory controller detects whether the transmitted data has bit errors or not to obtain a detection result.

Wherein, in the process of reading the transmitted data from the buffer into the buffer space inside the flash memory controller, detecting whether the transmitted data has a bit error by the flash memory controller to obtain a detection result, which may include:

in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold, obtains the detection result that the transmitted data is not in the range in which the errors can be safely corrected when the transmitted data is detected to be not less than the preset error threshold, and obtains the detection result that the transmitted data is in the range in which the errors can be safely corrected when the transmitted data is detected to be less than the preset error threshold.

S103: and correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data.

Wherein, the performing error correction on the bit error data associated with the detection result according to the obtained detection result to obtain correct data may include:

according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the error can be safely corrected, the data in the range in which the error can be safely corrected is not corrected, and when the detection result is that the transmitted data is not in the range in which the error can be safely corrected, the error correction is performed on the bit error data to obtain correct data.

In this embodiment, when the flash memory performs the write-back command, data transmission is not required, but only a process from the storage unit > Register > storage unit. If the flash memory controller is allowed to intervene after the data reaches the Register, the data can be read from the Register to the Buffer inside the flash memory controller, and in this process, when the data passes through the bus of the flash memory controller, an error correction module inside the flash memory controller, such as an ECC (error correction Code) module, an LDPC (Low Density Parity Check Code) module, etc., can correct the Bit error that has occurred, so that the data in the Buffer inside the flash memory controller is correct data.

S104: the correct data is transferred to the buffer of the flash memory by the flash memory controller.

In this embodiment, the flash memory controller may intervene in the programming command to transmit the correct data to the Register, so that the data written into the new page is the corrected real original data, instead of the erroneous data in which the Bit error occurs, thereby avoiding the situation that the Bit error is amplified continuously during the continuous data transfer process.

It can be found that, in this embodiment, data transmission can be performed between the upper computer and the flash memory, and in the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller detects whether a bit error exists in the transmitted data to obtain a detection result, and can correct the bit error data associated with the detection result according to the obtained detection result to obtain correct data, and the flash memory controller can convey the correct data to the buffer of the flash memory, so that the situation that a flash memory bit error is amplified can be avoided.

Furthermore, in this embodiment, data transmission can be performed between the host computer and the flash memory through the buffer space inside the flash memory controller, which has the advantage of transferring data transmission between the host computer and the flash memory through the buffer space inside the flash memory controller, thereby achieving the purpose of preventing flash memory bit errors from being amplified.

Further, in this embodiment, in the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller may detect whether the transmitted data has a condition that the number of bit errors is not less than the preset error threshold, obtain a detection result that the transmitted data is not within the range in which the errors can be safely corrected when detecting that the number of bit errors is not less than the preset error threshold, and obtain a detection result that the transmitted data is within the range in which the errors can be safely corrected when detecting that the number of bit errors is less than the preset error threshold.

Further, in this embodiment, it is possible to perform error correction on the data within the range in which the error can be safely corrected based on the obtained detection result when the detection result is that the transmitted data is within the range in which the error can be safely corrected, and perform error correction on the bit error data to obtain correct data when the detection result is that the transmitted data is not within the range in which the error can be safely corrected, which is advantageous in that the process of returning to the buffer of the flash memory can be omitted because the data within the range in which the error can be safely corrected is not corrected, and the transmission time of the data within the range in which the error can be safely corrected can be saved.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating another embodiment of a method for preventing flash memory bit error amplification according to the present invention. In this embodiment, the method includes the steps of:

s201: and paging the data page needing data transmission between the upper computer and the flash memory into at least two DMA.

S202: and data transmission is carried out between the upper computer and the flash memory.

As described above in S101, further description is omitted here.

S203: and in the process of reading the transmitted data from the buffer into the buffer space inside the flash memory controller, the flash memory controller detects whether the transmitted data has bit errors or not to obtain a detection result.

As described above in S102, further description is omitted here.

S204: and correcting the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data.

As described above in S103, which is not described herein.

S205: the correct data is transferred to the buffer of the flash memory by the flash memory controller.

As described above in S104, and will not be described herein.

It can be found that, in this embodiment, the data page that needs to be subjected to data transmission between the upper computer and the flash memory can be paged into at least two DMAs, which has the advantage of being able to realize a subsequent mode that it is convenient to perform error correction by randomly inserting error correction data only in the page with flash memory bit errors in the at least two paged DMAs, and not to perform random inserting error correction data in the page without flash memory bit errors in the at least two paged DMAs, thereby being able to save the transmission time of data transmission between the upper computer and the flash memory as much as possible and minimizing the data processing speed loss of the flash memory.

The invention also provides a device for preventing the error amplification of the flash memory bit, which can avoid the situation that the error amplification of the flash memory bit occurs.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an apparatus for preventing flash bit error amplification according to an embodiment of the present invention. In this embodiment, the apparatus 30 for preventing error amplification of flash bits comprises a transmission module 31, a detection module 32, an error correction module 33, and a transmission module 34.

The transmission module 31 is used for data transmission between the upper computer and the flash memory.

The detecting module 32 is configured to detect whether a bit error exists in the transmitted data by the flash memory controller to obtain a detection result when the transmitted data is read out from the buffer into a buffer space inside the flash memory controller.

The error correction module 33 is configured to correct the error of the bit error data associated with the detection result according to the obtained detection result to obtain correct data.

The transfer module 34 is used for transferring the correct data to the buffer of the flash memory through the flash memory controller.

Optionally, the transmission module 31 may be specifically configured to:

and data transmission is carried out between the upper computer and the flash memory through the buffer area space inside the flash memory controller.

Optionally, the detection module 32 may be specifically configured to:

in the process that the transmitted data is read out from the buffer to the buffer space in the flash memory controller, the flash memory controller detects whether the transmitted data has the condition that the number of bit errors is not less than a preset error threshold value, when the transmitted data is detected to be not less than the preset error threshold value, the detection result that the transmitted data is not in the range that the errors can be safely corrected is obtained, and when the transmitted data is detected to be less than the preset error threshold value, the detection result that the transmitted data is in the range that the errors can be safely corrected is obtained.

Optionally, the error correction module 33 may be specifically configured to:

according to the obtained detection result, when the detection result is that the transmitted data is in the range in which the error can be safely corrected, the error correction is not performed on the data in the range in which the error can be safely corrected, and when the detection result is that the transmitted data is not in the range in which the error can be safely corrected, the error correction is performed on the bit error data to obtain correct data.

Referring to fig. 4, fig. 4 is a schematic structural diagram of another embodiment of the apparatus for preventing flash bit error amplification according to the present invention. Unlike the previous embodiment, the apparatus 40 for preventing flash bit error amplification in this embodiment further includes a paging module 41.

The paging module 41 is configured to page a data page requiring data transmission between the host computer and the flash memory into at least two DMAs.

Each unit module of the apparatus 30/40 for preventing flash memory bit error amplification can respectively execute the corresponding steps in the above method embodiments, and therefore, the detailed description of each unit module is omitted here, please refer to the description of the corresponding steps above.

The present invention further provides an apparatus for preventing error amplification of flash memory bits, as shown in fig. 5, including: at least one processor 51; and a memory 52 communicatively coupled to the at least one processor 51; the memory 52 stores instructions executable by the at least one processor 51, and the instructions are executed by the at least one processor 51 to enable the at least one processor 51 to perform the above method for preventing error amplification of flash bits.

Wherein the memory 52 and the processor 51 are coupled in a bus, which may comprise any number of interconnected buses and bridges, which couple one or more of the various circuits of the processor 51 and the memory 52 together. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 51 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 51.

The processor 51 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And the memory 52 may be used to store data used by the processor 51 in performing operations.

The present invention further provides a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.

It can be found that, in the above scheme, data transmission can be performed between the upper computer and the flash memory, and in the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller detects whether the transmitted data has a bit error to obtain a detection result, and can correct the bit error data associated with the detection result according to the obtained detection result to obtain correct data, and the flash memory controller can convey the correct data to the buffer of the flash memory, so that the situation that the flash memory bit error is amplified can be avoided.

Furthermore, the above scheme can transmit data between the upper computer and the flash memory through the buffer space inside the flash memory controller, so that the advantage of transferring data between the upper computer and the flash memory through the buffer space inside the flash memory controller can be realized, and the purpose of preventing flash memory bit errors from being amplified can be achieved.

Further, in the above scheme, during the process that the transmitted data is read out from the buffer to the buffer space inside the flash memory controller, the flash memory controller may detect whether the transmitted data has a condition that the number of bit errors is not less than the preset error threshold, obtain a detection result that the transmitted data is not within a range in which the errors can be safely corrected when detecting that the number of bit errors is not less than the preset error threshold, and obtain a detection result that the transmitted data is within a range in which the errors can be safely corrected when detecting that the number of bit errors is less than the preset error threshold.

Further, the above-mentioned solution may not perform error correction on the data within the range in which the error can be safely corrected when the detection result is that the transmitted data is within the range in which the error can be safely corrected, and may perform error correction on the bit error data to obtain correct data when the detection result is that the transmitted data is not within the range in which the error can be safely corrected.

Furthermore, the above scheme can divide the data page needing data transmission between the upper computer and the flash memory into at least two DMAs, which has the advantages of realizing the subsequent mode of conveniently performing error correction by randomly inserting error correction data only in the page with flash memory bit errors in the at least two DMAs divided into the pages, and not performing random insertion of error correction data in the page without flash memory bit errors in the at least two DMAs divided into the pages, thereby saving the transmission time of data transmission between the upper computer and the flash memory as much as possible and reducing the data processing speed loss of the flash memory to the minimum.

In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.