阅读说明：本技术 一种通信装置 (Communication device ) 是由 金玮 冀晋 于 2020-05-22 设计创作，主要内容包括：一种通信装置,包括：主控芯片,包括发送端；被控芯片,包括接收端,发送端与接收端之间通过差分信号线相耦接,差分信号线包括正端和负端；正端状态检测单元,耦接正端以检测正端的单端信号；负端状态检测单元,耦接负端以检测负端的单端信号；控制单元,分别与所述正端状态检测单元、负端状态检测单元和接收端耦接,所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端,其中,所述信号状态组合为所述正端的单端信号和负端的单端信号的信号状态组合。通过本发明方案,主控芯片和被控芯片之间无需边带信号或额外的低功耗电路既能唤醒或睡眠对端,利于降低器件成本和减小尺寸,且实现简单并能够通过信号状态的切换传递更多信息。(A communication device, comprising: the main control chip comprises a sending end; the controlled chip comprises a receiving end, the transmitting end is coupled with the receiving end through a differential signal line, and the differential signal line comprises a positive end and a negative end; the positive end state detection unit is coupled with the positive end to detect a single-ended signal of the positive end; the negative terminal state detection unit is coupled with the negative terminal to detect a single-ended signal of the negative terminal; and the control unit is respectively coupled with the positive end state detection unit, the negative end state detection unit and the receiving end, and awakens or sleeps the receiving end according to the detected signal state combination, wherein the signal state combination is the signal state combination of the single-ended signal of the positive end and the single-ended signal of the negative end. According to the scheme of the invention, the opposite end can be awakened or sleeped without a sideband signal or an additional low-power consumption circuit between the main control chip and the controlled chip, so that the cost of the device and the size are reduced, the realization is simple, and more information can be transmitted through switching of signal states.)

1. A communications apparatus, comprising:

the main control chip comprises a sending end;

the controlled chip comprises a receiving end, the transmitting end is coupled with the receiving end through a differential signal line, and the differential signal line comprises a positive end and a negative end;

a positive terminal state detection unit coupled to the positive terminal to detect a single-ended signal of the positive terminal;

a negative terminal state detection unit coupled to the negative terminal to detect a single-ended signal of the negative terminal;

and the control unit is respectively coupled with the positive end state detection unit, the negative end state detection unit and the receiving end, and awakens or sleeps the receiving end according to the detected signal state combination, wherein the signal state combination is the signal state combination of the single-ended signal of the positive end and the single-ended signal of the negative end.

2. The communication apparatus according to claim 1, wherein the signal states of the single-ended signal of the positive terminal and the single-ended signal of the negative terminal in the signal state combination for waking up or sleeping the receiving terminal are the same.

3. The apparatus according to claim 1 or 2, wherein the controlling unit combines waking up or sleeping the receiving end according to the detected signal states comprises:

when the signal state combination is 11, the control unit wakes up the receiving end, and when the signal state combination is 00, the control unit sleeps the receiving end; alternatively, the first and second electrodes may be,

and when the signal state combination is 00, the control unit wakes up the receiving end, and when the signal state combination is 11, the control unit sleeps the receiving end.

4. The communication apparatus according to claim 1, wherein the positive and negative terminal state detection units enter an inactive state after the receiving terminal is awakened.

5. The apparatus according to claim 4, wherein the positive and negative terminal state detecting units are kept in an operating state after the receiving terminal is put to sleep.

6. The communication apparatus according to claim 1 or 4, wherein the receiving end receives the signals of the positive terminal and the negative terminal respectively, and determines the start timing and the end timing of the present data transmission according to the signal status combination of the positive terminal and the negative terminal.

7. The communications apparatus as claimed in claim 6, wherein the determining, by the receiving end, the start timing and the end timing of the data transmission according to the signal status combination of the positive terminal and the negative terminal comprises:

and when the signal state combination of the positive terminal and the negative terminal is 10, the receiving terminal determines that the data transmission starts after a preset time length, and when the signal state combination of the positive terminal and the negative terminal is 01, the receiving terminal determines that the data transmission is finished.

8. The communication apparatus according to claim 1, wherein the swing amplitudes of the signals transmitted by the positive and negative terminals for waking up or sleeping the receiving terminal are larger than the swing amplitudes of the signals transmitted by the positive and negative terminals during data transmission.

9. The communication apparatus according to claim 1, wherein the positive side state detection unit includes a first comparator for detecting whether a single-ended signal of the positive side is 1 or 0; the negative terminal state detection unit includes a second comparator for detecting whether a single-ended signal of the negative terminal is 1 or 0.

10. The communication apparatus according to claim 1, wherein the main control chip further comprises:

a first control switch for switching the signal state of the positive terminal and/or the signal state of the negative terminal.

11. The communication device according to claim 1, wherein the controlled chip comprises a second control switch for switching the signal state when the positive terminal and/or the negative terminal reversely transmit;

the communication apparatus includes: the reverse positive end state detection unit is coupled with the positive end to detect a single-ended signal when the positive end reversely transmits; the reverse negative terminal state detection unit is coupled with the negative terminal to detect a single-ended signal when the negative terminal reversely transmits;

the transmitting end is coupled to the reverse positive end state detection unit and the reverse negative end state detection unit respectively to obtain a reverse signal state combination, wherein the reverse signal state combination is a signal state combination of a single-ended signal when the positive end reversely transmits and a single-ended signal when the negative end reversely transmits.

12. The communication apparatus according to claim 11, wherein during reverse transmission, the positive terminal state detection unit monitors the signal state of the positive terminal and/or the negative terminal state detection unit monitors the signal state of the negative terminal to determine whether there is a state conflict on the differential signal lines.

13. The communication device according to claim 1, wherein the master chip is an application processor and the controlled chip is a modem.

14. The communications device of claim 13, further comprising:

a shared memory module coupled to and directly accessible by the application processor, the modem coupled to the application processor via the differential signal line and indirectly accessible to the shared memory via the application processor.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a communications apparatus.

Background

In order to meet the diversified demands of users, communication devices such as mobile phones and the like gradually expand diversified functions such as camera shooting and games in addition to the function of realizing communication. These applications may be controlled and implemented based on independent systems.

Therefore, for a communication device capable of implementing multiple applications, there are usually at least two integrated circuit chips, one of which is a modem (modem) for implementing a cellular communication function, which can be understood as a communication system; the other chip is an Application Processor (AP) for implementing functions such as shooting, displaying, 2D/3D engine, and may be understood as an Application processing system.

Generally, an application processor is used as a Master chip (Master IC) to control a Slave IC (Slave IC) modem, and a serial bus coupling is adopted between the Master IC and the Slave IC for data transmission. For example, the prior art typically employs differential signal lines to connect the application processor and the modem to achieve efficient data interaction.

However, in the existing protocols, for example, a Low Power (LP) mode (LP mode) of a Mobile Industry Processor Interface (MIPI) is used to wake up or sleep an opposite receiving end by transmitting a High voltage different from a swing amplitude of a High Speed (HS) signal as a control word. This requires additional provision of an LP circuit in the communication device or implementation by a side band (side band) signal.

Disclosure of Invention

The technical problem to be solved by the invention is to provide an improved communication device, so that the opposite end can be woken up or sleeped without a sideband signal or an additional low-power-consumption circuit between a main control chip and a controlled chip.

To solve the above technical problem, an embodiment of the present invention provides a communication apparatus, including: the main control chip comprises a sending end; the controlled chip comprises a receiving end, the transmitting end is coupled with the receiving end through a differential signal line, and the differential signal line comprises a positive end and a negative end; a positive terminal state detection unit coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit coupled to the negative terminal to detect a single-ended signal of the negative terminal; and the control unit is respectively coupled with the positive end state detection unit, the negative end state detection unit and the receiving end, and awakens or sleeps the receiving end according to the detected signal state combination, wherein the signal state combination is the signal state combination of the single-ended signal of the positive end and the single-ended signal of the negative end.

Optionally, in the signal state combination for waking up or sleeping the receiving end, the signal state of the single-ended signal of the positive end is the same as that of the single-ended signal of the negative end.

Optionally, the combining, waking up or sleeping the receiving end by the control unit according to the detected signal states includes: when the signal state combination is 11, the control unit wakes up the receiving end, and when the signal state combination is 00, the control unit sleeps the receiving end; or, when the signal state combination is 00, the control unit wakes up the receiving end, and when the signal state combination is 11, the control unit sleeps the receiving end.

Optionally, after the receiving end is awakened, the positive terminal state detection unit and the negative terminal state detection unit enter a non-working state.

Optionally, after the receiving end is put to sleep, the positive end state detection unit and the negative end state detection unit are kept in a working state.

Optionally, the receiving end receives the signals of the positive terminal and the negative terminal respectively, and determines the start timing and the end timing of the data transmission according to the signal state combination of the positive terminal and the negative terminal.

Optionally, the determining, by the receiving end, the start timing and the end timing of the data transmission according to the signal state combination of the positive terminal and the negative terminal includes: and when the signal state combination of the positive terminal and the negative terminal is 10, the receiving terminal determines that the data transmission starts after a preset time length, and when the signal state combination of the positive terminal and the negative terminal is 01, the receiving terminal determines that the data transmission is finished.

Optionally, the swing amplitudes of the signals transmitted by the positive terminal and the negative terminal for waking up or sleeping the receiving terminal are greater than the swing amplitudes of the signals transmitted by the positive terminal and the negative terminal during data transmission.

Optionally, the positive end state detection unit includes a first comparator, and the first comparator is configured to detect whether a single-ended signal of the positive end is 1 or 0; the negative terminal state detection unit includes a second comparator for detecting whether a single-ended signal of the negative terminal is 1 or 0.

Optionally, the main control chip further includes: a first control switch for switching the signal state of the positive terminal and/or the signal state of the negative terminal.

Optionally, the controlled chip includes a second control switch for switching a signal state when the positive terminal and/or the negative terminal reversely transmit; the communication apparatus includes: the reverse positive end state detection unit is coupled with the positive end to detect a single-ended signal when the positive end reversely transmits; the reverse negative terminal state detection unit is coupled with the negative terminal to detect a single-ended signal when the negative terminal reversely transmits; the transmitting end is coupled to the reverse positive end state detection unit and the reverse negative end state detection unit respectively to obtain a reverse signal state combination, wherein the reverse signal state combination is a signal state combination of a single-ended signal when the positive end reversely transmits and a single-ended signal when the negative end reversely transmits.

Optionally, during reverse transmission, the positive terminal state detection unit monitors the signal state of the positive terminal, and/or the negative terminal state detection unit monitors the signal state of the negative terminal, so as to determine whether there is a state conflict on the differential signal lines.

Optionally, the master control chip is an application processor, and the controlled chip is a modem.

Optionally, the communication device further includes: a shared memory module coupled to and directly accessible by the application processor, the modem coupled to the application processor via the differential signal line and indirectly accessible to the shared memory via the application processor.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

an embodiment of the present invention provides a communication apparatus, including: the main control chip comprises a sending end; the controlled chip comprises a receiving end, the transmitting end is coupled with the receiving end through a differential signal line, and the differential signal line comprises a positive end and a negative end; a positive terminal state detection unit coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit coupled to the negative terminal to detect a single-ended signal of the negative terminal; and the control unit is respectively coupled with the positive end state detection unit, the negative end state detection unit and the receiving end, and awakens or sleeps the receiving end according to the detected signal state combination, wherein the signal state combination is the signal state combination of the single-ended signal of the positive end and the single-ended signal of the negative end.

Compared with the existing awakening/sleeping mechanism between the master chip and the slave chip, the communication device adopting the scheme of the embodiment can awaken or sleep the opposite terminal without a sideband signal or an additional low-power-consumption circuit between the master chip and the slave chip, is beneficial to reducing the cost of devices and the size, is simple to realize and can transmit more information through switching of signal states. Specifically, the edge deletion of the differential single-terminal voltage amplitude is used as a judgment sign for state switching. Furthermore, the embodiment controls the receiving end and the transmitting end according to a single end, so that more signal states can be obtained and more messages can be transmitted.

Further, in the signal state combination for waking up or sleeping the receiving end, the signal state of the single-ended signal of the positive end is the same as that of the single-ended signal of the negative end. Therefore, two signal states of double-end high/double-end low are added on the basis of the original differential signal. That is, the control word is transmitted by using two abnormal states of the high-speed differential signal line, so that the sleep or wake-up control of the receiving end is realized. Further, because of the peer-to-peer control implemented using the differentially driven abnormal state, little or no additional circuitry support is required within the communication device. Further, more information can be transferred by switching of the abnormal state.

Drawings

Fig. 1 is a schematic diagram of a first communication device according to an embodiment of the present invention;

fig. 2 is a schematic diagram of signal swing when the communication device transmits signals through differential signal lines according to the embodiment of the present invention;

fig. 3 is a schematic diagram of a second communication device according to an embodiment of the present invention.

Detailed Description

As described in the background, in the existing communication apparatus, an LP circuit needs to be additionally provided or wake-up or sleep control between a master chip and a slave chip is realized through a sideband (sideband) signal.

To solve the above technical problem, an embodiment of the present invention provides a communication apparatus, including: the main control chip comprises a sending end; the controlled chip comprises a receiving end, the transmitting end is coupled with the receiving end through a differential signal line, and the differential signal line comprises a positive end and a negative end; a positive terminal state detection unit coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit coupled to the negative terminal to detect a single-ended signal of the negative terminal; and the control unit is respectively coupled with the positive end state detection unit, the negative end state detection unit and the receiving end, and awakens or sleeps the receiving end according to the detected signal state combination, wherein the signal state combination is the signal state combination of the single-ended signal of the positive end and the single-ended signal of the negative end.

By adopting the communication device of the scheme of the embodiment, the opposite end can be awakened or sleeped without a sideband signal or an additional low-power circuit between the main control chip and the controlled chip, the cost of the device is reduced, the size is reduced, and the communication device is simple to realize and can transmit more information through switching of signal states. Specifically, the edge deletion of the differential single-terminal voltage amplitude is used as a judgment sign for state switching. Furthermore, the embodiment controls the receiving end and the transmitting end according to a single end, so that more signal states can be obtained and more messages can be transmitted.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a schematic diagram of a first communication device according to an embodiment of the present invention.

The communication device can be a user equipment such as a mobile phone.

Specifically, referring to fig. 1, the communication apparatus 1 according to the present embodiment may include: the main control chip 11, the main control chip 11 may include a transmitting end 111. For example, the main control chip 11 may be an application processor.

Further, the communication apparatus 1 may further include a controlled chip 12, and the controlled chip 12 may include a receiving end 121. For example, the controlled chip 12 may be a modem.

Further, the master chip 11 and the slave chip 12 may be coupled to communicate via a serial bus.

In one implementation, the transmitter 111 and the receiver 121 are coupled by a differential signal line 13, and the differential signal line 13 may include a positive terminal Vp and a negative terminal Vn. For example, the initiator 111 may be a high speed initiator, such as a D-bus initiator; the receiver 121 may be a high speed receiver, such as a D-bus receiver.

The master control chip 11 and the controlled chip 12 communicate with each other through the differential signal line 13. For example, a high-speed differential signal is transmitted between the master chip 11 and the controlled chip 12 through the differential signal line 13 to realize data transmission.

In one implementation, with continued reference to fig. 1, the communication device 1 may further include: the positive terminal state detecting unit 122 is coupled to the positive terminal Vp to detect a single-ended signal of the positive terminal Vp.

For example, the positive terminal state detecting unit 122 may include a first comparator 124, and the first comparator 124 is used for detecting whether the single-ended signal of the positive terminal Vp is 1 or 0. That is, whether the single-ended signal of the positive terminal Vp is high or low is detected. In this embodiment, 1 represents high level, and 0 represents low level

Further, the positive terminal state detecting unit 122 may be disposed on the controlled chip 12 side.

In one implementation, with continued reference to fig. 1, the communication device 1 may further include: the negative terminal state detecting unit 123 is coupled to the negative terminal Vn to detect a single-ended signal of the negative terminal Vn.

For example, the negative terminal state detection unit 123 may include a second comparator 125, and the second comparator 125 is configured to detect whether the single-ended signal of the negative terminal Vn is 1 or 0. That is, whether the single-ended signal of the negative terminal Vn is high or low is detected.

Further, the negative terminal state detection unit 123 may be disposed on the controlled chip 12 side.

In one implementation, with continued reference to fig. 1, the communication device 1 may further include: a control unit 126 coupled to the positive terminal state detection unit 122, the negative terminal state detection unit 123 and the receiving terminal 121, respectively, where the control unit 126 may wake up or sleep the receiving terminal 121 according to a detected signal state combination, where the signal state combination is a signal state combination of the single-ended signal of the positive terminal Vp and the single-ended signal of the negative terminal Vn. Further, the signal state combinations have four cases, that is, the single-ended signal of the positive terminal Vp can be in a high state or a low state, and the single-ended signal of the negative terminal Vn can be in a high state or a low state, and the combination of the two cases is four cases.

Thus, the communication device 1 according to the present embodiment uses the edge deletion of the differential single-terminal voltage amplitude as the determination flag for the state switching. Specifically, both the transmitting end and the receiving end (i.e., the transmitting end 111 and the receiving end 121) are controlled by a single end, and the controlled chip 12 is provided with a positive end state detection unit 122 and a negative end state detection unit 123 for detecting the single end signal states of the positive end Vp and the negative end Vn of the differential signal line 13, respectively. Further, in the case of single ended control, more signal states can be combined, making it possible to transfer more messages.

In one implementation, the control unit 126 may be a physical module or control logic at a software level.

Further, the control unit 126 and the receiving end 121 may be integrated, and the positive end state detection unit 122 and the negative end state detection unit 123 directly transmit the detection result to the receiving end 121, so as to directly wake up or sleep the receiving end 121 when the signal states are combined into the wake-up or sleep control word. Alternatively, the two may be two separate modules that are separated.

In one implementation, in the combination of signal states for waking up or sleeping the receiving end 121, the signal state of the single-ended signal of the positive terminal Vp is the same as that of the single-ended signal of the negative terminal Vn.

Specifically, since the positive terminal Vp and the negative terminal Vn of the differential signal line 13 are controlled according to two single ends independent from each other at this time, the signals transmitted on the differential signal line 13 no longer have to be limited to differential signals. That is, the signals transmitted by the positive terminal Vp and the negative terminal Vn, respectively, no longer have to be in phase opposition.

Therefore, two signal states of double-end high/double-end low are added on the basis of the original differential signal. That is, the control word is transmitted by using the two abnormal states of the high-speed differential signal line 13, so as to realize the sleep or wake-up control of the receiving terminal 121. Further, since the opposite-end control is realized by using the abnormal state of the differential drive (driver), no or only a very small amount of additional circuit support is required within the communication apparatus 1. Further, more information can be transferred by switching of the abnormal state.

In one embodiment, the control unit 126 may wake up the receiving end 121 when the signal status combination is 11 (i.e., two high, positive and negative terminals are both high, or two high for short), and the control unit 126 may sleep the receiving end 121 when the signal status combination is 00 (i.e., two low, positive and negative terminals are both low, or two low for short).

In a variation, when the signal state combination is 00, the control unit 126 wakes up the receiving end 121, and when the signal state combination is 11, the control unit 126 sleeps the receiving end 121.

In one embodiment, the receiving end 121 can receive the signals of the positive end Vp and the negative end Vn respectively, and determine the start timing and the end timing of the data transmission according to the signal state combination of the positive end Vp and the negative end Vn.

Specifically, the signal transmitted by the differential signal line 13 received by the receiving end 121 may be a differential signal in the conventional sense, i.e., the phases of the signals transmitted on the positive terminal Vp and the negative terminal Vn have a phase difference of 180 °. The receiving end 121 determines the start timing and the end timing of the data transmission according to the received signal state combination.

For example, when the signal states of the positive terminal Vp and the negative terminal Vn are combined to be 10, the receiving end 121 may determine that the data transmission is to be started after a preset time period, and when the signal states of the positive terminal Vp and the negative terminal Vn are combined to be 01, the receiving end 121 determines that the data transmission is finished.

The preset duration may be a value configured by the protocol, such as 200 ns.

TABLE 1

In a typical application scenario, referring to fig. 1 and table 1, assuming that the controlled chip 12 (or at least the receiving end 121 of the controlled chip 12) is initially in a sleep state (also referred to as a sleep state), the master chip 11 needs to transmit data to the controlled chip 12.

First, the transmitting terminal 111 of the main control chip 11 pulls the signal states of both the positive terminal Vp and the negative terminal Vn of the differential signal line 13 from low level to high level.

The positive terminal state detecting unit 122 and the negative terminal state detecting unit 123 at the controlled chip 12 side respectively detect that the single-ended signals of the positive terminal Vp and the negative terminal Vn are both changed from 0 to 1, and further determine that the receiving terminal 121 needs to be woken up. The positive end state detection unit 122 and the negative end state detection unit 123 respectively transmit the detection results to the control unit 126.

In response to the received signal status of the positive terminal Vp and the signal status of the negative terminal Vn being both 1, the control unit 126 wakes up the receiving terminal 121. Specifically, only local modules in the receiving end 121 may be woken up, such as modules with long start-up time and slow response in the receiving end 121.

Further, after the receiving end 121 is awakened, the positive end state detection unit 122 and the negative end state detection unit 123 enter a non-operating state to save power consumption. Thereafter, the signal transmitted on the differential signal line 13 continues to be received by the receiving terminal 121.

Further, after sending the double-ended high signal, the main control chip 11 may pull down the signal state of the negative terminal Vn from a high level to a low level. Accordingly, the receiving end 121 detects that the combination of the signal states of the positive end Vp and the negative end Vn is 10, and determines that the DiFP signal is received. The DiFP signal is used for indicating that data transmission is started after a preset time length since the signal is received.

In response to receiving the DiFP signal, the receiving end 121 self-checks and makes a receiving preparation, and wakes up all internal modules.

Further, after the preset duration, the main control chip 11 performs normal data transmission to the controlled chip 12 through the differential signal line 13.

After the data transmission is completed, the transmitting end 111 of the main control chip 11 switches the signal state of the positive terminal Vp to 0 and switches the signal state of the negative terminal Vn to 1. Accordingly, the receiving end 121 detects that the signal states of the positive terminal Vp and the negative terminal Vn are combined to be 01, and determines that the din signal is received. Wherein, the din n signal is used to indicate that the data transmission is finished.

In response to receiving the din signal, the receiving end 121 determines that the data transmission is completed, and wakes up the positive terminal state detecting unit 122 and the negative terminal state detecting unit 123.

Further, the main control chip 11 switches the signal state of the negative terminal Vn from high level to low level. Accordingly, the single-ended signals of the positive terminal Vp and the negative terminal Vn detected by the positive terminal state detecting unit 122 and the negative terminal state detecting unit 123 are both 0, and it is determined that the sleep receiving terminal 121 is required. The positive end state detection unit 122 and the negative end state detection unit 123 respectively transmit the detection results to the control unit 126.

In response to both the received signal state of the positive terminal Vp and the signal state of the negative terminal Vn being 0, the control unit 126 sleeps the receiving terminal 121.

Further, after the receiving end 121 is put to sleep, the positive end state detecting unit 122 and the negative end state detecting unit 123 remain in an operating state, and then find the next wake-up signal of the transmitting end 111.

The application scenario can realize the fusion of a wake-up/sleep mechanism and a burst mode.

In one implementation, in the data transmission phase, a high-speed signal may be transmitted between the transmitting end 111 and the receiving end 121 through the differential signal line 13; in the wake/sleep state switching stage, the signals transmitted by the transmitter 111 to the positive side state detection unit 122 and the negative side state detection unit 123 may be low speed signals.

For example, referring to fig. 2, the Swing amplitude (Signal Swing) of the signals transmitted by the positive terminal Vp and the negative terminal Vn for waking up or sleeping the receiving terminal 121 is greater than the Swing amplitude of the signals transmitted by the positive terminal Vp and the negative terminal Vn during data transmission.

Therefore, the first comparator 124 and the second comparator 125 can distinguish different signal states by only comparing the voltage values of the single-ended signals.

In a specific implementation, the main control chip 11 may include: a first control switch (not shown) for switching the signal state of the positive terminal Vp and/or the signal state of the negative terminal Vn.

For example, the first control switch can switch the signal states of the positive terminal Vp and the negative terminal Vn simultaneously.

For another example, the number of the first control switches may be two and used for switching the signal states of the positive terminal Vp and the negative terminal Vn, respectively.

In one embodiment, the controlled chip 12 may include a second control switch (not shown) for switching the signal state when the positive terminal Vp and/or the negative terminal Vn transmit in reverse. The reverse transmission refers to data transmission from the controlled chip 12 to the master chip 11. At this time, the single-ended signal state switching of the positive terminal Vp/or the negative terminal Vn is realized by the second control switch, similarly to the first control switch.

Further, the communication apparatus 1 may include: a reverse positive terminal status detecting unit (not shown) coupled to the positive terminal Vp for detecting a single-ended signal when the positive terminal Vp is in reverse transmission; a reverse negative terminal state detection unit (not shown) coupled to the negative terminal Vn for detecting a single-ended signal when the negative terminal Vn transmits in a reverse direction. Wherein, the aforementioned description about the positive terminal state detecting unit 122 can be referred to for the specific structure of the reverse positive terminal state detecting unit, and the aforementioned description about the negative terminal state detecting unit 123 can be referred to for the specific structure of the reverse negative terminal state detecting unit.

Further, the transmitting end 111 is coupled to the reverse positive end state detection unit and the reverse negative end state detection unit respectively to obtain a reverse signal state combination, where the reverse signal state combination is a signal state combination of a single-ended signal when the positive end Vp reversely transmits and a single-ended signal when the negative end Vn reversely transmits.

Further, different reverse signal state combinations may be used to convey different messages.

For example, the inverse signal state combinations include: 00. 01, 10 and 11. I.e. double ended low level, positive side low level negative side high level, positive side high level negative side low level and double ended high level.

Thus, by adding a simple switch (switch) to the receiving terminal 121 and a comparator to the transmitting terminal 111, reverse signal interaction can be realized.

In one implementation, during reverse transmission, the positive terminal state detection unit 122 may monitor the signal state of the positive terminal Vp and/or the negative terminal state detection unit 123 may monitor the signal state of the negative terminal Vn to determine whether there is a state conflict on the differential signal line 13.

For example, when the first comparator 124 and/or the second comparator 125 of the receiving end 121 detects that the differential signal line 13 is not pulling up the signal state of the positive terminal Vp or the signal state of the negative terminal Vn according to its own request, or when the differential signal line 13 fails to pull down the on-line state according to the request of the receiving end 121, it can be determined that the on-line state is in conflict. Thereby, reverse transmission collision detection may be achieved.

In one implementation, referring to fig. 3, the communication device 1 may further include: a shared memory module 14, the application processor (i.e. the master chip 11) is coupled with the shared memory module 14 and can directly access the shared memory module 14, and the modem (i.e. the slave chip 12) is coupled with the application processor through the differential signal line 13 and indirectly accesses the shared memory 14 through the application processor.

For example, the application processor executes the aforementioned wake mechanism (e.g., sending a two-terminal high control word) to wake up the modem, and the woken up modem accesses the shared memory module 14 through the application processor to read/write data. The read/write data is transmitted at high speed between the application processor and the modem via differential signal lines 13.

After the data read/write is completed, the application processor executes the sleep mechanism (e.g., sending dual-ended low control word) to put the modem into a sleep state.

By adopting the scheme of the embodiment, the main control chip 11 and the controlled chip 12 in the communication device 1 can wake up or sleep the opposite terminal without a sideband signal or an additional low-power circuit, so that the device cost and the size are reduced, the realization is simple, and more information can be transmitted through the switching of signal states.

The "logic high level" (i.e., high level) and the "logic low level" (i.e., low level) are relative logic levels in this embodiment. "logic high level" refers to a level range that can be recognized as a digital signal "1", and "logic low level" refers to a level range that can be recognized as a digital signal "0", and the specific level range thereof is not particularly limited.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.