阅读说明：本技术 存储元件和存储装置 (Memory element and memory device ) 是由 大场和博 野野口诚二 清宏彰 曾根威之 五十岚实 于 2018-12-06 设计创作，主要内容包括：根据本公开的实施例的存储元件设置有：第一电极；布置成与第一电极对置的第二电极；和存储层,设置在第一电极和第二电极之间,并且包括选自碲(Te)、硒(Se)和硫(S)中的至少一种硫族元素、过渡金属以及氧。存储层具有非线性的电阻特性以及整流特性,以使得当施加电压大于或等于预定阈值电压时获得低电阻状态,并且当施加电压是小于预定阈值电压的电压时获得高电阻状态。(A memory element according to an embodiment of the present disclosure is provided with: a first electrode; a second electrode arranged opposite to the first electrode; and a memory layer disposed between the first electrode and the second electrode and including at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), a transition metal, and oxygen. The memory layer has a non-linear resistance characteristic and a rectifying characteristic such that a low resistance state is obtained when an applied voltage is greater than or equal to a predetermined threshold voltage, and a high resistance state is obtained when the applied voltage is a voltage less than the predetermined threshold voltage.)

1. A memory element, comprising:

a first electrode;

a second electrode arranged opposite to the first electrode; and

a memory layer disposed between the first electrode and the second electrode and including one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), a transition metal, and oxygen, wherein

The memory layer has a nonlinear resistance characteristic, and is in a low resistance state by setting an applied voltage equal to or higher than a predetermined threshold voltage, and is in a high resistance state by setting the applied voltage lower than the predetermined threshold voltage, thereby having a rectifying characteristic.

2. The memory element according to claim 1, wherein the transition metal comprises one or more of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W).

3. The memory element according to claim 1, wherein the memory layer includes 55 atomic% or more of oxygen atoms.

4. The memory element according to claim 1, wherein the memory layer comprises tellurium oxide.

5. The memory element according to claim 1, wherein the memory layer comprises an oxide of the transition metal.

6. The memory element according to claim 1, wherein the memory layer further comprises one or more of boron (B), aluminum (Al), gallium (Ga), silicon (Si), and germanium (Ge).

7. The memory element according to claim 1, wherein a thickness between the first electrode and the second electrode is 20nm or less.

8. The memory element according to claim 1, wherein the memory layer records the low resistance state by applying a voltage between the first electrode and the second electrode to switch a resistance state above a predetermined voltage, and records the high resistance state by applying a voltage in a direction opposite to a direction of the predetermined voltage.

9. A memory device, comprising:

one or more first wirings extending in one direction;

one or more second wirings extending in another direction and intersecting the first wirings; and

one or more memory elements arranged at intersections of the first wiring and the second wiring,

the memory element comprises

A first electrode for forming a first electrode layer on a substrate,

a second electrode arranged opposite to the first electrode, an

A memory layer disposed between the first electrode and the second electrode and including one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), a transition metal, and oxygen, wherein

The memory layer has a nonlinear resistance characteristic, and is in a low resistance state by setting an applied voltage equal to or higher than a predetermined threshold voltage, and is in a high resistance state by setting the applied voltage lower than the predetermined threshold voltage, thereby having a rectifying characteristic.

Technical Field

The present disclosure relates to: a memory element including a chalcogenide layer between electrodes; and a memory device including the memory element.

Background

In recent years, it has been demanded to increase the capacity of a data storage nonvolatile memory represented by a resistance change type memory such as a ReRAM (resistance random access memory) (registered trademark) or a PRAM (phase change random access memory) (registered trademark). To solve this problem, for example, patent document 1 discloses a cross-point type memory device (memory cell array) in which memory cells are arranged at respective intersections (cross points) of crossing wirings. The memory cell has the following configuration: in which the memory element and the cell selection switching element are stacked on each other, for example, with an intermediate electrode therebetween.

CITATION LIST

Patent document

Patent document 1: international publication No. WO2016/158429

Disclosure of Invention

Meanwhile, higher capacity is further demanded in the cross-point memory cell array.

It is desirable to provide a memory element and a memory device that enable higher capacity.

A memory element according to one embodiment of the present disclosure includes a first electrode, a second electrode, and a memory layer. The second electrode is arranged opposite to the first electrode. The memory layer is disposed between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), a transition metal, and oxygen. The memory layer has a nonlinear resistance characteristic, and is in a low resistance state by setting an applied voltage equal to or higher than a predetermined threshold voltage, and is in a high resistance state by setting the applied voltage lower than the predetermined threshold voltage, thereby having a rectifying characteristic.

A memory device according to one embodiment of the present disclosure includes one or more first wirings, one or more second wirings, and one or more memory elements according to the above-described embodiments of the present disclosure. One or more first wirings extend in one direction. One or more second wirings extend in another direction and intersect the first wirings. One or more memory elements are arranged at intersections of the first wiring and the second wiring.

In each of the memory element according to the embodiment of the present disclosure and the memory device according to the embodiment of the present disclosure, the memory layer is provided between the first electrode and the second electrode. The storage layer includes: one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S); a transition metal; and oxygen. This makes it possible to provide a memory element having an element selection function.

According to each of the memory element according to the embodiment of the present disclosure and the memory device according to the embodiment of the present disclosure, the memory layer includes: one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S); a transition metal; and oxygen. This adds an element selection function to the storage layer. Therefore, fine processing becomes easier compared to a typical cross-point type memory device. This makes it possible to achieve higher capacity.

It is noted that the above effects are not necessarily limiting, and any of the effects described herein may be provided.

Drawings

Fig. 1 is a schematic cross-sectional view of an example of a configuration of a memory element according to one embodiment of the present disclosure.

Fig. 2 is a diagram showing an example of a schematic configuration of a memory cell array according to one embodiment of the present disclosure.

Fig. 3 is a diagram showing an example of a schematic configuration of a typical memory cell array.

Fig. 4 is a schematic cross-sectional view of a configuration of a memory cell in the memory cell array shown in fig. 3.

Fig. 5 is a schematic diagram explaining aspect ratios in the memory cell array shown in fig. 3.

Fig. 6 is a graph showing write current dependency of a switching operation in the memory element shown in fig. 1 at the time of high current writing.

Fig. 7 is a diagram showing write current dependency of a switching operation in the memory element shown in fig. 1 at the time of medium current writing.

Fig. 8 is a graph showing the write current dependency of the switching operation in the memory element shown in fig. 1 at the time of low current writing.

Fig. 9 is a graph showing the write current dependency of a switching operation in a typical memory element at the time of high-current writing.

Fig. 10 is a graph showing the write current dependency of a switching operation in a typical memory element at the time of medium current writing.

Fig. 11 is a graph showing the write current dependency of a switching operation in a typical memory element at the time of low-current writing.

Fig. 12 is a schematic diagram explaining aspect ratios in the memory cell array shown in fig. 2.

Fig. 13 is a diagram showing an example of a schematic configuration of a memory cell array according to a modified example of the present disclosure.

Fig. 14 is a diagram showing another example of a schematic configuration of a memory cell array according to a modified example of the present disclosure.

Fig. 15 is a diagram showing still another example of a schematic configuration of a memory cell array according to a modified example of the present disclosure.

Fig. 16 is a diagram showing still another example of a schematic configuration of a memory cell array according to a modified example of the present disclosure.

Fig. 17 is a graph showing the IV characteristic of example 1.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following description is one specific example of the present disclosure, and the present disclosure should not be limited to the following embodiments. Further, the present disclosure is not limited to the positions, sizes, size ratios, and the like of the respective elements shown in each drawing. It should be noted that the description is given in the following order.