阅读说明：本技术 一种通信方法、通信控制装置及i2c总线系统 (Communication method, communication control device and I2C bus system ) 是由 蒋磊 于泽洋 于 2020-04-17 设计创作，主要内容包括：本发明公开一种通信方法、通信控制装置及I2C总线系统,涉及总线通信技术领域,以解决从机地址引脚多所导致的从机地址修改效率低,应用场景有限的问题。所述通信方法包括：所述从机接收主机发送的寻址编码；所述从机响应寻址编码,确定每个地址引脚电连接的参考引脚的类型的情况下,根据m个地址引脚电连接的参考引脚的类型配置从机地址编码的低2m位；根据寻址编码的低2m位和从机地址编码的低2m位向主机发送链接信号。主机用于根据链接信号确定是否与所述从机建立通信。所述通信控制装置包括上述技术方案所提的通信方法。本发明提供的通信方法用于减少从机地址引脚的数量,提高从机地址的修改效率,增加其应用场景。(The invention discloses a communication method, a communication control device and an I2C bus system, relates to the technical field of bus communication, and aims to solve the problems of low slave address modification efficiency and limited application scenes caused by a plurality of slave address pins. The communication method comprises the following steps: the slave machine receives an addressing code sent by the host machine; the slave responds to the addressing code, and configures the low 2m bits of the slave address code according to the types of the reference pins electrically connected with the m address pins under the condition of determining the types of the reference pins electrically connected with each address pin; and sending a link signal to the host according to the lower 2m bits of the addressing code and the lower 2m bits of the slave address code. The master is used for determining whether to establish communication with the slave according to the link signal. The communication control device comprises the communication method provided by the technical scheme. The communication method provided by the invention is used for reducing the number of slave machine address pins, improving the modification efficiency of slave machine addresses and increasing the application scenes of the slave machine addresses.)

1. A communication method is applied to an I2C bus system with a host and a plurality of slaves, wherein each slave is provided with m address pins and n reference pins, m is less than or equal to n, m and n are integers, each address pin is electrically connected with the corresponding reference pin, and the reference pins are used for providing assignment codes for the corresponding address pins; the communication method comprises the following steps:

the slave machine receives an addressing code sent by the host machine;

the slave computer responds to the addressing code, and configures the low 2m bits of the slave computer address code according to the types of the reference pins electrically connected with the m address pins under the condition of determining the type of the reference pin electrically connected with each address pin;

sending a link signal to the host according to the low 2m bits of the addressing code and the low 2m bits of the slave address code; the master is used for determining whether to establish communication with the slave according to the link signal.

2. The communication method according to claim 1, wherein the determining the type of the reference pin to which each of the address pins is electrically connected comprises:

determining the type of a reference pin corresponding to each address pin according to the XOR operation result under the condition that the XOR operation result of the assignment code of each address pin and the assignment code of the reference pin is constantly 0;

and configuring the address of the corresponding address pin according to the type of the reference pin corresponding to each address pin, and determining the low 2m bits of the slave address code according to the addresses of m address pins.

3. The communication method according to claim 2, wherein the determining the type of the reference pin to which each of the address pins is electrically connected comprises:

and under the condition that the result of the XOR operation of the assignment codes of the address pins and the assignment code of one reference pin is larger than 0, carrying out the XOR operation on the assignment codes of the address pins and the assignment codes of the other reference pin.

4. The communication method according to claim 1, wherein the sending a link signal to the master according to the lower 2m bits of the addressing code and the lower 2m bits of the slave address code comprises:

sending a link success signal to the host under the condition that the low 2m bit of the slave address code is determined to be consistent with the low 2m bit data of the addressing code;

and under the condition that the lower 2m bits of the slave address code are different from the lower 2m bits of the addressing code, sending a link failure signal to the host.

5. The communication method according to claim 1, wherein m is 1 or 2, n is 4.

6. The communication method according to any of claims 1-5, wherein the n reference pins comprise a clock pin, a data pin, a ground pin, and a power supply voltage.

7. A communication control device is applied to an I2C bus system with a host and a plurality of slaves, wherein each slave is provided with m address pins and n reference pins, m is less than or equal to n, m and n are integers, each address pin is electrically connected with the corresponding reference pin, and the reference pins are used for providing assignment codes for the corresponding address pins; the communication control apparatus includes: a processor and a communication interface coupled to the processor;

the processor is adapted to run a computer program or instructions to implement the communication method according to any of claims 1-6.

8. An I2C bus system, comprising:

a host;

a plurality of slaves in communication with the master; each slave is used for executing the communication method of any one of claims 1-6; each slave has m address pins and n reference pins, m is less than or equal to n, m and n are integers, each address pin is electrically connected with the corresponding reference pin, and the reference pins are used for providing assignment codes for the corresponding address pins.

9. A computer storage medium having stored therein instructions that, when executed, implement the communication method of any one of claims 1-6.

10. A chip comprising a processor and a communication interface coupled to the processor; the processor is adapted to run a computer program or instructions to implement the communication method according to any of claims 1-6.

Technical Field

The present invention relates to the field of bus communication technologies, and in particular, to a communication method, a communication control apparatus, and an I2C bus system.

Background

The I2C bus is an abbreviation of Inter-Integrated Circuit and is named as "eye-squared center" or "eye-two-cee", is a standard of bidirectional, two-wire, serial and multi-master control interfaces, has a bus arbitration mechanism, and is suitable for short-distance and irregular data communication between devices. In the standard I2C bus protocol, the physical layer is composed of two bi-directional serial lines including a data line SDA and a clock line SCL. Typically, the I2C communication system is composed of a master and a single or multiple slaves. Each slave typically has a unique address that can be used to enable communication between that slave and the master.

In the conventional method, the address of each slave is determined by its address pin and corresponds one-to-one to the addressing code sent by the host. Fig. 1 is a schematic diagram of a conventional slave device for mounting 16 different addresses on a bus. As shown in FIG. 1, to mount 16 slaves on a bus, each slave requires 4 address pins A₃-A₀At this time, 7-bit addressing code D sent by the host on SDA₆-D₀Middle high three-digit code word D₆-D₄Fixed, low four-bit D₃-D₀For finding the slave responding to the corresponding address. Due to the limitation of the number of pins and the pin spacing in the traditional method, the modification efficiency of slave addresses in the traditional method is low, and the application scenarios are limited.

Disclosure of Invention

The invention aims to provide a communication method, a communication control device and an I2C bus system, which are used for reducing the number of slave address pins, improving the modification efficiency of slave addresses and increasing the application scenes of the slave addresses.

In order to achieve the above object, the present invention provides a communication method, applied to an I2C bus system having a master and a plurality of slaves, each slave having m address pins and n reference pins, where m is an integer, each address pin is electrically connected to a corresponding reference pin, and the reference pins are used for providing assignment codes to the corresponding address pins; the communication method comprises the following steps:

the slave machine receives an addressing code sent by the host machine;

the slave computer responds to the addressing code, and configures the low 2m bits of the slave computer address code according to the types of the reference pins electrically connected with the m address pins under the condition of determining the type of the reference pin electrically connected with each address pin;

sending a link signal to the host according to the low 2m bits of the addressing code and the low 2m bits of the slave address code; the master is used for determining whether to establish communication with the slave according to the link signal.

Compared with the prior art, in the communication method provided by the invention, under the condition that the slave can respond to the addressing code sent by the host and determine the type of the reference pin electrically connected with each address pin, the slave can configure the lower 2m bits of the slave address code according to the types of the reference pins electrically connected with m address pins. Therefore, when the communication method provided by the invention determines the slave address code, the data bit of the slave address code which can be configured by using the m address pins is at least more than 2m bits. Therefore, the communication method of the invention can configure the slave address code with more data bits under the condition of less address pins, so that more slaves can be loaded on the master under the condition of less slave address pins. Compared with the slave addresses in the prior art, the slave addresses of the invention are fewer under the condition of carrying the same number of slaves, so the efficiency is higher when the address pins are modified. And a fixed distance is required between every two adjacent address pins, so that the area of the slave device is larger as the number of the address pins is larger, and part of the slave devices cannot be used in equipment with requirements on volume, thereby causing the application scene of the slave device to be limited. Therefore, the application scene of the slave device can be expanded due to the reduction of the address pins.

The invention also provides a communication control device, which is applied to an I2C bus system with a host and a plurality of slaves, wherein each slave is provided with m address pins and n reference pins, m is an integer, each address pin is electrically connected with the corresponding reference pin, and the reference pins are used for providing assignment codes for the corresponding address pins; the communication control apparatus includes: a processor and a communication interface coupled to the processor;

the processor is used for running a computer program or instructions to implement the above communication method.

Compared with the prior art, the beneficial effects of the communication control device provided by the invention are the same as those of the communication method in the technical scheme, and are not repeated herein.

The present invention also provides an I2C bus system, comprising:

a host;

a plurality of slaves in communication with the master; each slave is used for executing the communication method of any one of claims 1-6; each slave has m address pins and n reference pins, m is less than or equal to n, m and n are integers, each address pin is electrically connected with the corresponding reference pin, and the reference pins are used for providing assignment codes for the corresponding address pins.

Compared with the prior art, the beneficial effects of the I2C bus system provided by the invention are the same as those of the communication method described in the above technical scheme, and are not described herein again.

The invention also provides a computer storage medium, wherein the computer storage medium stores instructions, and when the instructions are executed, the communication method of the technical scheme is realized.

Compared with the prior art, the beneficial effects of the computer storage medium provided by the invention are the same as the beneficial effects of the communication method in the technical scheme, and the details are not repeated here.

The invention also provides a chip, which comprises a processor and a communication interface coupled with the processor; the processor is used for running a computer program or instructions to implement the communication method of the above technical scheme.

Compared with the prior art, the beneficial effects of the chip provided by the invention are the same as those of the communication method in the technical scheme, and the details are not repeated here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a slave device implementing 16 different addresses for I2C communication in the prior art;

FIG. 2 is a schematic diagram of an I2C bus system according to an embodiment of the present invention;

fig. 3 is a flow chart of a first implementation of a communication method in an embodiment of the invention;

FIG. 4 is a flow chart of a second implementation of a communication method in an embodiment of the invention;

fig. 5 is a flow chart three of the implementation of the communication method in the embodiment of the present invention;

fig. 6 is a flow chart of a fourth implementation of the communication method in an embodiment of the invention;

fig. 7 is a flow chart of an implementation of a communication method in an embodiment of the invention;

FIG. 8 is a schematic diagram of 4 slaves on an I2C bus according to an embodiment of the present invention;

FIG. 9 is a flowchart of an implementation of loading 4 slaves on an I2C bus according to an embodiment of the present invention;

FIG. 10 is a flowchart of an implementation of loading 16 slaves on an I2C bus according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a communication control apparatus according to an embodiment of the present invention;

fig. 12 is a schematic hardware configuration diagram of a communication control apparatus according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Before describing the embodiments of the present invention, the related terms related to the embodiments of the present invention are first explained as follows:

the I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips. It requires only two wires to transfer information between devices connected to the bus.

The SCL is a clock line and transmits a clock signal sent by the master control to control the transmission of data. The rising edge inputs data into each EEPROM device; the falling edge drives the EEPROM device to output data. (edge triggered)

The SDA is a data line and performs bidirectional transfer between the CPU and the controlled IC and between the ICs.

Serial communication technology: the method refers to a communication mode that two communication parties carry out bitwise and follow the time sequence. In serial communication, data are transmitted in order according to bits, each bit of data occupies a fixed time length, information exchange among systems can be completed by using a few communication lines, and the method is particularly suitable for remote communication between computers and peripheral equipment. The serial communication is mostly used for serial transmission of data among inter-system communication (multi-master control system), inter-device communication (master control device and accessory device), and inter-device communication (master control CPU and functional chip), so as to realize transmission and sharing of data.

The host 100 refers to: the bus device for issuing the main instruction may be a single chip, or may be a microcontroller or a DSP, as long as the host 100 has a data processing capability.

The slave 200 refers to: the bus device for receiving the instruction may be a single chip, but is not limited thereto. The slave 200 may be other devices connected to the bus according to the application scenario of the single-bus system.

A flying wire (also called a jumper wire) refers to a method for directly connecting two nodes on a printed circuit board with wires due to design defects, test purposes or other design considerations.

Fig. 1 shows a schematic structural diagram of an I2C bus system provided by an embodiment of the present invention. The I2C bus system includes a master and 16 slaves of different addresses mounted on the master. As shown in fig. 1, the address of each slave is determined by its address pin and corresponds to the addressing code sent by the host one to one. The relationship of master and slave, send and receive is not constant over the bus, but depends on the direction of data transfer at the time.

In the standard I2C bus protocol, the physical layer is composed of two bi-directional serial lines including a data line SDA and a clock line SCL. In general, the I2C communication system is composed of a master and one or more slaves, where each slave generally has a unique address, and the address can be used for communication between the slave and the master by the following method:

(1) the host computer firstly initiates a communication request, and when SCL is at high level and SDA is changed from high level to low level, an initial signal is generated;

(2) the master selects the slave to be communicated, the clock is sent by SCL, and 7-bit addressing code (D) is sent by SDA line₆-D₀) And 1 bit read-write bit, and wait for the selected slave to respond, return an ACK signal: (Low level); if no matched slave responses, a NACK signal (high level) is returned;

(3) after the host receives the ACK signal, the host establishes communication with the corresponding slave and starts to read and write data;

(4) the host initiates a communication termination command, pulls the SDA high from the low level when the SCL is at the high level, and ends the communication.

As can be seen from the above, if the master wants to send data to the slave, the master addresses the slave first, then actively sends data to the slave, and finally the master terminates the data transfer. If the master is to receive data from a slave, the slave is addressed first by the master. Then the host receives the data sent by the slave, and finally the host terminates the receiving process. In this case, the host is responsible for generating the timing clock and terminating the data transfer.

If the conventional mode is used for realizing the mounting on the bus 2⁴The slaves with different addresses need 4 address pins A₃-A₀. At this time 7-bit addressing code D sent by the host on SDA₆-D₀Middle high three-digit code word D₆-D₄Fixed, low four-bit D_3-D₀For finding the slave responding to the corresponding address. Since the distance between the pins of the slave is required, the larger the number of pins, the larger the area of the slave is, which will limit the application of the slave device in some devices with area requirements. And because the number of the pins of each slave in the bus is large, the modification complexity is increased, so that the modification efficiency of the pins of the slave is low.

In view of the above, fig. 2 shows a schematic structural diagram of an I2C bus system provided by the embodiment of the present invention. As shown in fig. 2, the I2C bus system includes: a host 100; and a plurality of slaves 200 communicating with master 100; each slave 200 is for performing a communication method; each slave 200 is provided with m address pins and n reference pins, m is less than or equal to n, m and n are integers, and each address pin is electrically connected with the corresponding reference pin. The reference pins are used to provide assignment codes to the corresponding address pins. The reference pin includes a clock pin SCL, a data pin SDA, a ground pin GND and a power voltage VDD.

In practical applications, the slave 200 may be a chip provided with 1 address pin, and the slave 200 is electrically connected to the corresponding reference pin before accessing the bus circuit. It should be noted that the electrical connection here may be a wire connection, a flying lead connection, or when there is a special need, it may be directly connected inside the chip before packaging without providing a pin.

In addition, two or more address pins may be electrically connected to different reference pins, or may be electrically connected to the same reference pin. At this time, the slave 200 may configure a plurality of data bits of the slave address code by using the reference pin type electrically connected to each address pin, so as to reduce unnecessary address pins.

On this basis, the embodiment of the application provides a communication method. This communication method is applicable to the I2C bus system shown in fig. 2. In the I2C bus system, the steps executed by the master 100 may be executed by a chip applied to the master 100, the steps executed by the slave 200, or the steps executed by a chip applied to the slave 200. Fig. 3 illustrates a flowchart of a communication method provided in an embodiment of the present application. The communication method provided by the embodiment of the present invention is described below with the master 100 and the slave 200 as execution subjects.

As shown in fig. 3, the communication method includes:

step 110: the master 100 sends an addressing code to the slave 200 with m address pins. The addressing code may comprise a 7-bit addressing code (D)₆-D₀) And 1-bit read-write bits.

Step 120: the slave 200 receives the addressing code transmitted by the master 100. At this time, the slave 200 may receive the address code transmitted by the host 100 using the data line pin SDA.

Step 130: and the slave 200 responds to the addressing code, and configures the low 2m bits of the slave address code according to the types of the reference pins electrically connected with the m address pins under the condition of determining the type of the reference pin electrically connected with each address pin.

In practice, it may be that the processor inside the slave 200 responds to the addressing code and performs the operation of step 130.

Step 140: the slave 200 transmits a link signal to the master 100 according to the lower 2m bits of the address code and the lower 2m bits of the address code of the slave 200.

Step 150: the master 100 determines whether to establish communication with the slave 200 according to the link signal. It should be understood that the slave 200 may feed back the addressing code to the master 100 using the data line pin SDA. At this time, the host 100 may receive the link signal using the data line and confirm the link signal.

In one example, if the slave 200 has only one address pin and the address pin is electrically connected to one of the reference pins, the address pin is automatically configured with the address code of the lower 2 bits of the slave 200 after determining the type of the reference pin electrically connected to the address pin of the slave 200. The slave 200 transmits a link signal to the master 100 according to the comparison result of the address code of the lower 2 bits with the address code of the master 100 of the lower 2 bits. The master 100 determines whether to establish communication with the slave 200 according to the link signal.

In another example, if the slave 200 has 2 address pins A₁A₀And address pin A₁A₀Respectively electrically connected to a reference pin, if it is determined that the address pin A of the slave 200 is connected to the reference pin₁A₀Automatically giving the address pin A after the type of the electrically connected reference pin₁A₀The address codes of the lower 4 bits of the slave 200 are configured respectively. The slave 200 transmits a link signal to the master 100 according to the comparison result of the address code of the lower 4 bits with the address code of the master 100 of the lower 4 bits. The master 100 determines whether to establish communication with the slave 200 according to the link signal.

As a possible implementation manner, as shown in fig. 4, the slave 200 determines the type of the reference pin electrically connected to each address pin in response to the addressing code, including:

step 1301: and under the condition that the slave 200 determines that the exclusive-or operation result of the assignment code of each address pin and the assignment code of the reference pin is constantly 0, determining the type of the reference pin corresponding to each address pin according to the exclusive-or operation result.

Step 1302: the slave 200 configures the address of the corresponding address pin according to the type of the reference pin corresponding to each address pin, and determines the low 2m bits of the slave address code according to the addresses of the m address pins.

In practical applications, since the address pins of the slave 200 are electrically connected to the specific reference pins before the slave 200 is connected to the bus circuit, the assignment codes of the address pins of the slave 200 are the same as those of the corresponding reference pins connected thereto. When the assignment codes of the address pins and the assignment codes of each reference pin are subjected to exclusive-or operation, the exclusive-or operation result of the assignment codes of the reference pins electrically connected with the address pins of the slave 200 and the assignment codes of the address pins of the slave 200 is always 0, and the type of the reference pin corresponding to each address pin can be determined according to the exclusive-or operation result.

In one example, if the slave 200 has only one address pin, the slave 200 configures the address of the address pin according to the type of the reference pin to which the address pin is connected, and determines the low 2-bit code word encoded by the slave address according to the address of the address pin.

In another example, if the slave 200 has 2 address pins A₁A₀Then the slave 200 is according to the address pin A₁A₀The type of reference pin connected configures the address pin A₁A₀According to address pin A₁A₀Determines the lower 4-bit code word encoded from the slave address.

As a possible implementation manner, as shown in fig. 5, the slave 200 determines the type of the reference pin to which each address pin is electrically connected, including:

step 1303: and under the condition that the slave 200 determines that the result of the exclusive-or operation of the assignment code of the address pin and the assignment code of one reference pin is greater than 0, the exclusive-or operation is carried out on the assignment code of the address pin and the assignment code of the other reference pin.

In practical application, when the slave 200 determines that the result of the exclusive or operation between the assignment code of the slave address pin and the assignment code of one of the reference pins is greater than 0, the slave 200 controls the assignment code of the slave address pin and the assignment code of the other reference pin to perform exclusive or operation until the result of the exclusive or operation between the assignment code of the address pin of the slave 200 and the assignment code of one of the reference pins is always 0, and the slave 200 determines the type of the reference pin corresponding to each address pin according to the result of the exclusive or operation.

As a possible implementation manner, as shown in fig. 6, the slave 200 sends a link signal to the master 100 according to the low 2m bits of the addressing code and the low 2m bits of the slave address code, including:

step 1401: the slave 200 transmits a link success signal to the master 100 when it is determined that the lower 2m bits of the slave address code coincide with the lower 2m bits of the address code.

Step 1402: if the slave 200 determines that the lower 2m bits of the slave address code are different from the lower 2m bits of the address code, it transmits a link failure signal to the master 100.

Accordingly, as shown in fig. 7, the determining, by the master 100, whether to establish communication with the slave 200 according to the link signal includes:

step 1501: the master 100 receives the link signal transmitted from the slave 200.

Step 1502: the master 100 determines whether to establish communication with the slave 200 according to the connection signal transmitted from the slave 200.

In one example, if the slave 200 has only one address pin, the slave 200 transmits a link success signal, i.e., an ACK signal, to the master 100 in a case where it is determined by the slave 200 that the lower 2 bits of the address code of the address pin coincide with the lower 2 bits of the address code transmitted by the master 100. If the lower 2 bits of the address code of the address pin do not match the lower 2 bits of the address code transmitted by the master 100, the slave 200 transmits a link failure signal, that is, a NACK signal, to the master 100. Accordingly, when the master 100 receives the link signal transmitted from the slave 200, the master 100 selects and transmits the ACK link signal to connect with the slave 200, and establishes data communication.

In another example, if the slave 200 has 2 address pins, the slave 200 transmits a link success signal, i.e., an ACK signal, to the master 100 in a case where the slave 200 determines that the lower 4 bits of the address code of the address pin coincide with the lower 4 bits of the address code transmitted by the master 100. If the lower 4 bits of the address code of the address pin do not match the lower 4 bits of the address code transmitted by the master 100, the slave 200 transmits a link failure signal, that is, a NACK signal, to the master 100. Accordingly, when the master 100 receives the link signal transmitted from the slave 200, the master 100 selects and transmits the ACK link signal to connect with the slave 200, and establishes data communication.

As a possible implementation manner, as shown in fig. 8 to 10, m is 1 or 2 in the slave 200 having m address pins in the embodiment of the present application. N of the n reference pins in the embodiment of the application is 4.

In practical applications, the slave 200 in the embodiment of the present application may be the slave 200 having one address pin, or may be the slave 200 having two address pins. The 4 reference pins in the embodiment of the present application include a clock pin, a data pin, a ground pin and a power voltage.

In order to understand the communication method provided by the embodiment of the present invention, the implementation process of the communication method is described below by taking the I2C bus system shown in fig. 8 to fig. 10 as an example.

As shown in fig. 8 to 10, the I2C bus system has an I2C bus system composed of 1 master 100 and 4 slaves 200, and an I2C bus system composed of 1 master 100 and 16 slaves 200 as an example. It should be understood that each slave 200 has a VDD pin, a GND pin, an SDA pin, an SCL pin. Wherein SCL is clock pin, SDA is data pin, GND is grounding pin, and VDD is power voltage. Each slave 200 has address pins connected to corresponding reference pins before accessing the I2C bus system.

In one example, as shown in FIGS. 8 and 9, if 4 slaves are mounted on the I2C bus, each slave has an address pin A₀. The implementation method of the application is that before each slave is connected to the I2C bus system, the address pin A of each slave is connected₀And selecting to be connected with one of a VDD pin, a GND pin, an SDA pin or an SCL pin of the slave. Now the addressing code high five-digit code word D sent by the limited host 100₆～D₂Fixed, the other two lower bitsD₁～D₀And A₀The connection relationship of (a) is one-to-one correspondence, for example 10010, the addressing code sent by the master 100 through the SDA bus is associated with each slave address pin a₀The corresponding connection relationship of (2) is shown in table 1. When the host 100 sends an addressing code in the table, only when A₀And the slave machines with the pins meeting the corresponding connection relation can respond and return an ACK signal. Taking 1001000 as an example, the upper five-bit codeword D of the addressing code is sent at the host 100₆～D₂In the process of (1), each slave is according to its A₀The assignment codes of the pins are respectively subjected to exclusive OR operation with a VDD pin, a GND pin, an SDA pin and an SCL pin of the slave, the type of a reference pin specifically connected with each slave is determined, and a corresponding A is configured according to the type of the connected reference pin₀The address of the pin is a 2-bit lower codeword. Each slave is according to its A₀The low 2 bits of the address of the pin are compared with the low two bits of the address code word "00" sent by the host 100, and only A is₀When the pin is connected with GND, the slave A₀The low 2 bits of the address for the pin are "00". In this case, only A is present in the I2C bus system₀The slave with the pin connected to GND can respond and return an ACK signal. The slave machines of other connection modes return NACK signals. At this time, the master 100 receives the signal transmitted from the slave, and establishes communication connection with the slave that returns the ACK signal.

TABLE 1 addressing code sent by the Master and Each Slave Address Pin A₀Corresponding connection relation of

Addressing code D6～D0	A0Connection relation
		1001000	Is connected with GND
1001001	Is connected to VDD
		1001010	Connected with SDA
1001011	Connected to the SCL

In one example, as shown in FIG. 10, if 16 slaves 200 are mounted on the I2C bus, each slave 200 now has 2 address pins A₁A₀. The method for realizing the bus interface is that before each slave machine 200 accesses the I2C bus system, the address pin A of each slave machine 200 is connected₁A₀One of the VDD pin, GND pin, SDA pin or SCL pin of the slave 200 is selected to be connected, respectively. Since the slave 200 has two address pins a₁A₀So that now the high three bits D in the addressing code sent by the host 100 are limited₆～D₄Fixed, the rest D₃～D₂Connection to A1, D₁～D₀And the connection relationship of A0 is in one-to-one correspondence. Addressing code sent by the host 100 through SDA bus and each slave address pin A₁A₀The corresponding connection relationship of (2) is shown in table 2. When the host 100 sends an addressing code in the table, only when A₁A₀The slave 200 whose pins satisfy the corresponding connection relationship can respond and return an ACK signal. For example, if A is 1000000₁The pin is connected with GND, A₀When the pins are connected to GND, A of each slave 200 is in the transmission process of the addressing-coded high three-bit code word "100" sent by the master 100₁The pins are respectively exclusive-OR-ed with the VDD pin, the GND pin, the SDA pin and the SCL pin of the slave 200, only A₁The operation result of the pin and the GND pin is always 0, and A is determined₁The reference pin connected with the pin is a GND pin, and the corresponding A is configured according to the definition value of the GND pin₁Address coding Y of pin₁Y₀Is "00". Sending addressing code D at host 100₃～D₂During the transmission of the codeword "00", a of each slave 200₀The pins are respectively exclusive-OR-ed with the VDD pin, the GND pin, the SDA pin and the SCL pin of the slave 200, only A₀The operation result of the pin and the GND pin is always 0, and A is determined₀The reference pin connected with the pin is a GND pin, and the corresponding A is configured according to the definition value of the GND pin₀Address coding X of pin₁X₀Is "00". The slave 200 returns an ACK signal to the master 100 according to the comparison and coincidence between the low four-bit code word "0000" of the slave 200 and the low four-bit code word "0000" of the addressing code sent by the master 100. When receiving the signal transmitted from the slave 200, the master 100 establishes communication connection with the slave 200 that returns the ACK signal.

TABLE 2 addressing code sent by the Master and Each Slave Address Pin A₁、A₀Corresponding connection relation of

Addressing code D6～D0	A1、A0Connection relation	Addressing code D6～D0	A1、A0Connection relation
				1000000	GND、GND	1001000	SDA、GND
1000001	GND、VDD	1001001	SDA、VDD
				1000010	GND、SDA	1001010	SDA、SDA
1000011	GND、SCL	1001011	SDA、SCL
				1000100	VDD、GND	1001100	SCL、GND
1000101	VDD、VDD	1001101	SCL、VDD
				1000110	VDD、SDA	1001110	SCL、SDA
1000111	VDD、SCL	1001111	SCL、SCL

From the above, the present inventionThe I2C bus system in the embodiment of the invention only needs one address pin A to load 4 slaves 200₀Compared with the traditional method, at least 2 slave address pins are required, and one address pin is reduced. Only 2 address pins A are needed to load 16 slaves 200₀In the conventional method, at least 4 slave address pins are required, and 2 address pins are reduced compared with the conventional method. Therefore, the I2C bus system of the application is more convenient and faster when the address pins of the slave are modified due to the reduction of the address pins. In addition, since a fixed distance is required to be set between adjacent address pins, the area of the slave device is increased, and the slave device cannot be used in some devices with limited area. Therefore, the I2C bus system of the present application increases the range of applications of the slave device due to address pin saving.

The above description mainly describes the scheme provided by the embodiment of the present invention from the perspective of the interaction between the master 100 and the slave 200. It is to be understood that the communication control apparatus 300 includes hardware structures and/or software modules for performing the respective functions in order to realize the above functions. Those of skill in the art will readily appreciate that the present invention can be implemented in hardware or a combination of hardware and computer software, with the exemplary elements and algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The embodiments of the present invention may perform functional module division on the master 100 and the slave 200 according to the above method examples, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, the division of the modules in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

In the case of adopting the integrated unit division, fig. 11 shows a schematic structural diagram of a communication control apparatus 300 provided in an embodiment of the present invention. As shown in fig. 11, the communication control apparatus 300 includes: a processing unit 301 and a communication unit 302. Optionally, the communication control apparatus 300 may further include a storage unit 303 for storing program codes and data of the communication control apparatus 300.

In one example, as shown in fig. 11, the communication control apparatus 300 may be the host 100 shown in fig. 2, or may be a chip applied to the host 100 shown in fig. 2.

The communication unit 302 is used to support the communication control apparatus 300 to execute the step 110 executed by the host 100 shown in fig. 2 in the above embodiment.

The processing unit 301 is configured to support the communication control apparatus 300 to execute the step 150 executed by the host 100 shown in fig. 2 in the above embodiment.

In one possible implementation, the processing unit 301 is configured to support the communication control apparatus 300 to execute step 1501 performed by the host 100 shown in fig. 2 in the above-described embodiment.

The processing unit 301 is configured to support the communication control apparatus 300 to execute the step 1502 executed by the host 100 shown in fig. 2 in the above embodiment.

In another example, as shown in fig. 11, the communication control device 300 may be the slave 200 shown in fig. 2, or may be a chip applied to the slave 200 shown in fig. 2.

As shown in fig. 11, the communication unit 302 is configured to support the communication control device 300 to execute the step 120 executed by the slave 200 shown in fig. 2 in the above embodiment.

As shown in fig. 11, the processing unit 301 is configured to support the communication control apparatus 300 to execute the step 130 executed by the communication control apparatus 300 shown in fig. 2 in the above embodiment.

As shown in fig. 11, the communication unit 302 is configured to support the communication control apparatus 300 to execute the step 140 executed by the communication control apparatus 300 shown in fig. 2 in the above embodiment.

In a possible implementation manner, as shown in fig. 11, the processing unit 301 is configured to support the communication control apparatus 300 to perform steps 1301 to 1302 performed by the communication control apparatus 300 shown in fig. 2 in the foregoing embodiment.

In a possible implementation manner, as shown in fig. 11, the processing unit 301 is further configured to support the communication control apparatus 300 to execute step 1303, which is executed by the communication control apparatus 300 shown in fig. 2 in the foregoing embodiment.

In a possible implementation manner, as shown in fig. 11, the communication unit 302 is further configured to support the communication control apparatus 300 to perform steps 1401-1402 in the embodiment described above, which are performed by the communication control apparatus 300 shown in fig. 2.

As shown in fig. 11, the Processing Unit 301 may be a processor or a controller, such as a Central Processing Unit (CPU), a general purpose processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, a DSP and a microprocessor, or the like. The communication unit 302 may be a transceiver, a transceiving circuit or a communication interface, etc. The storage unit 303 may be a memory.

As shown in fig. 11, when the processing unit 301 is a processor, the communication unit 302 is a transceiver, and the storage unit 303 is a memory, the communication control apparatus 300 according to the embodiment of the present invention may be a hardware configuration diagram of the communication control apparatus 300 shown in fig. 11.

As shown in fig. 12, the communication control apparatus 300 according to the embodiment of the present invention includes a processor 310 and a communication interface 330. Communication interface 330 is coupled to processor 310.

In one example, as shown in fig. 12, the communication device is the host 100 shown in fig. 2. The processor 310 is used to execute computer programs or instructions to implement the steps performed by the host 100 in the above embodiments.

In another example, as shown in fig. 12, the communication device is the slave 200 shown in fig. 2. The processor 310 is used for executing computer programs or instructions to implement the steps executed by the slave 200 in the above-described embodiments.

As shown in fig. 12, the processor 310 may be a general-purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention. The communication interface 330 may be one or more. The communication interface 330 may use any transceiver or the like for communicating with other devices or communication networks.

As shown in fig. 12, the communication control device 300 may further include a communication line 340. Communication link 340 may include a path to communicate information between the aforementioned components.

Optionally, as shown in fig. 12, the communication control apparatus 300 may further include a memory 320. The memory 320 is used to store computer instructions for performing aspects of the present invention and is controlled for execution by the processor 310. The processor 310 is configured to execute the computer instructions stored in the memory 320, thereby implementing the communication method provided by the embodiment of the present invention.

As shown in fig. 12, the memory 320 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 320 may be separate and coupled to the processor 310 via a communication line 340. The memory 320 may also be integrated with the processor 310.

Optionally, the computer instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In particular implementations, as one embodiment, processor 310 may include one or more CPUs, such as CPU0 and CPU1 in fig. 12, as shown in fig. 12.

In one implementation, as shown in fig. 12, the communication control apparatus 300 may include a plurality of processors, such as the processor 310 and the processor 350 in fig. 12. Each of these processors may be a single core processor or a multi-core processor.

Fig. 13 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 13, the chip 400 includes one or more (including two) processors 410 and a communication interface 420.

Optionally, as shown in fig. 13, the chip 400 further includes a memory 430, and the memory 430 may include a read-only memory and a random access memory, and provides the processor 410 with operation instructions and data. A portion of memory 430 may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 13, memory 430 stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present invention, as shown in fig. 13, the processor 410 executes the corresponding operation by calling the operation instruction stored in the memory 430 (the operation instruction may be stored in the operating system).

As shown in fig. 13, the processor 410 controls the processing operation of any one of the communication control apparatuses 300, and the processor 410 may also be referred to as a Central Processing Unit (CPU).

As shown in fig. 13, memory 430 may include both read-only memory and random-access memory, and provides instructions and data to processor 410. A portion of the memory 430 may also include NVRAM. For example, in an application, the memory 430, the communication interface 420, and the memory 430 are coupled together by a bus system 440, wherein the bus system 440 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 440 in FIG. 13.

The method disclosed by the embodiment of the invention can be applied to a processor or realized by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

The embodiment of the invention also provides a computer readable storage medium. The computer-readable storage medium has stored therein instructions that, when executed, implement the functions performed by the communication control apparatus in the above-described embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.