阅读说明：本技术 存储单元测试方法、装置、存储介质及电子设备 (Storage unit testing method and device, storage medium and electronic equipment ) 是由 雷泰 刘冲 李振华 于 2020-04-28 设计创作，主要内容包括：本发明公开了一种存储单元测试方法、装置、存储介质及电子设备,该存储单元测试方法包括：获取测试数据；将测试数据按照预设间隔依次写入待测存储单元并对应读取,得到待测数据,对待测数据与测试数据进行一致性比较,得到比较结果；将测试数据按照预设间隔重复执行上述写入、读取和比较步骤,直至待测存储单元上的每一个地址至少被写入过一次；根据所有比较结果输出测试结果。本发明能检测出包括单cell的存储故障和多cell之间的存储故障,以保证存储单元的故障覆盖率；同时无需进行多次的先后升降测试,能有效的降低时间复杂度,有利于提高产能,降低成本,即本发明在保证存储单元的故障覆盖率的同时能减少测试时间。(The invention discloses a storage unit testing method, a device, a storage medium and electronic equipment, wherein the storage unit testing method comprises the following steps: acquiring test data; sequentially writing the test data into the storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result; repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once; and outputting a test result according to all the comparison results. The invention can detect the storage fault of a single cell and the storage fault among multiple cells so as to ensure the fault coverage rate of the storage unit; meanwhile, repeated sequential lifting tests are not needed, time complexity can be effectively reduced, productivity can be improved, and cost is reduced.)

1. A method for testing a memory cell, comprising the steps of:

acquiring test data;

sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result;

repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

and outputting a test result according to all the comparison results.

2. The method for testing a memory cell according to claim 1, wherein the step of sequentially writing the test data into the memory cell to be tested according to the preset interval specifically comprises the steps of:

and extracting interval data from the test data according to a preset interval and writing the interval data into a storage unit to be tested in sequence according to the preset interval.

3. The method for testing a memory cell according to claim 1, wherein the step of sequentially writing the test data into the memory cell to be tested according to a preset interval and reading the test data correspondingly to obtain the data to be tested, and the step of comparing the consistency of the data to be tested and the test data to obtain the comparison result specifically comprises the following steps:

negating the test data to obtain negation data, extracting data of even-numbered bits on the test data to be first data, and extracting data of odd-numbered bits on the test data to be second data;

all addresses of the storage unit to be tested are divided into even row and even column addresses, even row and odd column addresses, odd row and even column addresses and odd row and odd column addresses;

writing the negation data into all addresses of the memory unit to be tested;

writing the first data into even row and even column addresses of the storage unit to be tested according to ascending operation, and writing the second data into odd row and odd column addresses of the storage unit to be tested according to ascending operation;

reading third data from even row and even column addresses of the memory unit to be tested, and performing consistency comparison on the third data and the first data to obtain a comparison result;

reading fourth data from odd row and odd column addresses of the storage unit to be tested, and performing consistency comparison on the fourth data and the second data to obtain a comparison result;

the step of repeatedly executing the writing, reading and comparing the test data according to a preset interval until each address on the memory unit to be tested is written at least once specifically comprises the following steps:

writing the second data into even row and odd column addresses of the storage unit to be tested according to descending operation, and writing the first data into odd row and even column addresses of the storage unit to be tested according to descending operation;

reading fifth data from even row and odd column addresses of the storage unit to be tested, and performing consistency comparison on the fifth data and the second data to obtain a comparison result;

and reading sixth data from the odd-row and even-column addresses of the memory unit to be tested, and performing consistency comparison on the sixth data and the first data to obtain a comparison result.

4. The method as claimed in claim 3, wherein the step of comparing the sixth data with the first data to obtain the comparison result further comprises the following steps:

writing the test data into all addresses of the memory unit to be tested;

writing the second data into even row and even column addresses of the storage unit to be tested according to ascending operation, and writing the first data into odd row and odd column addresses of the storage unit to be tested according to ascending operation;

reading seventh data from even row and even column addresses of the memory unit to be tested, and performing consistency comparison on the seventh data and the second data to obtain a comparison result;

reading eighth data from odd-row and even-column addresses of the storage unit to be tested, and performing consistency comparison on the eighth data and the first data to obtain a comparison result;

writing the first data into even row and odd column addresses of the storage unit to be tested according to descending operation, and writing the second data into odd row and even column addresses of the storage unit to be tested according to descending operation;

ninth data are read from even row and odd column addresses of the storage unit to be tested, consistency comparison is carried out on the ninth data and the first data, and a comparison result is obtained;

and reading tenth data from the odd-row and even-column addresses of the memory unit to be tested, and performing consistency comparison on the tenth data and the second data to obtain a comparison result.

5. The method as claimed in claim 4, wherein the step of comparing the tenth data with the second data for consistency further comprises the following steps:

and reading final data from all addresses of the storage unit to be tested, and performing consistency comparison on the final data and the inverted data to obtain a comparison result.

6. The method as claimed in claim 1, wherein outputting the test result according to all the comparison results comprises the following steps:

if one data in the comparison results is inconsistent, outputting a test result of test failure, and if all the comparison results are consistent, outputting a test result of test passing.

7. The method of claim 1, wherein the test data is selected from a test data set;

after the test result is output according to all the comparison results, the method also comprises the following steps:

and selecting a group of new test data from the test data set, and performing the steps of writing, reading, comparing and outputting test results on the new test data according to a preset interval until each group of test data in the test data set is tested.

8. A memory cell testing apparatus, comprising:

the input module is used for acquiring test data;

the comparison module is used for sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result; repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

and the output module is used for outputting a test result according to all the comparison results.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program stores the memory cell testing method of any one of claims 1-7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the memory cell testing method according to any one of claims 1 to 7 when executing the computer program.

Technical Field

The invention relates to the technical field of LPDDR chip testing, in particular to a storage unit testing method, a storage unit testing device, a storage medium and electronic equipment.

Background

The basic memory cell of LPDDR (Low Power Double Data Rate SDRAM, Low Power consumption memory) is a cell, and a computer and an embedded system perform Data storage and read/write by writing a high level or a Low level in the cell. However, due to the influence of the manufacturing process, the memory cell may cause data storage failure during reading and writing.

Besides the storage failure of a single cell, the failure ratio caused by mutual influence among multiple cells is high, and the detection difficulty is higher. Typical failures of multiple cells are: bridging Fault (BF) and Coupling Fault (CF). For these two failures, the conventional detection method is to perform writing and reading in ascending order and then writing and reading in descending order on the memory cells in the address space, and detect whether there is a data error. Because the simple ascending and descending reading and writing is too simple, the coverage rate of faults is not high, the coverage rate of the algorithm is improved by increasing the sequence and the times of the reading and writing, but the time complexity of the algorithm is greatly improved, and the test time is further increased.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a storage unit testing method, a storage unit testing device, a storage medium and an electronic device are provided, which can ensure the fault coverage rate of a storage unit and reduce the testing time.

In order to solve the technical problems, the invention adopts the technical scheme that:

a memory cell testing method, comprising the steps of:

acquiring test data;

sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result;

repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

and outputting a test result according to all the comparison results.

In order to solve the technical problem, the invention adopts another technical scheme as follows:

a memory cell testing apparatus, comprising:

the input module is used for acquiring test data;

the comparison module is used for sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result; repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

and the output module is used for outputting a test result according to all the comparison results.

In order to solve the technical problem, the invention adopts another technical scheme as follows:

a computer-readable storage medium having stored thereon a computer program having stored thereon the above-described storage unit testing method.

In order to solve the technical problem, the invention adopts another technical scheme as follows:

an electronic device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the computer program to realize the memory cell testing method.

The invention has the beneficial effects that: test data are written into each address of a storage unit to be tested in sequence according to preset intervals and are correspondingly read and compared, so that the writing of each time of the data is performed at intervals, the reading and the comparison are performed, for example, the interval 1 is the address 0, the address 2 and the address 6 are analogized, the interval 2 is the address 0, the address 3 and the address 6 are analogized, the final comparison result can reflect the storage fault among multiple cells, and the coverage rate of the storage fault of the single cell can be ensured by writing all the addresses on the storage unit to be tested at least once, so that the simultaneous detection of the storage fault of the single cell and the storage fault among the multiple cells is realized, and the fault coverage rate of the storage unit is ensured; meanwhile, repeated sequential lifting tests are not needed, time complexity can be effectively reduced, productivity can be improved, and cost is reduced.

Drawings

FIG. 1 is a flow chart illustrating a method for testing a memory cell according to an embodiment of the invention;

FIG. 2 is a schematic diagram illustrating the structure of even row and even column addresses and odd row and odd column addresses of a memory cell according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating the structure of even and odd row and even column addresses on a memory cell according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating data changes of a memory cell according to an embodiment of the present invention;

FIG. 5 is a block diagram of a memory cell testing apparatus according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Description of reference numerals:

1. a memory cell test device; 2. an electronic device; 11. an input module; 12. a comparison module; 13. an output module; 21. a processor; 7. a memory.

Detailed Description

In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1 to 4, an embodiment of the invention provides a method for testing a memory cell, including the steps of:

acquiring test data;

sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result;

repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

and outputting a test result according to all the comparison results.

In this embodiment, the logical way of arranging the memory cells of LPDDR is to determine the location of a certain cell by giving a row address and a column address, but under the current memory technology, the operation of a column is performed by a Burst Length (BL), where the burst length is determined by JEDEC standard, and can be freely set, that is, one-time operation of reading and writing multi-bit (e.g. 8 or 16 bit) column addresses, and writing or reading data of 0 and 1 in each burst length (e.g. the located address is 0 row, the burst length is 8bit, then the first 8 values of the memory cells are written at the same time at the location of 0 row and 0 column, and the second burst length is written into the 9-16 bit values of the memory cells, and writing is continued all the time), when the memory locations of one row are completely written, the test software relocates the address of the next row, and continues the operation of the previous row until the data is written on the whole disk, and the like), that is, in the present embodiment, if the test data is rewritten at the storage location of each row, for example, the test data is 101010 … 1010, the first row is written 101, and the second row is also 101, instead of being connected to the end 010 of the first row.

In addition, the explanation for writing at preset intervals is as follows: for example, at an interval of 1, the test data is written into addresses of 0 column, 2 column, 4 column, etc. on a certain row of the memory cell, and if the interval is 2, the test data is written into addresses of 0 column, 3 column, 6 column, etc. on a certain row of the memory cell. Since a storage failure between multiple cells is generally a failure between adjacent cells, the interval writing, reading and comparing can identify the storage failure between multiple cells.

From the above description, the beneficial effects of the present invention are: the method comprises the steps of sequentially writing test data into each address of a storage unit to be tested according to preset intervals, and performing corresponding reading and comparison, so that the writing of the data every time is interval writing, reading and comparison, the final comparison result can reflect the storage fault among multiple cells, and the coverage rate of the storage fault of a single cell can be ensured by writing all the addresses on the storage unit to be tested at least once, so that the simultaneous detection of the storage fault of the single cell and the storage fault among the multiple cells is realized, and the coverage rate of the storage unit fault is ensured; meanwhile, repeated sequential lifting tests are not needed, time complexity can be effectively reduced, productivity can be improved, and cost is reduced.

Further, the step of sequentially writing the test data into the memory unit to be tested according to the preset interval specifically includes the following steps:

and extracting interval data from the test data according to a preset interval and writing the interval data into a storage unit to be tested in sequence according to the preset interval.

As can be seen from the above description, data is extracted from test data at a predetermined interval and then written into the test data, for example, the test data is 101010 … 1010, and if the interval is 1, the extracted data is 111 … … 11, and then 111 … … 11 is sequentially written into addresses of 0 column, 2 column, 4 column, etc. on a certain row of the memory cell, and if the interval is 2, the extracted data is 101 … … 101, then the test data is written into addresses of 0 column, 3 column, 6 column, etc. on a certain row of the memory cell, and 101 … … 101 is sequentially written into the addresses.

Further, the step of sequentially writing the test data into a storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result specifically includes the following steps:

negating the test data to obtain negation data, extracting data of even-numbered bits on the test data to be first data, and extracting data of odd-numbered bits on the test data to be second data;

all addresses of the storage unit to be tested are divided into even row and even column addresses, even row and odd column addresses, odd row and even column addresses and odd row and odd column addresses;

writing the negation data into all addresses of the memory unit to be tested;

writing the first data into even row and even column addresses of the storage unit to be tested according to ascending operation, and writing the second data into odd row and odd column addresses of the storage unit to be tested according to ascending operation;

reading third data from even row and even column addresses of the memory unit to be tested, and performing consistency comparison on the third data and the first data to obtain a comparison result;

reading fourth data from odd row and odd column addresses of the storage unit to be tested, and performing consistency comparison on the fourth data and the second data to obtain a comparison result;

the step of repeatedly executing the writing, reading and comparing the test data according to a preset interval until each address on the memory unit to be tested is written at least once specifically comprises the following steps:

writing the second data into even row and odd column addresses of the storage unit to be tested according to descending operation, and writing the first data into odd row and even column addresses of the storage unit to be tested according to descending operation;

reading fifth data from even row and odd column addresses of the storage unit to be tested, and performing consistency comparison on the fifth data and the second data to obtain a comparison result;

and reading sixth data from the odd-row and even-column addresses of the memory unit to be tested, and performing consistency comparison on the sixth data and the first data to obtain a comparison result.

As can be seen from the above description, setting the interval to 1, that is, it can be distinguished twice before and after by the parity on the address, and when writing for the first time, writing the first data into the even rows and the even columns, and writing the second data into the odd rows and the odd columns, respectively, as shown in fig. 2, so that the upper, lower, left, and right sides of each cell in which test data is written are cells in which test data is not written, thereby better detecting a storage failure between multiple cells; in addition, the data writing, reading and testing of the even row and odd column addresses and the odd row and even column addresses are also the same, and refer to fig. 3. Therefore, the fault coverage rate of the storage unit can be ensured only by writing, reading and testing twice, so that the time complexity is further reduced, and the fault coverage rate of the storage unit is improved.

Further, after the consistency comparison of the sixth data and the first data is performed, the following steps are further included after a comparison result is obtained:

writing the test data into all addresses of the memory unit to be tested;

writing the second data into even row and even column addresses of the storage unit to be tested according to ascending operation, and writing the first data into odd row and odd column addresses of the storage unit to be tested according to ascending operation;

reading seventh data from even row and even column addresses of the memory unit to be tested, and performing consistency comparison on the seventh data and the second data to obtain a comparison result;

reading eighth data from odd-row and even-column addresses of the storage unit to be tested, and performing consistency comparison on the eighth data and the first data to obtain a comparison result;

writing the first data into even row and odd column addresses of the storage unit to be tested according to descending operation, and writing the second data into odd row and even column addresses of the storage unit to be tested according to descending operation;

ninth data are read from even row and odd column addresses of the storage unit to be tested, consistency comparison is carried out on the ninth data and the first data, and a comparison result is obtained;

and reading tenth data from the odd-row and even-column addresses of the memory unit to be tested, and performing consistency comparison on the tenth data and the second data to obtain a comparison result.

From the above description, it can be seen that data is written after being inverted, and then full coverage of even rows and even columns, odd rows and odd columns, even rows and odd columns, and full coverage of even rows and even columns is performed, so that each cell is written, read, and compared at least once by high level 1, low level 0, ascending operation, and descending operation, and thus whether a storage fault exists in each cell when writing high level, low level, ascending operation, or descending operation is performed on the memory cell can be detected, and the detection coverage rate of the storage fault of a single cell and the storage fault between multiple cells is further improved.

Further, after the consistency comparison between the tenth data and the second data is performed, the following steps are further included:

and reading final data from all addresses of the storage unit to be tested, and performing consistency comparison on the final data and the inverted data to obtain a comparison result.

From the above description, after the previous even row and odd column and odd row and even column are traversed, the data in all the cells should be the same as the inverted data without storage failure, but if there is a coupling failure, the data of individual cells may not be the corresponding value on the inverted data, so the consistency comparison is performed again through the inverted data to further detect whether there is a coupling failure, thereby further improving the failure detection coverage rate of the storage cells.

Further, the outputting the test result according to all the comparison results specifically includes the following steps:

if one data in the comparison results is inconsistent, outputting a test result of test failure, and if all the comparison results are consistent, outputting a test result of test passing.

From the above description, it can be seen that, in the test process, if a comparison error occurs, the test process is not stopped until the test is completely completed, so as to ensure the test fluency, and in addition, if any comparison result is that the data comparison is inconsistent, it is determined that a storage fault exists in the storage unit to be tested, so as to ensure the quality of the storage unit to be tested.

Further, the test data is selected from a set of test data;

after the test result is output according to all the comparison results, the method also comprises the following steps:

and selecting a group of new test data from the test data set, and performing the steps of writing, reading, comparing and outputting test results on the new test data according to a preset interval until each group of test data in the test data set is tested.

From the above description, it can be seen that, in the testing process, the multiple sets of data are used for repeated testing to ensure better fault coverage, although the testing time is increased, compared with other existing detection methods, the time complexity is still lower under the condition that the number of the test data is consistent, so that the high fault coverage and the low time complexity of the test can be better realized at the same time.

Referring to fig. 5, another embodiment of the invention provides a memory cell testing apparatus 1, including:

the input module 11 is used for acquiring test data;

the comparison module 12 is configured to sequentially write the test data into a to-be-tested storage unit according to a preset interval and correspondingly read the test data to obtain to-be-tested data, and perform consistency comparison on the to-be-tested data and the test data to obtain a comparison result; repeatedly executing the writing, reading and comparing steps on the test data according to preset intervals until each address on the memory unit to be tested is written at least once;

the output module 13 is configured to output a test result according to all the comparison results.

With regard to the specific processes and corresponding effects implemented by the input module 11, the comparison module 12 and the output module 13, reference may be made to the related descriptions in the memory cell testing method of the above-mentioned embodiments.

Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, where the computer program stores the storage unit testing method of the above-mentioned embodiment.

With regard to the specific implementation procedure and the corresponding effect of the memory cell testing method included in the computer program in the present embodiment, reference may be made to the related description in the memory cell testing method of the above-described embodiment.

Referring to fig. 6, another embodiment of the present invention provides an electronic device 2, which includes a memory 22, a processor 21, and a computer program stored in the memory 22 and executable on the processor 21, wherein the processor 21 implements the memory cell testing method of the above embodiment when executing the computer program.

With regard to the specific implementation procedure and the corresponding effect of the memory cell testing method implemented by the processor 21 in this embodiment, reference may be made to the related description in the memory cell testing method of the foregoing embodiment.

The storage unit testing method, the corresponding device, the storage medium and the electronic device are mainly applied to an application scenario of performing storage testing on LPDDR3, LPDDR4, LPDDR4X and other LPDDR, and the following description is given in combination with a specific application scenario:

as described above, with reference to fig. 1 to 4, the first embodiment of the present invention is:

a memory cell testing method, comprising the steps of:

s1, obtaining test data;

specifically, in the present embodiment, the test data D is 01010101 … … 010;

s2, sequentially writing the test data into the storage unit to be tested according to a preset interval and correspondingly reading the test data to obtain data to be tested, and performing consistency comparison on the data to be tested and the test data to obtain a comparison result;

in this embodiment, the method specifically includes the following steps:

s21, negating the test data D to obtain negation data/D, wherein the negation data/D is 10101010 … … 1010;

s22, extracting the even-numbered data of the test data D as the first data, i.e. the first data is 000 … 000, and extracting the odd-numbered data of the test data D as the second data, i.e. the second data is 111 … 111;

s23, dividing all addresses of the memory cell to be tested into even row and even column addresses, even row and odd column addresses, odd row and even column addresses, and odd row and odd column addresses, as shown in fig. 2 and 3, the even row and even column addresses are 0 row and 0 column addresses, the even row and odd column addresses are 0 row and 1 column addresses, the odd row and even column addresses are 2 row and 0 column addresses, and the odd row and odd column addresses are 1 row and 1 column addresses; for convenience of description, the six address data diagrams of fig. 4 are named as an upper left diagram, an upper middle diagram, an upper right diagram, a lower middle diagram and a lower left diagram according to the directions and arrows, wherein the numerical values in the cell being written at the time are indicated by underlining;

s24, writing the inverted data/D into all the addresses of the memory cells to be tested to obtain the upper left diagram of FIG. 4, namely each row is 10101010 … … 1010;

s25, writing the first data 000 … 000 into even row and even column addresses of the memory unit to be tested according to an ascending operation, and writing the second data 111 … 111 into odd row and odd column addresses of the memory unit to be tested according to the ascending operation, so as to obtain the middle upper graph of the graph in FIG. 4;

s26, reading third data from even row and even column addresses of the memory unit to be tested, performing consistency comparison on the third data and the first data 000 … 000 to obtain a comparison result, reading fourth data from odd row and odd column addresses of the memory unit to be tested, and performing consistency comparison on the fourth data and the second data 111 … 111 to obtain a comparison result; thus, if there is no storage failure, the comparison results should be consistent;

s27, writing the second data 111 … 111 into the even row and odd column addresses of the memory unit to be tested according to the descending operation, and writing the first data 000 … 000 into the odd row and even column addresses of the memory unit to be tested according to the descending operation, so that the upper right diagram of the graph in FIG. 4 is obtained;

s28, reading fifth data from even row and odd column addresses of the memory unit to be tested, performing consistency comparison on the fifth data and the second data 111 … 111 to obtain a comparison result, reading sixth data from odd row and even column addresses of the memory unit to be tested, and performing consistency comparison on the sixth data and the first data 000 … 000 to obtain a comparison result; thus, if there is no memory failure, the comparison results should also be consistent.

Therefore, as can be seen from the upper left diagram and the upper right diagram of fig. 4, after the round of testing of steps S21 to S28 is performed, all cells on the memory cell to be tested are written once, and the values are changed, i.e., written effectively, which is beneficial to the accuracy of the testing.

S3, repeatedly executing the writing, reading and comparing steps on the test data according to a preset interval until each address on the memory unit to be tested is written at least once;

in this embodiment, the method specifically includes the following steps:

s31, writing the test data D into all addresses of the memory unit to be tested to obtain a lower right diagram of the graph 4;

s32, writing the second data 111 … 111 into even row and even column addresses of the storage unit to be tested according to an ascending operation, and writing the first data 000 … 000 into odd row and odd column addresses of the storage unit to be tested according to the ascending operation to obtain a middle lower graph of the graph in FIG. 4;

s33, reading seventh data from even row and even column addresses of the memory unit to be tested, performing consistency comparison on the seventh data and the second data 111 … 111 to obtain a comparison result, reading eighth data from odd row and even column addresses of the memory unit to be tested, and performing consistency comparison on the eighth data and the first data 000 … 000 to obtain a comparison result; thus, if there is no memory failure, the comparison should be consistent.

S34, writing the first data 000 … 000 into even row and odd column addresses of the storage unit to be tested according to descending operation, and writing the second data 111 … 111 into odd row and even column addresses of the storage unit to be tested according to descending operation to obtain a lower left diagram of the graph in FIG. 4;

s35, reading ninth data from the even row and odd column address of the memory unit to be tested, performing consistency comparison on the ninth data and the first data 000 … 000 to obtain a comparison result, reading tenth data from the odd row and even column address of the memory unit to be tested, and performing consistency comparison on the tenth data and the second data 111 … 111 to obtain a comparison result, wherein if no storage fault exists, the comparison result is consistent.

Therefore, all cells on the memory cell to be tested are written twice, and the value is written and tested from 1 to 0 or from 0 to 1, so that the accuracy and comprehensiveness of the test are facilitated.

And S36, finally, reading the final data from all the addresses of the memory unit to be tested, and performing consistency comparison on the final data and the inverted data/D to obtain a comparison result, wherein if no storage fault exists, the lower left diagram of the figure 4 is equal to the inverted data/D, and therefore the comparison result is consistent.

And S4, outputting a test result according to all the comparison results.

Specifically, in the present embodiment, since the test is continued in the next step regardless of whether the comparison result is passed or failed, the verification is performed at the end. If one comparison result is that the data comparison is inconsistent, the test result is that the test fails, and if all the comparison results are that the data comparison is consistent, the test result is that the test passes.

In this embodiment, the test data D, the preset interval, and the ascending and descending order are exemplified, in other equivalent embodiments, other test data D may be considered, such as 100100 … 100, 11011101 … 1101, and the like, the preset interval may also be considered as 2 or 3, and each round of test may also be first descending and then ascending, and the like.

As described above, with reference to fig. 1 to 4, the second embodiment of the present invention is:

a method for testing a memory cell, based on the first embodiment, in this embodiment, there is more than one test data D, for example, in this embodiment, the test data set is a test data set, and the test data set includes two sets of test data, which are: d1 ═ 01010101 … … 0101 and D2 ═ 10101010 … … 1010, and in this embodiment, step S2 to step S4 in the first embodiment can be implemented by first using D1 as the test data D. Then, a new set of test data, i.e., D2, is selected from the test data set as new test data D, and the new test data D is used to implement steps S2 to S4 in the first embodiment.

Referring to fig. 5, a third embodiment of the invention is a memory cell testing apparatus 1 corresponding to the memory cell testing method in the first or second embodiment, including:

the input module 11 is used for acquiring test data;

the comparison module 12 is configured to sequentially write test data into the memory unit to be tested according to a preset interval, read the data to be tested from the memory unit to be tested according to the preset interval, perform consistency comparison on the data to be tested and the test data to obtain a comparison result, then sequentially write the test data into other addresses of the memory unit to be tested according to the preset interval, and perform reading and comparison until all addresses on the memory unit to be tested are written into at least once;

the output module 13 is used for outputting the test result according to all the comparison results.

An embodiment four of the present invention is a computer-readable storage medium corresponding to the method for testing a memory cell in the above-mentioned embodiment one or two, wherein a computer program is stored thereon, and the computer program stores the method for testing a memory cell in the above-mentioned embodiment one or two.

Referring to fig. 6, a fifth embodiment of the present invention is an electronic device 2 corresponding to the memory cell testing method in the first or second embodiment, and includes a memory 22, a processor 21, and a computer program stored in the memory 22 and capable of being executed on the processor 21, where the memory cell testing method in the first or second embodiment is implemented when the processor 21 executes the computer program.

In the six embodiments provided in the present application, it should be understood that the disclosed method, apparatus, storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In summary, in the memory cell testing method, the memory cell testing device, the memory medium and the electronic device provided by the invention, multiple groups of data are used for testing, the test data are written into the memory cells to be tested in sequence according to the even rows and even columns, the odd rows and odd columns, the even rows and odd columns and the odd rows and even columns, and are sequentially read and compared, so that each cell is written, read and compared at least once by the high level 1, the low level 0, the ascending operation and the descending operation, and finally consistency comparison is performed again through the negation data, so that the memory faults including single cells and the memory faults among multiple cells can be comprehensively detected, and the fault coverage rate of the memory cells is ensured; meanwhile, repeated successive lifting tests are not needed, the time complexity can be effectively reduced, the productivity is favorably improved, and the cost is reduced, namely, when the storage test is carried out on the LPDDR3, LPDDR4, LPDDR4X and other LPDDR, the fault coverage rate of the storage unit can be ensured, and the test time can be reduced.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.