阅读说明：本技术 位线驱动的读出放大器时钟方案 (Bit line driven sense amplifier clocking scheme ) 是由 H·尚卡尔 M·加格 R·K·纳德卡尔尼 R·库马尔 M·潘 于 2018-10-25 设计创作，主要内容包括：公开了一种存储器系统,该存储器系统包括：被电耦合到与存储器阵列的列相关联的第一位线和第二位线的读出放大器；被电耦合到第一位线的bl晶体管,其中bl晶体管被配置为从第一位线接收第一电信号作为输入；以及被电耦合到第二位线的blb晶体管,其中blb晶体管被配置为从第二位线接收第二电信号作为输入,其中bl晶体管的输出和blb晶体管的输出被电耦合在一起作为共同输出,并且其中读出放大器被配置为接收bl晶体管和blb晶体管的共同输出作为输入。(Disclosed is a memory system including: a sense amplifier electrically coupled to a first bit line and a second bit line associated with a column of the memory array; a bl transistor electrically coupled to the first bit line, wherein the bl transistor is configured to receive a first electrical signal from the first bit line as an input; and a blb transistor electrically coupled to the second bit line, wherein the blb transistor is configured to receive the second electrical signal as an input from the second bit line, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive the common output of the bl transistor and the blb transistor as an input.)

1. A memory system, comprising:

a sense amplifier electrically coupled to a first bit line and a second bit line associated with a column of a memory array;

a bl transistor electrically coupled to the first bit line, wherein the bl transistor is configured to receive a first electrical signal as an input from the first bit line; and

a blb transistor electrically coupled to the second bit line, wherein the blb transistor is configured to receive a second electrical signal as an input from the second bit line,

wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive the common output of the bl transistor and the blb transistor as an input.

2. The memory system of claim 1, wherein the memory array comprises a Static Random Access Memory (SRAM) array.

3. The memory system of claim 1, wherein the bl transistor is configured to conduct when the first bit line is discharged, and wherein the blb transistor is configured to be powered when the second bit line is discharged.

4. The memory system of claim 1, wherein the common output of the bl transistor and the blb transistor comprises: a sense amplifier enable signal configured to be input to the sense amplifier.

5. The memory system of claim 1, wherein the common output of the bl transistor and the blb transistor is connected across two or more columns of the memory array that are configured to be accessed together.

6. The memory system of claim 1, further comprising a multiplexer electrically coupled between a plurality of bit lines and the sense amplifier, the plurality of bit lines including the first bit line and the second bit line, the multiplexer configured to select a pair of the plurality of bit lines and output the pair of bit lines to the sense amplifier.

7. The memory system of claim 1, further comprising a program clock transistor electrically coupled to the bl transistor and the blb transistor, wherein the program clock transistor is configured to disable the common output of the bl transistor and the blb transistor.

8. The memory system of claim 7, wherein a size of the program clock transistor determines a strength of the program clock transistor.

9. The memory system of claim 7, wherein a gate voltage of the program clock transistor determines a strength of the program clock transistor when the program clock transistor is conducting during a read operation.

10. The memory system of claim 7, wherein the program clock transistor is configured to: disabling the common output of the bl transistor and the blb transistor based on enabling a subset of program clock transistors.

11. The memory system of claim 1, further comprising a multiplexer configured to: selecting an input from a program sense amplifier enable signal transistor or the common output of the bl transistor and the blb transistor.

12. The memory system of claim 1, further comprising a discharge transistor configured to disable the common output of the bl transistor and the blb transistor.

13. The memory system of claim 1, further comprising:

a plurality of columns of the memory array, including the columns, wherein less than all of the columns of the plurality of columns are associated with pairs of bl transistors and blb transistors that include the bl transistors and the blb transistors.

14. A method of operating a memory system, comprising:

receiving, at a bl transistor electrically coupled to a first bit line of a column of a memory array, a first electrical signal from the first bit line based on the first bit line being discharged;

receiving, at a blb transistor electrically coupled to a second bit line of the column of the memory array, a second electrical signal from the second bit line based on the second bit line being discharged, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output;

receiving the common output of the bl transistor and the blb transistor as a sense amplifier enable signal at a sense amplifier electrically coupled to the first bit line and the second bit line; and

measuring, by the sense amplifier, a voltage difference across the first bit line and the second bit line based on receipt of the sense amplifier enable signal.

15. The method of claim 14, wherein the memory array comprises a Static Random Access Memory (SRAM) array.

16. The method of claim 14, wherein the bl transistor conducts when the first bit line is discharged, and wherein the blb transistor is powered when the second bit line is discharged.

17. The method of claim 14, wherein the common output of the bl transistor and the blb transistor comprises a sense amplifier enable signal input to the sense amplifier.

18. The method of claim 14, wherein the common output of the bl transistor and the blb transistor are connected across two or more columns of the memory array that are accessed together.

19. The method of claim 14, further comprising:

selecting, by a multiplexer electrically coupled between a plurality of bit lines and the sense amplifier, a pair of bit lines of the plurality of bit lines, the plurality of bit lines including the first bit line and the second bit line; and

outputting, by the multiplexer, the pair of bit lines to the sense amplifier.

20. The method of claim 14, further comprising:

disabling the common output of the bl transistor and the blb transistor by a program clock transistor electrically coupled to the bl transistor and the blb transistor.

21. The method of claim 20, wherein a size of the program clock transistor determines a strength of the program clock transistor.

22. The method of claim 20, wherein a gate voltage of the program clock transistor determines a strength of the program clock transistor when the program clock transistor is conducting during a read operation.

23. The method of claim 20, wherein the program clock transistor is configured to: disabling the common output of the bl transistor and the blb transistor based on enabling a subset of program clock transistors.

24. The method of claim 14, further comprising:

selecting, by a multiplexer, an input from a program sense amplifier enable signal transistor or the common output of the bl transistor and the blb transistor.

25. The method of claim 14, further comprising:

disabling the common output of the bl transistor and the blb transistor by a discharge transistor.

26. The memory system of claim 14, wherein the memory array comprises a plurality of columns including the column, wherein less than all columns of the plurality of columns are associated with pairs of bl transistors and blb transistors including the bl transistors and the blb transistors.

27. A memory system, comprising:

a first means for receiving a first electrical signal from a first bit line of a column of a memory array based on the first bit line being discharged, the first means for receiving being electrically coupled to the first bit line;

second means for receiving a second electrical signal from a second bit line of the column of the memory array based on the second bit line being discharged, the second means for receiving being electrically coupled to the second bit line, wherein an output of the first means for receiving and an output of the second means for receiving are electrically coupled together as a common output; and

means for amplifying a voltage swing configured to receive the common output of the first means for receiving and the second means for receiving as a sense amplifier enable signal, the means for amplifying the voltage swing being electrically coupled to the first bit line and the second bit line, wherein the means for amplifying the voltage swing is further configured to measure a voltage difference across the first bit line and the second bit line based on receipt of the sense amplifier enable signal.

28. The memory system of claim 27, further comprising:

means for selecting and outputting a pair of bit lines of a plurality of bit lines of the memory array, the plurality of bit lines including the first bit line and the second bit line, the means for selecting coupled between the plurality of bit lines and the means for amplifying the voltage swing.

29. The memory system of claim 27, further comprising:

means for disabling the common output of the first means for receiving and the second means for receiving, the means for disabling being electrically coupled to the first means for receiving and the second means for receiving.

30. The memory system of claim 27, further comprising:

means for selecting an input from a program sense amplifier enable signal transistor or the common output of the first means for receiving and the second means for receiving.

Background

Aspects of the present disclosure relate generally to sense amplifiers in memory chips, and more particularly to sense amplifier clocking schemes and the like.

In a computer memory, a sense amplifier is part of the read circuitry of a semiconductor memory chip used in reading data from the memory. Data in a semiconductor memory chip is stored in memory cells arranged on the chip in an array of rows and columns. The wires connecting a row of memory cells are called a "word line" and are activated by generating a voltage thereon. Each column of memory cells has an associated pair of conductive lines (one on either side of the column of memory cells), referred to as "bit lines". Each pair of bit lines is attached to a sense amplifier at the edge of the memory array. Each memory cell is located at the intersection of a particular word line and bit line, and their intersection can be used to "address" the cell.

To read a bit from a particular memory cell in a Static Random Access Memory (SRAM) chip, the word line (row) in which the cell is located is activated (i.e., a current is generated on the word line). The value stored in the cell (a logical "0" or "1") may then be determined by sensing the voltage difference across a pair of bit lines associated with the memory cell (i.e., bit lines on either side of the column of memory cells containing the memory cell in question). The role of the sense amplifier associated with a bit line pair is to sense the voltage difference across the bit line (which represents the value stored in the memory cell) and amplify the voltage difference to an identifiable logic level (i.e., a logic "0" or "1") so that the data can be properly interpreted by logic external to the memory array. The desired bit in the memory cell is then latched into a buffer from the sense amplifier of the cell and then placed on the output bus.

The operation of the sense amplifiers in a Dynamic Random Access Memory (DRAM) chip with additional functionality is similar to the operation of the sense amplifiers in an SRAM chip. The data in each memory cell of a DRAM chip is stored as a charge in a capacitor in the memory cell. A read operation of a particular memory cell depletes the charge in the cell, destroying the data. Thus, after data is read out, the sense amplifier writes it back into the cell by applying a voltage to the cell immediately, thereby charging the capacitor. This is called memory refresh.

The sense amplifier is driven by a sense amplifier enable ("saen") signal generated by a sense amplifier enable signal generator. To enable the sense amplifier to sense a voltage level across a pair of bit lines, a sense amplifier enable signal generator receives an external clock signal and generates a sense amplifier enable signal after a delay of a period of time. Upon receiving the sense amplifier enable signal, the sense amplifier may detect a voltage difference across the pair of bit lines.

Memory cells in SRAM circuits are typically composed of two, four, or six transistors. In a six transistor (6T) SRAM based design, "contention" between the time the sense amplifier receives the sense amplifier enable signal and the time during which the sense amplifier can accurately evaluate the voltage across the bit line (i.e., determine whether the memory cell being read contains a "0" or a "1") is an important performance margin. The sense amplifier enable signal needs to arrive so that the bit line differential (i.e., the voltage across the pair of bit lines) is sufficient for the sense amplifier offset (i.e., the minimum voltage difference required on the bit lines for the sense amplifier to properly detect the voltage difference). In addition, the timing of the sense amplifier enable signal directly affects the delay of the SRAM output, where a longer delay in generating the sense amplifier enable signal results in a longer delay in reading the memory cell.

Furthermore, it is necessary to track the sense amplifier enable signal with a six sigma statistical weak bit evaluation (in any integrated circuit, there are some differences in the current strength of the transistors due to manufacturing defects — therefore, most SRAM circuits are designed with enough margin to cover six times the variance or "sigma" of the process). In memories with complex decoding, such as Content Addressable Memory (CAM) based decoding or predictive based decoding, the divergent path between the bit line pair voltage difference and the arrival of the sense amplifier enable signal may be large, and thus the on-chip variation (OCV) margin may also be large. This difference increases the output delay of the SRAM array.

In general, "rd _ bank _ clk" (i.e., the clock within the memory array of the memory chip) serves as a divergence point of the contention margin because the sense amplifier enable signal generator receives the clock signal from rd _ bank _ clk. However, in memories that require word/byte gating of the word line, there may be multiple deterministic divergent pinback paths, and thus the main clock ("clk") may also cause a delay. Also, dual voltage domains require that the margin span both the various array and logic domain voltages. More specifically, the low power memory uses a dual voltage domain architecture. In this architecture, the memory bitcell array is connected to a power supply with limited scalability (array power domain), while part of the peripherals and the rest of the logic are connected to a different fully scalable power supply (logic power domain). During low power operation, the logic power supply is reduced to a voltage much lower than the minimum voltage at which the bitcell can operate. Under this architecture, the word line and sense amplifier paths span two voltage domains and need to track each other over the entire power supply range.

In addition, the worst case sensing margin occurs at low voltage levels, which drives the turbo corner (i.e., the high voltage corner that sets the highest supported frequency) sense amplifier enable signal timing. More specifically, the increased variation at low voltage requires more margin at the low voltage corners and affects the timing of the sense amplifier enable signal at the turbo corners. Reducing the difference between the bit line and sense amplifier enable signals can help to save OCV margin and improve the overall timing of the macro (e.g., SRAM block).

Disclosure of Invention

The following presents a simplified summary in connection with one or more aspects disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects, nor should it be considered to identify key or critical elements relating to all contemplated aspects or to delineate the scope associated with any particular aspect. Accordingly, the sole purpose of the following summary is to present some concepts of one or more aspects related to the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

In one aspect, a memory system includes: a sense amplifier electrically coupled to a first bit line and a second bit line associated with a column of the memory array; a bl transistor electrically coupled to the first bit line, wherein the bl transistor is configured to receive a first electrical signal from the first bit line as an input; and a blb transistor electrically coupled to the second bit line, wherein the blb transistor is configured to receive the second electrical signal as an input from the second bit line, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive the common output of the bl transistor and the blb transistor as an input.

In one aspect, a method of operating a memory system includes: receiving, at a bl transistor electrically coupled to a first bit line of a column of a memory array, a first electrical signal from the first bit line based on the first bit line being discharged; receiving, at a blb transistor electrically coupled to a second bit line of a column of the memory array, a second electrical signal from the second bit line based on the second bit line being discharged, wherein an output of the bl transistor and an output transistor of the blb are electrically coupled together as a common output; receiving a common output of the bl transistor and the blb transistor as a sense amplifier enable signal at a sense amplifier electrically coupled to the first bit line and the second bit line; and measuring, by the sense amplifier, a voltage difference across the first bit line and the second bit line based on the receipt of the sense amplifier enable signal.

In one aspect, a memory system includes: first means for receiving a first electrical signal from a first bit line based on the first bit line being discharged for a column of the memory array, the first means for receiving being electrically coupled to the first bit line; second means for receiving a second electrical signal from a second bit line based on the second bit line being discharged for a column of the memory array, the second means for receiving being electrically coupled to the second bit line, wherein an output of the first means for receiving and an output of the second means for receiving are electrically coupled together as a common output; and means for amplifying a voltage swing configured to receive a common output of the first means for receiving and the second means for receiving as a sense amplifier enable signal, the means for amplifying a voltage swing electrically coupled to the first bit line and the second bit line, wherein the means for amplifying a voltage swing is further configured to measure a voltage difference across the first bit line and the second bit line based on the receiving of the sense amplifier enable signal.

Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description.

Drawings

The accompanying drawings are presented to aid in the description of various aspects of the disclosure and are provided solely for illustration of the aspects and not limitation thereof.

FIG. 1 shows an exemplary architecture of an SRAM.

FIG. 2 illustrates an exemplary architecture of a single column of an SRAM array in more detail.

Fig. 3 shows an exemplary circuit including a conventional sense amplifier.

Fig. 4 illustrates a conventional system showing generation of a sense amplifier enable signal.

Fig. 5 illustrates an exemplary architecture showing generation of a sense amplifier enable signal in accordance with at least one aspect of the present disclosure.

Fig. 6A and 6B illustrate an exemplary system showing generation of a sense amplifier enable signal according to at least one aspect of the present disclosure.

Fig. 7 illustrates an example circuit including a sense amplifier according to an aspect of this disclosure.

Fig. 8 illustrates various graphs showing timing of various signals in accordance with at least one aspect of the present disclosure.

FIG. 9 illustrates an example method of operating a memory system according to an aspect of this disclosure.

Detailed Description

Disclosed is a memory system including: a sense amplifier electrically coupled to a first bit line and a second bit line associated with a column of a memory array; a bl transistor electrically coupled to the first bit line, wherein the bl transistor is configured to receive a first electrical signal from the first bit line as an input; and a blb transistor electrically coupled to the second bit line, wherein the blb transistor is configured to receive the second electrical signal as an input from the second bit line, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive the common output of the bl transistor and the blb transistor as an input.

More particular aspects of the disclosure are provided in the following description and related drawings directed to various examples provided for purposes of illustration. Alternative aspects may be devised without departing from the scope of the disclosure. Additionally, well-known aspects of the disclosure may not be described in detail, or may be omitted, so as not to obscure the more relevant details.

Those of skill in the art would understand that the information and signals described below may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending, in part, on the particular application, desired design, corresponding technology, and so forth.

Further, some aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., Application Specific Integrated Circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, for each aspect described herein, any such aspect in corresponding form may be implemented, for example, as logic "configured to" perform the described action.

Fig. 1 shows an exemplary architecture of an N × M SRAM array 100, the N × M SRAM array 100 having N rows and M columns and thus N × M memory cells (some of which are labeled with reference numeral 102). Each memory cell 102 is connected to one of a plurality of word lines (some of which are labeled with reference numeral 104) and a pair of bit lines (some of which are labeled with reference numerals 106a and 106b and are collectively referred to as bit lines 106 or individually as bit lines 106) arranged perpendicular to the word lines 104. Only one word line 104 is active at a time. Row decoder 110 receives and decodes address information to activate a single row by generating a current for that row on word line 104. Similarly, the column decoder 112 also receives address information and activates the corresponding column. The number of columns activated depends on the size of the words in the context of the system. For example, a system may have 32-bit words, and in this case, column decoder 112 would activate 32 columns at a time.

Sense amplifiers (not shown in fig. 1) associated with columns of the SRAM array 100 are used during read operations to measure the voltage difference across the bit line pair 106 and output full swing data (full swing data), which represents the value of the data stored in the selected memory cell 102. That is, the sense amplifier amplifies a small voltage "swing" (variation) across the bit line pair 106 and amplifies it to an identifiable logic level (i.e., "0" or "1"). Each column may be coupled to a sense amplifier or a plurality of column multiplexers 114 may be used to multiplex the columns of bit lines 106 to a single sense amplifier, thereby reducing the number of sense amplifiers required. The column decoder 112 may also send information to write circuitry (not shown in FIG. 1) for writing data into the selected memory cell 102 during a write operation. The SRAM array 100 also includes precharge circuitry 116, which will be described further below.

FIG. 2 illustrates an exemplary architecture of a single column 200 of the SRAM array 100 of FIG. 1 in more detail. Column 200 includes precharge circuitry 116, a plurality of memory cells 102, a plurality of word lines 104, a pair of bit lines 106a and 106b (referred to as "bl" bit line 106a and "blb" bit line 106b, respectively, and collectively as bit lines 106), a column multiplexer 114, and a sense amplifier 204. When the SRAM array 100 is inactive (i.e., no read or write operation), the precharge circuitry 116 is enabled, maintaining a high voltage on the bit lines 106. When a read operation occurs, the precharge circuitry 116 is disabled and the single wordline 104 is enabled (i.e., current flows through the wordline 104). When a word line 104 is enabled, an individual memory cell 102 is able to change the voltage on the corresponding bit line 106 ("bl" and "blb").

Fig. 2 shows a detailed view of circuitry 202 of the most common type of memory cell 102(6T cell) of the SRAM array 100. Circuitry 202 includes latches, where one side stores a high logic value and the other side stores a low logic value. When the access transistor of circuitry 202 is enabled by the current on word line 104, circuitry 202 affects bit line 106 by discharging one of bit lines 106 "bl" or "blb" depending on which side of the latch stores a low logic value.

The memory cells 102 of the SRAM array 100 are designed to be as small as possible so that the maximum number of memory cells 102, and thus information, is contained in a given area. Because the memory cell 102 is small, its transistors are inherently weak. In addition, bit line 106 spans the entire height of column 200 and is connected to each memory cell 102 in column 200. Thus, the bit line 106 has a high inherent parasitic capacitive load. As a result of the weak memory cell 102 and the large capacitance of the bit line 106, it may take a long time for the memory cell 102 to fully discharge. Furthermore, once discharged, the bit lines 106 need to be recharged by the precharge circuitry 116, which results in not little power consumption. The purpose of the sense amplifier 204 is to detect and amplify the small differential signal on the bit line 106 to identify the data value stored in the selected memory cell 102.

The operation of the sense amplifiers in the DRAM chip with additional functionality is similar to the operation of the sense amplifiers in the SRAM chip. The data in each memory cell of a DRAM chip is stored as a charge in a capacitor in the memory cell. A read operation of a particular memory cell depletes the charge in the cell, destroying the data. Thus, after data is read out, the sense amplifier writes it back into the cell by applying a voltage to the cell immediately, thereby charging the capacitor. This is called memory refresh.

The sense amplifier (e.g., sense amplifier 204) is driven by a sense amplifier enable ("saen") signal generated by a sense amplifier enable signal generator. To enable the sense amplifier to sense a voltage level across a pair of bit lines (e.g., bit lines 106a and 106b), the sense amplifier enable signal generator receives an external clock signal and generates a sense amplifier enable signal after a delay of a period of time. Upon receiving the sense amplifier enable signal, the sense amplifier may detect a voltage difference across the pair of bit lines.

Fig. 3 shows a circuit 300 including a conventional sense amplifier 302. Sense amplifier 302 (which may be an example of sense amplifier 204 in fig. 2) has nine transistors: five n-channel field effect transistors (NFETs) and four p-channel field effect transistors (PFETs). Two nor gates, an inverter, and two push-pull transistors are example logic gates that may be coupled to the sense amplifier 302. The two inputs "sain _ h" and "sain _ 1" are the outputs of a column multiplexer (e.g., column multiplexer 114) that feed into sense amplifiers 302. Signals "sain _ h" and "sain _ 1" represent signals on a pair of bit lines selected by the column multiplexer. The "saen" input is a sense amplifier enable signal that activates the sense amplifier 302. In addition, the "saen" signal feeds two PFETs (shown above and below the left of sense amplifier 302) that feed the output signals "sao _ h" and "sao _ 1".

When "saen" is "low" (i.e., logic "0"), the PFET drives a "high" (i.e., logic "1") value into the output signals "sao _ h" and "sao _ 1". This operation is referred to as precharging, and the two PFETs feeding the output signals "sao _ h" and "sao _ 1" are referred to as precharging transistors. Similarly, where "sain _ h" and "sain _ 1" begin with a "high" value, then during a read operation, "sain _ 1" will begin to discharge and "sain _ h" will remain "high". When "saen" becomes "high," sain _ h "remains" high, "which causes" sao _1 "to be pulled" low "through the NFET stack 304. The cross-coupled PFET keeps "sao _ h" high. The small discharge on "sain _ 1" can be amplified to full swing by the sense amplifier.

Fig. 4 illustrates a conventional system 400 that shows the divergence between the time a sense amplifier 402 receives a sense amplifier enable signal ("saen" in fig. 4) and the time during which the sense amplifier 402 can accurately evaluate the voltage across the bit lines ("saen _ h" and "saen _ l"). As described above, a memory cell (e.g., memory cell 102) in an SRAM array is typically comprised of two, four, or six transistors. In a 6T SRAM-based design, "contention" between the time the sense amplifier 402 receives the sense amplifier enable signal "saen" and the time during which the sense amplifier 402 can accurately evaluate the voltage difference across the bit line pair "saen _ h" and "saen _ 1" (to determine whether the memory cell being read contains a logic "0" or "1") is an important performance margin. The sense amplifier enable signal "saen" needs to reach the sense amplifier 402 so that the bit line differential (i.e., the voltage across the pair of bit lines "saen _ h" and "saen _ 1") is sufficient to satisfy the sense amplifier offset (i.e., the minimum voltage difference required on the bit lines for the sense amplifier to properly detect the voltage difference). In addition, the timing of the sense amplifier enable signal saen directly affects the delay of the SRAM output, where a longer delay in generating the sense amplifier enable signal saen results in a longer delay in reading the memory cell.

Furthermore, a six sigma statistical weak bit estimate needs to be used to track the sense amplifier enable signal. In macros with complex decoding, such as CAM-based decoding or predictive-based decoding, the divergent path between the bit line pair voltage difference and the arrival of the sense amplifier enable signal may be large, and therefore the OCV margin may also be large. This divergence increases the output delay of the SRAM array.

Typically, "rd _ bank _ clk" 404 (i.e., the clock within the memory bank (bank) array of the memory chip) serves as the divergence point 404 of the contention margin (path 401) because the sense amplifier enable signal generator 406 receives the clock signal from rd _ bank _ clk, and rd _ bank _ clk 404 also provides the voltage across the bit lines "saen _ h" and "saen _ 1" (path 403). However, in macros that require word/byte gating of the word lines, there may be multiple paths that determine the divergence point, and therefore, the main clock ("clk") (not shown) may also cause a delay. Also, dual voltage domains require that the margin span both the various array and logic domain voltages. More specifically, the low power memory uses a dual voltage domain architecture. In this architecture, the memory bitcell array is connected to a power supply with limited scalability (array power domain), while part of the peripherals and the rest of the logic are connected to a different fully scalable power supply (logic power domain). During low power operation, the logic power supply is reduced to a voltage much lower than the minimum voltage at which the bitcell can operate. Under this architecture, the word line and sense amplifier paths span two voltage domains and need to track each other over the entire power supply range.

In addition, the worst case sensing margin occurs at a low voltage level, which drives the turbo corner (i.e., the high voltage corner that sets the highest supported frequency) sense amplifier enable signal timing. More specifically, the increased variation at low voltage requires more margin at the low voltage corners and affects the timing of the sense amplifier enable signal at the turbo corners. Reducing the difference between the bit line evaluation and the sense amplifier enable signal can help to save OCV margin and improve the overall timing of the macro.

One way to simplify the timing of the sense amplifier enable signal is to reduce the divergence between the evaluation of the bit line pair voltage difference and the generation of the corresponding sense amplifier enable signal. A sub-array of 6T memory cells (e.g., memory cell 102) has pairs of bit lines evaluated at different speeds. For example, a bit line that is discharged by a weak bit and whose column multiplexer is ON evaluates the slowest. Conversely, a bit line that is discharged by a nominal bit and whose column multiplexer is OFF evaluates fastest.

The proposed solution is to trigger the sense amplifier enable signal from the bitline evaluation. In particular, a faster bit line evaluation triggers the sense amplifier enable signal to meet the margins of a slower bit line evaluation. Because the sense amplifier enable signal is generated using the bit line discharge, the divergent path between the bit line evaluation and the generation of the sense amplifier enable signal is eliminated.

Fig. 5 illustrates an example architecture 500 showing generation of a self-timed sense amplifier enable signal in accordance with at least one aspect of the present disclosure. In the example of fig. 5, the associated memory array (not shown, but may correspond to, for example, SRAM array 100) is a 96 x 64 array (96 rows and 64 columns). As shown in fig. 5, an even 48 x 2 data slice 502a and an odd 48 x 2 data slice 502b are read from the memory array. Together, these two slices of data (referred to as "half-banks") represent two entire columns (two columns, 96 rows total) of the memory array. However, it will be appreciated that this is merely an example configuration.

Two 48 x 2 data slices 502a and 502b (collectively referred to as data slices 502) are passed to corresponding multiplexers 504a and 504b (collectively referred to as multiplexers 504). Multiplexer 504 may be, for example, a four-input two-output multiplexer (referred to as an "rd collemux × 2" multiplexer) that has as input signals on four bit lines, particularly two pairs of bit lines (shown as "bl _ even < 1: 0 >", "blb _ even < 1: 0 >", "bl _ odd < 1: 0 >" and "blb _ odd < 1: 0 >", respectively), and outputs signals "sain _ h" and "sain _ 1" representing signals on a selected pair of bit lines. The sense amplifier 506 (which may correspond to the sense amplifier 302 in fig. 3) receives the output signals "sain _ h" and "sain _ 1" of the selected bit line pair from the multiplexer 504. Thus, rather than each column in the memory array being associated with its own sense amplifier, two columns (e.g., data slice 502) are associated with a single sense amplifier 506. Sense amplifier 506 also receives a sense amplifier enable ("saen") signal (the generation of which will be described below) to detect a voltage difference across signals "sain _ h" and "sain _ 1".

In architecture 500, two additional pairs of transistors 508a and 508b (e.g., p-channel metal oxide semiconductor (PMOS) transistors) may be used to generate sense amplifier enable signals based on the bit line discharge of each half bank (i.e., data slice 502). Each time a pair of bit lines in data slice 502 discharges, the discharge generates a signal on the "bl" and "blb" bit lines (as shown in fig. 2). On the even half-memory side (i.e., data slice 502a), the pair of transistors 508a receive as inputs "bl _ even" and "blb _ even" signals from a discharged pair of even bit lines, while on the odd side, the pair of transistors 508b receive as inputs "bl _ odd" and "blb _ odd" signals from a discharged pair of odd bit lines. These even and odd "bl" and "blb" signals generate sense amplifier enable signals when input to the corresponding transistors 508a and 508 b.

At the even half memory side (i.e., data slice 502a), the third transistor 510a is coupled to a "prog _ even _ clk" input, which when present, may be used to enable or disable the self-timed even sense amplifier enable signal generated by the pair of transistors 508 a. Likewise, on the odd half memory side (i.e., data slice 502b), the third transistor 510b is coupled to a "prog _ odd _ clk" input, which when present, may be used to disable the self-timed odd sense amplifier enable signal generated by the pair of transistors 508 b. The three transistors 508a/b (collectively referred to as transistors 508) and 510a/b (collectively referred to as transistors 510) coupled to each half bank are referred to herein as "transistor stacks" 512a/b (collectively referred to as transistor stacks 512). The strength of the third transistor 510 determines the speed at which the sense amplifier enable signal is generated in response to the discharge of the corresponding bl and blb bit lines. The strength of the transistor 510 may be adjusted to affect the sense amplifier margin. The strength can be adjusted by changing the effective size of the transistor 510 or controlling the gate voltage of the transistor 510 when it is turned on during a read operation.

In architecture 500, the outputs of transistor stacks 512 are coupled together to form a sense amplifier enable signal "saen" that is input to each sense amplifier 506 across the respective columns or data slices 502 of the memory array. The combined output of the transistor stack 512 may also be coupled to additional transistors/inputs. In particular, a sense amplifier enable signal (shown as "prog _ saen _ n") generated by conventional methods may be multiplexed with the self-timed sense amplifier enable signal generated by the transistor stack 512. Thus, the sense amplifier enable signal will be delayed during the self-timing mode and arrive early when the presence of prog _ saen _ n disables the self-timing mode. Further, to drop back (i.e., "reset") the self-timed sense amplifier enable signal, a "saen _ discharge _ clk" signal may be added to architecture 500. This signal will have the opposite polarity as the word line and therefore become active after the word line becomes "0". More specifically, the signal is an active low signal. Its rest value is "high" and goes "low" during a read operation where the word line is "high".

Fig. 6A illustrates an example architecture 600A that illustrates generation of a self-timed sense amplifier enable signal in accordance with at least one aspect of the present disclosure. Architecture 600A is a variation of architecture 500 in fig. 5. Similar to architecture 500 in fig. 5, the associated memory array (not shown, but may correspond to, for example, SRAM array 100) is a 96 x 64 array (96 rows and 64 columns). As shown in fig. 6A, an even 48 x 2 data slice 602a and an odd 48 x 2 data slice 602b are read from the memory array. Together, the two slices of data represent two entire columns of the memory array. However, it will be appreciated that this is merely an example configuration.

Two 48 x 2 data slices 602a and 602b (collectively referred to as data slices 602) are passed to corresponding multiplexers 604a and 604b (collectively referred to as multiplexers 504). As in fig. 5, multiplexer 604 may be, for example, a four-input two-output multiplexer (referred to as an "rd collexx 2" multiplexer) having as inputs signals on four bit lines, particularly two pairs of bit lines (shown as "bl _ even < 1: 0 >", "blb _ even < 1: 0 >", "bl _ odd < 1: 0 >" and "blb _ odd < 1: 0 >", respectively), and outputting signals "sain _ h" and "sain _ 1" representing signals on a selected pair of bit lines. Sense amplifier 606 (which may correspond to sense amplifier 702 in fig. 7) receives the output signals "sain _ h" and "sain _ 1" of the selected bit line pair and sense amplifier enable signals ("saen _ even" and "saen _ odd") (the generation of which will be described below) from multiplexer 604 in order to detect the voltage difference across signals "sain _ h" and "sain _ 1".

Like architecture 500, two additional pairs of transistors 608a and 608b (e.g., PMOS transistors) may be used to generate the sense amplifier enable signal based on the bit line discharge of each half bank (i.e., data slice 602). On the even half-bank side (i.e., data slice 602a), the pair of transistors 608a receive as inputs "bl _ even" and "blb _ even" signals from a discharged pair of even bit lines, while on the odd side, the pair of transistors 608b receive as inputs "bl _ odd" and "blb _ odd" signals from a discharged pair of odd bit lines. These even and odd "bl" and "blb" signals, when input to the corresponding transistor pairs 608a and 608b, generate sense amplifier enable signals "saen _ even" and "saen _ odd", respectively "

At the even half memory side (i.e., data slice 602a), a third transistor 610a is coupled to a "prog _ even _ clk" input, which when present, may be used to disable the self-timed even sense amplifier enable signal generated by the pair of transistors 608 a. Likewise, on the odd half memory side (i.e., data slice 602b), the third transistor 610b is coupled to a "prog _ odd _ clk" input, which when present, may be used to disable the self-timed odd sense amplifier enable signal generated by the pair of transistors 608 b. The three transistors 608a/b (collectively transistors 608) and 610a/b (collectively transistors 610) coupled to each half bank are referred to herein as "transistor stacks" 612a/b (collectively transistor stacks 612).

In architecture 600A, unlike architecture 500, a read may be performed in one of the data slices 602a and 602b of the memory array, and a write operation may be performed in the other of the data slices 602a and 602b of the memory array. Thus, in architecture 600A, the output of transistor stack 612a forms a sense amplifier enable signal "saen _ even" that is input to each sense amplifier 606 across the respective column of the memory array, and the output of transistor stack 612b forms a sense amplifier enable signal "saen _ odd" that is also input to each sense amplifier 606 across the respective column of the memory array.

Because of the even and odd amplifier enable signals, separate "prog _ even _ saen _ n" and "prog _ odd _ saen _ n" signals and separate "saen _ even _ discharge _ clk" and "saen _ odd _ discharge _ clk" signals are required, rather than the single "prog _ saen _ n" and "saen _ discharge _ clk" signals in architecture 500. In particular, the even and odd sense amplifier enable signals (shown as "prog _ even _ saen _ n" and "prog _ odd _ saen _ n") generated by conventional methods may be multiplexed with the even and odd self-timed sense amplifier enable signals generated by the transistor stack 612. Thus, the even and odd sense amplifier enable signals will be delayed during the self-timing mode and arrive in advance when the presence of prog _ even _ saen _ n and prog _ odd _ saen _ n disables the self-timing mode. Further, to reset the self-timed even and odd sense amplifier enable signals, the "saen _ even _ discharge _ clk" and "saen _ odd _ discharge _ clk" signals may be added to architecture 600A. These signals have opposite polarity to the corresponding word lines and thus become active after the word lines become "0".

Fig. 6B illustrates an example architecture 600B that illustrates generation of a self-timed sense amplifier enable signal in accordance with at least one aspect of the present disclosure. Architecture 600B is a variation of architecture 600A in fig. 6A. In architecture 600B, the program clock transistors (even program clock transistors 610a-0 and 610a-1 coupled to the "prog _ even _ clk <0 >" and "prog _ even _ clk <1 >" inputs, respectively, and odd program clock transistors 610B-0 and 610B-1 coupled to the "prog _ odd _ clk <0 >" and "prog _ odd _ clk <1 >" inputs, respectively) are configured to disable the common output ("saen _ even" or "saen _ odd") of the bl and blb transistors (either pair of transistors 608a or pair of transistors 608B) based on enabling a subset of the program clock transistors. More specifically, FIG. 6B shows two representative columns, where transistor heads in different columns are driven by different signals. For example, the transistor heads in the two columns of even sub-banks are driven by "prog _ even _ clk <1 >" and "prog _ even _ clk <0 >". Similarly, the transistor heads in the two columns of the odd sub-banks are driven by "prog _ odd _ clk <1 >" and "prog _ odd _ clk <0 >". In this way, a subset of program clock transistors 610a-0, 610a-1, 610b-0, and 610b-1 may be enabled.

Fig. 7 illustrates an example circuit 700 including a sense amplifier 702 according to an aspect of this disclosure. Sense amplifier 702 may correspond to sense amplifier 606 in fig. 6A capable of receiving two sense amplifier enable signals. The sense amplifier 702 is similar to the sense amplifier 302 of FIG. 3, but includes two additional transistors to receive the second sense amplifier enable signal. Specifically, sense amplifier 702 includes a first pair of PFETs (shown above and below the left of sense amplifier 702) that receive an even sense amplifier enable signal ("saen _ even") and a second pair of PFETs (also above and below the left of sense amplifier 702) that receive an odd sense amplifier enable signal ("saen _ odd").

These two signals are mutually exclusive: one of them becomes valid depending on whether an even half bank array column or an odd half bank array column (e.g., data slice 602) is read. More specifically, prior to a read operation, the "saen _ even" (or "saen _ odd") signal is "low", thereby placing the sense amplifier output in a precharged state. When reading an even (or odd) column, "saen _ even" (or "saen _ odd") goes "high", which allows the sense amplifier 702 to sense in the voltage difference between "sain _ 1" and "sain _ r" (the output of the column multiplexer (e.g., column multiplexer 114) that feeds into the sense amplifier 702) and capture and output it as a full swing from 1 to 0 (or vice versa). Since the precharge transistors (i.e., the four PFETs feeding the output signals "sao h" and "sao 1") must be disconnected from the output signal when either sense amplifier enable signal goes "high", each output signal "sao h" and "sao 1" is connected in series to two such PFETs, each PFET connected to one (even or odd) sense amplifier enable signal.

Fig. 8 is a diagram 800 illustrating timing of various signals in accordance with at least one aspect of the present disclosure. As shown in fig. 8, the signals are part of a read operation. The first row 802 shows that the local word line "lwl _ odd <47 >" goes "high," which indicates an active word line. The second row 804 shows the bit lines discharging at a different rate. The third row 806 shows "prog _ odd _ clk" going "low" to enable the PFET stack (e.g., transistor stack 512a in fig. 5) to drive the sense amplifier enable signal "saen _ odd". The fourth row 808 indicates "prog _ odd _ saen _ n," which is a programmable sense amplifier enable signal that may be multiplexed with the output of the PFET stack. The fifth row 810 represents "saen _ odd _ discharge _ clk", "saen _ odd _ discharge _ clk" resets "saen _ odd". The sixth row 812 shows the "saen _ odd" signal, which feeds the input of the sense amplifier.

Existing methods for generating sense amplifier enable signals use logic gates such as inverters, nand gates, nor gates, and the like. The processing variations of conventional logic gates are different from 6T SRAM bit cells. Since the proposed solution uses SRAM bit cell delay to generate the sense amplifier enable signal, it tracks a much better process corner than the existing approaches.

FIG. 9 illustrates an example method 900 of operating a memory system in accordance with an aspect of the present disclosure. At 910, method 900 includes: at a bl transistor (e.g., the bl transistor in the pair of transistors 508) electrically coupled to a first bit line (e.g., the bit line 106a in fig. 2) associated with a column (e.g., the column 200 in fig. 2) of a memory array (e.g., the SRAM array 100), a first electrical signal is received from the first bit line based on the first bit line being discharged. At 920, method 900 includes: at a blb transistor (e.g., the blb transistor in the pair of transistors 508) electrically coupled to a second bit line (e.g., the bit line 106b in fig. 2) associated with a column of the memory array, a second electrical signal is received from the second bit line based on the second bit line being discharged. In one aspect, the output of the bl transistor and the output of the blb transistor are combined into a common output (e.g., the common output of the pair of transistors 508). At 930, method 900 includes: the common output of the bl transistor and the blb transistor is received as a sense amplifier enable signal at a sense amplifier (e.g., sense amplifier 506 of fig. 5) electrically coupled to the first bit line and the second bit line. At 940, method 900 includes: a voltage difference across the first bit line and the second bit line is measured by a sense amplifier based on receipt of a sense amplifier enable signal.

It will be understood that any reference herein to elements using a name such as "first," "second," etc., does not generally limit the number or order of such elements. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, references to a first element and a second element do not imply that only two elements may be used therein, nor that the first element must precede the second element in some manner. In addition, a set of elements can include one or more elements unless otherwise specified. In addition, the term in the form of "at least one of A, B or C" or "one or more of A, B or C" or "at least one of the group consisting of A, B and C" as used in the specification or claims means "a or B or C or any combination of these elements". For example, the term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, and the like.

In view of the above description and explanation, those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Thus, it will be appreciated that the apparatus or any component of the apparatus may be configured (or made operable or adapted) to provide the functionality taught herein, for example. This can be achieved, for example, by: machining (e.g., manufacturing) the device or component to enable it to provide functionality; programming a device or component to enable it to provide a function; or using some other suitable implementation technique. As one example, an integrated circuit may be fabricated to provide the necessary functionality. As another example, an integrated circuit may be manufactured to support the necessary functionality and then configured (e.g., via programming) to provide the necessary functionality. As yet another example, the processor circuit may execute code to provide the necessary functionality.

While the foregoing disclosure shows various illustrative aspects, it should be noted that various changes and modifications could be made to the examples shown without departing from the scope defined by the appended claims. The present disclosure is not intended to be limited to the specifically illustrated examples only. For example, the functions, steps and/or actions of the method claims in accordance with the aspects of the disclosure described herein need not be performed in any particular order unless otherwise specified. Furthermore, although some aspects may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.