阅读说明：本技术 存储单元、晶体管的制备方法及存储单元的制备方法 (Memory cell, preparation method of transistor and preparation method of memory cell ) 是由 陈静 吕迎欢 王硕 葛浩 谢甜甜 于 2020-04-22 设计创作，主要内容包括：本申请实施例提供了一种存储单元、晶体管的制备方法及存储单元的制备方法,其中,该存储单元是通过第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管,第七晶体管和第八晶体管,这八个晶体管的电性连接得到的具有特定功能的存储单元。本发明公开的存储单元相较于现有技术中的存储单元,在传统六管单元的基础上加入两个晶体管,以牺牲较小单元面积的情况下提升单元抗单粒子能力；该存储单元中的晶体管均采用“工”字型的栅氧层和金属栅结构,可有效抑制总剂量效应引起的上下边角漏电及侧壁漏电和寄生晶体管效应。此外,该存储单元不仅可以在抗单粒子效应能力上得到提高,还可以在存储数据的稳定性上得到增加。(The embodiment of the application provides a memory cell, a preparation method of a transistor and a preparation method of the memory cell, wherein the memory cell is a memory cell with a specific function obtained by electrically connecting a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. Compared with the memory cell in the prior art, the memory cell disclosed by the invention has the advantages that two transistors are added on the basis of the traditional six-tube cell, so that the single particle resistance of the cell is improved under the condition of sacrificing small cell area; the transistors in the storage unit all adopt I-shaped gate oxide layers and metal gate structures, and can effectively inhibit the upper and lower corner electric leakage, the side wall electric leakage and the parasitic transistor effect caused by the total dose effect. In addition, the memory cell can not only improve the single event effect resistance, but also increase the stability of stored data.)

1. A memory cell, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

gate oxide layers and metal gate layers in the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all of I-shaped structures;

a first end of the first transistor is connected with a first end of the second transistor, a second end of the first transistor is connected with a first end of the third transistor, and a third end of the first transistor is connected with a first end of the fifth transistor;

a second end of the second transistor is connected with a first end of the fourth transistor, and a third end of the second transistor is connected with a first end of the sixth transistor;

the third end of the third transistor is connected with the second end of the fifth transistor and the third end of the second transistor;

the third end of the fourth transistor is connected with the second end of the sixth transistor and the third end of the first transistor;

a first end of the seventh transistor is connected with a third end of the third transistor;

and the first end of the eighth transistor is connected with the third end of the fourth transistor.

2. The memory cell of claim 1, further comprising: a word line, a first bit line and a second bit line;

a first end of the first transistor is connected with the word line, a first end of the second transistor is connected with the word line, a second end of the seventh transistor is connected with the word line, and a second end of the eighth transistor is connected with the word line;

a third end of the seventh transistor is connected with the first bit line;

and the third end of the eighth transistor is connected with the second bit line.

3. The memory cell of claim 1, wherein a power supply is pulled up to a second terminal of the third transistor;

and the second end of the fourth transistor is connected with a power supply in a pulling mode.

4. The memory cell according to claim 1, wherein a third terminal of the fifth transistor is grounded;

and the third end of the sixth transistor is grounded.

5. The memory cell of claim 1, wherein the first transistor and the second transistor are both N-type field effect transistors.

6. The memory cell of claim 1, wherein the third transistor and the fourth transistor are both P-type field effect transistors.

7. The memory cell of claim 1, wherein the fifth transistor and the sixth transistor are both N-type field effect transistors.

8. The memory cell according to claim 1, wherein the seventh transistor and the eighth transistor are both N-type field effect transistors;

the seventh transistor and the eighth transistor are both gate tubes.

9. A method for manufacturing a transistor in a memory cell, comprising the steps of:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the transistor;

carrying out first doping on the active region to form a doping type required by a channel; the first doping comprises any one of N-type doping or P-type doping;

preparing and forming a gate oxide layer on the active region; the shape of the gate oxide layer is I-shaped;

defining a source end region and a drain end region on the active region; carrying out second doping with the opposite type of the first doping on the source end region and the drain end region to form a source end and a drain end;

preparing and forming a metal gate layer on the gate oxide layer; the shape of the metal gate layer is consistent with that of the gate oxide layer;

and respectively leading out the source end, the drain end and the metal gate layer.

10. A method of making a memory cell, comprising the steps of:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the storage unit;

preparing and forming a first transistor, a fifth transistor and a seventh transistor in a first area of the active area, preparing and forming a third transistor and a fourth transistor in a second area of the active area, and preparing and forming a second transistor, a sixth transistor and an eighth transistor in a third area of the active area;

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type field effect transistors, and the third transistor and the fourth transistor are all P-type field effect transistors;

the shapes of the gate oxide layer and the metal gate layer of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are I-shaped;

and manufacturing a metal through hole and a corresponding metal connecting line, and preparing to form the storage unit.

And respectively leading out the source end, the drain end and the metal gate layer.

Technical Field

The invention relates to the field of integrated circuits, in particular to a memory cell, a preparation method of a transistor and a preparation method of the memory cell.

Background

Generally, in a computer system, a Random access memory (DRAM) and a Static RAM (SRAM) are commonly used, and the difference between the DRAM and the SRAM is that the DRAM needs to be refreshed by a memory control circuit according to a certain period to maintain data storage, and the SRAM can also store internally stored data without a refresh circuit during the operation of the computer system. Therefore, the SRAM is widely used because of its good performance.

Disclosure of Invention

The invention provides a memory cell, a preparation method of a transistor and a preparation method of the memory cell, which can improve the single event effect resistance of the memory cell and enhance the stability of the memory cell.

An embodiment of the present application provides a memory cell, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

the gates of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor isolate the channel from the field oxide;

the first end of the first transistor is connected with the first end of the second transistor, the second end of the first transistor is connected with the first end of the third transistor, and the third end of the first transistor is connected with the first end of the fifth transistor;

the second end of the second transistor is connected with the first end of the fourth transistor, and the third end of the second transistor is connected with the first end of the sixth transistor;

the third end of the third transistor is connected with the second end of the fifth transistor and the third end of the second transistor;

the third end of the fourth transistor is connected with the second end of the sixth transistor and the third end of the first transistor;

the first end of the seventh transistor is connected with the third end of the third transistor;

and the first end of the eighth transistor is connected with the third end of the fourth transistor.

Further, the unit further comprises: a word line, a first bit line and a second bit line;

the first end of the first transistor is connected with the word line, the first end of the second transistor is connected with the word line, the second end of the seventh transistor is connected with the word line, and the second end of the eighth transistor is connected with the word line;

the third end of the seventh transistor is connected with the first bit line;

and the third end of the eighth transistor is connected with the second bit line.

The memory cell in the embodiment of the present application can be used as a memory cell of a static random access memory.

Further, a second end of the third transistor is connected with a power supply in a pulling mode; the second terminal of the fourth transistor is connected with a power supply in a pulling mode.

Further, a third terminal of the fifth transistor is grounded; and the third end of the sixth transistor is grounded.

Further, the first transistor and the second transistor are both N-type field effect transistors.

Further, the third transistor and the fourth transistor are both P-type field effect transistors.

Further, the fifth transistor and the sixth transistor are both N-type field effect transistors.

Further, the seventh transistor and the eighth transistor are both N-type field effect transistors, and the seventh transistor and the eighth transistor are both gate transistors.

Correspondingly, the embodiment of the application also provides a preparation method of the transistor in the memory unit, which comprises the following steps:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the transistor;

carrying out first doping on the active region to form a doping type required by a channel; the first doping comprises any one of N-type doping or P-type doping;

preparing and forming a gate oxide layer on the active region; the shape of the gate oxide layer is I-shaped;

defining a source end region and a drain end region on the active region; carrying out second doping with the opposite type of the first doping on the source end region and the drain end region to form a source end and a drain end;

preparing and forming a metal gate layer on the gate oxide layer; the shape of the metal gate layer is consistent with that of the gate oxide layer;

and respectively leading out the source end, the drain end and the metal gate layer.

Correspondingly, the embodiment of the application also provides a preparation method of the storage unit, which comprises the following steps:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the storage unit;

preparing and forming a first transistor, a fifth transistor and a seventh transistor in a first area of the active area, preparing and forming a third transistor and a fourth transistor in a second area of the active area, and preparing and forming a second transistor, a sixth transistor and an eighth transistor in a third area of the active area;

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type field effect transistors, and the third transistor and the fourth transistor are all P-type field effect transistors;

the shapes of the gate oxide layer and the metal gate layer of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are I-shaped;

and manufacturing a metal through hole and a corresponding metal connecting line, and preparing to form the storage unit.

The embodiment of the invention has the following beneficial effects:

compared with the memory cell in the prior art, the memory cell disclosed by the invention has the advantages that two transistors (the first transistor and the second transistor) are added on the basis of the traditional six-transistor cell, so that the single particle resistance of the cell is improved under the condition of sacrificing small cell area; the transistors in the storage unit all adopt I-shaped gate oxide layers and metal gate structures, and can effectively inhibit the upper and lower corner electric leakage, the side wall electric leakage and the parasitic transistor effect caused by the total dose effect. In addition, the memory cell can not only improve the single event effect resistance, but also increase the stability of stored data.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic circuit diagram of a prior art six-transistor static memory cell according to an embodiment of the present application;

FIG. 2 is a circuit diagram of a memory cell according to an embodiment of the present disclosure;

FIG. 3 is a schematic top view of a memory cell according to an embodiment of the present disclosure after doping an active region of a transistor;

FIG. 4 is a schematic diagram illustrating the distribution of transistors in each region of the active region of a memory cell according to an embodiment of the present disclosure;

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the embodiments of the application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that "embodiment" as referred to herein refers to a particular feature, structure, or characteristic that may be included in at least one implementation of an embodiment of the present application. In the description of the embodiments of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated, whereby features defined as "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" may explicitly or implicitly include one or more of such features. Also, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," and "eighth" are used for distinguishing between similar elements and not for describing a particular sequential or chronological order, and it is to be understood that such usage data may be interchanged where appropriate. Furthermore, the terms "comprises" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a list of elements does not necessarily limit the order in which they are listed, but may include elements not expressly listed or inherent to such elements.

Referring to fig. 2, a circuit diagram of a memory cell according to an embodiment of the present application is shown, where the circuit diagram includes: a first transistor 1, a second transistor 2, a third transistor 3, a fourth transistor 4, a fifth transistor 5, a sixth transistor 6, a seventh transistor 7 and an eighth transistor 8, wherein the gates of the first transistor 1, the second transistor 2, the third transistor 3, the fourth transistor 4, the fifth transistor 5, the sixth transistor 6, the seventh transistor 7 and the eighth transistor 8 isolate the channel from the field oxide, the first end 11 of the first transistor 1 is connected with the first end 21 of the second transistor 2, the second end 12 of the first transistor 1 is connected with the first end 31 of the third transistor 3, the third end 13 of the first transistor 1 is connected with the first end 51 of the fifth transistor 5, the second end 22 of the second transistor 2 is connected with the first end 41 of the fourth transistor 4, the third end 23 of the second transistor 2 is connected with the first end 61 of the sixth transistor 6, the second end 32 of the third transistor 3 is connected with the power source, the third terminal 33 of the third transistor 3 is connected to the second terminal 52 of the fifth transistor 5 and to the third terminal 23 of the second transistor 2, the second terminal 42 of the fourth transistor 4 is pulled up to the power supply, the third terminal 43 of the fourth transistor 4 is connected to the second terminal 62 of the sixth transistor 6 and to the third terminal 13 of the first transistor 1, the third terminal 53 of the fifth transistor 5 is grounded, the third terminal 63 of the sixth transistor 6 is grounded, the first terminal 71 of the seventh transistor 7 is connected to the third terminal 33 of the third transistor 3, and the first terminal 81 of the eighth transistor 8 is connected to the third terminal 43 of the fourth transistor 4.

In the embodiment of the present application, the memory cell further includes a word line WL, a first bit line BL, and a second bit line BLB. The first terminal 11 of the first transistor 1 is connected to the word line WL, the first terminal 21 of the second transistor 2 is connected to the word line WL, the second terminal 72 of the seventh transistor 7 is connected to the word line WL, the second terminal 82 of the eighth transistor 8 is connected to the word line WL, the third terminal 73 of the seventh transistor 7 is connected to the first bit line BL, and the third terminal 83 of the eighth transistor 8 is connected to the second bit line BLB.

In the embodiment of the present application, the first transistor 1 and the second transistor 2 are both N-type field effect transistors, the third transistor 3 and the fourth transistor 4 are both P-type field effect transistors, the fifth transistor 5 and the sixth transistor 6 are both N-type field effect transistors, the seventh transistor 7 and the eighth transistor 8 are both N-type field effect transistors, and the seventh transistor 7 and the eighth transistor are both gate transistors, so as to implement data storage.

Compared with the memory cell in the prior art, the memory cell provided by the embodiment of the application is added with two N-type transistors (a first transistor 1 and a second transistor 2) on the basis of the traditional six-transistor cell so as to improve the single particle resistance of the cell under the condition of sacrificing a small cell area; the transistors in the storage unit all adopt I-shaped gate oxide layers and metal gate structures, and can effectively inhibit the upper and lower corner electric leakage, the side wall electric leakage and the parasitic transistor effect caused by the total dose effect. In addition, the memory cell can not only improve the single event effect resistance, but also increase the stability of stored data.

Several embodiments of the operating state of the memory cell are described below based on the memory cell shown in fig. 2. Presetting a storage unit in a holding state, namely a word line WL is in a '0' state, bombarding transistors in the storage unit through energetic particles, forming two inverters by a third transistor 3, a fourth transistor 4, a fifth transistor 5 and a sixth transistor, wherein a sensitive node in the storage unit is the drain terminals of four transistors in the two inverters, and the drain terminals of two transistors can cause inversion under one storage condition. Assume that point Q is high and point QB is low. At this time, the sensitive node is a reverse-biased junction of the drains of the fifth transistor 5 and the second transistor 2.

In an optional implementation manner, high-energy particles bombard the fifth transistor 5, the fifth transistor 5 generates a transient current to pull down the voltage of the Q point, because the second transistor 2 is in an off state, which can be regarded as a resistor with a very large resistance value, the voltage of the Q2 point is slowly reduced, and the voltage of the QB point is slowly increased, so that the delay of the feedback loop can be increased, and meanwhile, because the first transistor 1 is also in an off state, the QB2 point maintains the original low voltage, the third transistor 3 is turned on, the charging of the Q point is realized, and further, the anti-overturning capability of the storage units 1 to 0 can be greatly improved.

In another alternative embodiment, the high-energy particles bombard the fourth transistor 4, the fourth transistor 4 generates transient current to raise the potential of the QB point, and then the fifth transistor 5 is turned on and performs discharge operation on the Q point, and since the second transistor 2 is in an off state, it can be regarded as a resistor with a very large resistance value, so that the voltage at the Q2 point is slowly reduced, thereby increasing the delay of the feedback loop and improving the turning capability of the memory cell 0 to 1.

A method of fabricating a single transistor in a memory cell is described based on the memory cell depicted in fig. 2, the method comprising the steps of:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the transistor;

carrying out first doping on the active region to form a doping type required by a channel; the first doping comprises any one of N-type doping or P-type doping;

preparing and forming a gate oxide layer on the active region; the shape of the gate oxide layer is I-shaped;

defining a source end region and a drain end region on the active region; carrying out second doping with the opposite type of the first doping on the source end region and the drain end region to form a source end and a drain end;

preparing and forming a metal gate layer on the gate oxide layer; the shape of the metal gate layer is consistent with that of the gate oxide layer; a schematic top view of a single transistor in a memory cell is shown in fig. 3. In fig. 3, the shape of the metal gate layer may be "i" shape, wherein the part filled with oblique lines is the metal gate layer, and the parts not filled are the source terminal and the drain terminal of the transistor, respectively.

And respectively leading out the source end, the drain end and the metal gate layer.

In the embodiment of the present application, when the first doping is N-type doping and the second doping is P-type doping, the P-type field effect transistor is obtained, and when the first doping is P-type doping and the second doping is N-type doping, the N-type field effect transistor is obtained.

In the embodiment of the application, the shape of the metal gate layer and the shape of the gate oxide layer are in an I shape, and the doping of the active region under the gate oxide layer can be reserved when the active region is subjected to second doping, so that the active regions are formed on two sides of a channel, the upper and lower corner electric leakage, the side wall electric leakage and the parasitic transistor effect caused by the total dose effect can be effectively inhibited, and the capability of resisting the total ionizing radiation dose effect is improved.

The method for manufacturing the memory cell is introduced on the basis of the memory cell described in fig. 2, and comprises the following steps:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the storage unit;

preparing and forming a first transistor, a fifth transistor and a seventh transistor in a first area of the active area, preparing and forming a third transistor and a fourth transistor in a second area of the active area, and preparing and forming a second transistor, a sixth transistor and an eighth transistor in a third area of the active area;

wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type field effect transistors, and the third transistor and the fourth transistor are all P-type field effect transistors;

the shapes of the gate oxide layer and the metal gate layer of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are I-shaped; fig. 3 is a schematic top view of a memory cell after doping an active region of a single transistor, and the shape of a metal gate layer in fig. 3 can be an i shape, wherein a part filled with oblique lines is the metal gate layer, and a part not filled with oblique lines is a source terminal and a drain terminal of the transistor respectively.

And manufacturing a metal through hole and a corresponding metal connecting line, and preparing to form the storage unit. A

The principle of the single transistor manufacturing process in the embodiment of the present application can be applied to the manufacturing of the transistor in the memory cell.

In the embodiment of the present application, the memory cell is formed by using a 22nm FDSOI (fully depleted SOI) process, and the preparation steps are described in detail as follows:

obtaining an SOI substrate, wherein the SOI substrate comprises a substrate, an oxygen buried layer and a top silicon film;

etching the top silicon film to form a shallow trench isolation structure; the shallow trench isolation structure is used for isolating an active region in the storage unit;

a first transistor, a fifth transistor and a seventh transistor are defined and prepared in a first area of the active area, a third transistor and a fourth transistor are defined and prepared in a second area of the active area, a second transistor, a sixth transistor and an eighth transistor are prepared in a third area of the active area, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all N-type field effect transistors, and the third transistor and the fourth transistor are all P-type field effect transistors:

p-type doping is carried out on the first region of the active region to form channels of a first transistor, a fifth transistor and a seventh transistor respectively; n-type doping is carried out on the second area of the active area to form channels of a third transistor and a fourth transistor respectively; performing P-type doping on a third region of the active region to form channels of a second transistor, a sixth transistor and an eighth transistor respectively, wherein the first region, the second region and the third region are three regions on the same plane;

preparing gate oxide layers for forming the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor, respectively; the shape of the gate oxide layer is I-shaped;

defining source and drain regions of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors, respectively;

n-type doping is carried out on the first region and the third region, P-type doping is carried out on the second region, and source terminals and drain terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are formed;

preparing and forming a metal gate layer on the gate oxide layer; the shape of the metal gate layer is consistent with that of the gate oxide layer;

leading out the source end, the drain end and the metal gate layer of each transistor;

and manufacturing a metal through hole and a corresponding metal connecting line, and preparing to form the storage unit.

The position distribution diagram of the transistor in each area of the active area in the memory cell prepared based on the preparation method of the memory cell is shown in FIG. 4, and the first area, the second area and the third area are sequentially arranged from left to right;

it should be noted that: the foregoing descriptions of the embodiments of the present application are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be implemented.

All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments.

Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in a computer readable medium.

The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiment of the present application, and these modifications and decorations are also considered to be the protection scope of the embodiment of the present application.