阅读说明：本技术 一种三维存储器及制造方法 (Three-dimensional memory and manufacturing method ) 是由 左青云 赵宇航 李铭 于 2020-05-19 设计创作，主要内容包括：本发明公开了一种三维存储器,包括：形成在衬底上的多层水平导电电极,以及形成在所述水平导电电极之间的隔离介质层；所述水平导电电极之间竖直设有两个多层结构,两个所述多层结构的内侧设有竖直导电电极,所述多层结构由外而内包括选通管材料层、中间导电电极和存储材料层,所述水平导电电极连接所述选通管材料层,所述竖直导电电极连接所述存储材料层,所述隔离介质层从外侧将所述选通管材料层和中间导电电极隔断。本发明与CMOS工艺兼容,能够实现垂直三维1S1R存储器件,有效提升存储器密度,并有利于降低成本。本发明还公开了一种三维存储器制造方法。(The invention discloses a three-dimensional memory, comprising: the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; the horizontal conductive electrode is vertically provided with two multilayer structures, the inner sides of the multilayer structures are provided with vertical conductive electrodes, the multilayer structures comprise a gate tube material layer, a middle conductive electrode and a storage material layer from outside to inside, the horizontal conductive electrode is connected with the gate tube material layer, the vertical conductive electrode is connected with the storage material layer, and an isolation medium layer is used for isolating the gate tube material layer from the outside and the middle conductive electrode. The invention is compatible with CMOS technology, can realize a vertical three-dimensional 1S1R memory device, effectively improves the density of the memory and is beneficial to reducing the cost. The invention also discloses a manufacturing method of the three-dimensional memory.)

1. A three-dimensional memory, comprising:

the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; the horizontal conductive electrode is vertically provided with two multilayer structures, the inner sides of the multilayer structures are provided with vertical conductive electrodes, the multilayer structures comprise a gate tube material layer, a middle conductive electrode and a storage material layer from outside to inside, the horizontal conductive electrode is connected with the gate tube material layer, the vertical conductive electrode is connected with the storage material layer, and an isolation medium layer is used for isolating the gate tube material layer from the outside and the middle conductive electrode.

2. The three-dimensional memory according to claim 1, wherein a gate tube is formed by the horizontal conductive electrode, the gate tube material layer and the middle conductive electrode, a memory cell is formed by the middle conductive electrode, the memory material layer and the vertical conductive electrode, and the gate tube and the memory cell are connected in series through the middle conductive electrode.

3. The three-dimensional memory according to claim 2, wherein the memory material layer comprises a resistive memory material layer or a phase change memory material layer.

4. The three-dimensional memory according to claim 1, wherein the isolation medium layer material comprises a solid isolation medium or a gas isolation medium.

5. The three-dimensional memory according to claim 1, wherein an insulating dielectric layer is disposed between the substrate and the plurality of horizontal conductive electrodes.

6. The three-dimensional memory according to claim 1, wherein a protective dielectric layer is disposed on the plurality of horizontal conductive electrodes, and the protective dielectric layer is interrupted by the plurality of layers.

7. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

step S01: providing a substrate, and alternately forming a plurality of layers of horizontal conductive electrodes and sacrificial dielectric layers on the substrate;

step S02: forming a groove downwards to penetrate through the plurality of layers of horizontal conductive electrodes and the sacrificial dielectric layers;

step S03: forming a gate tube material layer, a middle conductive electrode and a storage material layer in sequence along the inner wall of the groove to form a multilayer structure, and forming a vertical conductive electrode on the storage material layer;

step S04: removing the sacrificial dielectric layer;

step S05: continuously removing the gate tube material layer and the middle conductive electrode material at the junction with the sacrificial medium layer to form a gate tube structure which is isolated from each other in the vertical direction;

step S06: and filling an isolation dielectric layer between the horizontal conductive electrodes.

8. The method according to claim 7, wherein the memory material layer comprises a resistive memory material layer or a phase change memory material layer.

9. The method of claim 7, wherein in step S06, an isolation dielectric layer is formed by filling a solid isolation dielectric or a gas isolation dielectric between the horizontal conductive electrodes.

10. The method as claimed in claim 7, wherein the sacrificial dielectric layer in step S04 and the gate tube material layer and the middle conductive electrode material in step S05 are removed by chemical etching or remote plasma etching.

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to a three-dimensional memory and a method for manufacturing the same.

Background

Memory is one of the core components of modern information technology, and the global market has exceeded $ 700 billion. The amount of data required to be stored and processed in the big data era has increased at about 60% per year, reaching 40ZB in 2020. Therefore, it is necessary to develop a high-speed, high-density, low-power-consumption memory technology, expand the memory-logic fusion function thereof, and develop an efficient computing system.

With the arrival of the big data era, the two-dimensional architecture for improving the storage density of mass data in a planar micro mode is far from meeting the requirements of data explosion type growth on high density and high capacity of a storage, and three-dimensional integration gradually becomes the mainstream development trend of the future storage technology.

At present, the main three-dimensional memory on the market is 3D NAND Flash, and the mainstream technology is 64-96 layers. It is expected that 128-layer 3D NAND Flash will also come into the world soon and be used on a large scale.

With the development of integrated circuits along with moore's law, the speed of signal processing chips such as CPUs is faster and faster, but the working speed of mainstream memories cannot be correspondingly increased. The problem of "storage walls" is therefore increasingly apparent and exacerbated. The development speed of the memory is faster, the power consumption is lower, and the density is higher, wherein various new memories are expected.

The novel memory has the advantages of low power consumption, high speed and the like, and can be integrated in a three-dimensional mode. Common three-dimensional integration approaches include planar stacked three-dimensional integration approaches and vertical three-dimensional integration approaches. The vertical three-dimensional integration mode has obvious advantages in the case of integration with a large number of layers because the vertical three-dimensional integration mode can realize three-dimensional integration by using fewer photomasks. Due to leakage channel crosstalk in the crossbar array, it is necessary to connect the memory device and the gate device in series to form a gate tube, a 1S1R cell of a memory device (one selector one resistor, 1S1R), or to prepare a self-selecting memory device with self-gating.

For the 1S1R memory cell, a metal electrode (electrode two) 03 is disposed between the gate line containing the gate material layer 02 and the memory device containing the memory material layer 04, and two metal electrodes (electrode one, electrode three) 01, 05 are disposed on both sides of the whole cell, as shown in fig. 10. Thus, in the prior art, three-dimensional integration is typically achieved by planar stacking, such as "3D-Xpoint" distributed by Intel and magnesium optics. If vertical three-dimensional integration is adopted, the metal electrode (electrode two) 03 in the middle of the array cannot work normally in the array due to the difficulty in patterning.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned defects in the prior art, and provides a three-dimensional memory and a manufacturing method thereof, so as to solve the problem that the conventional 1S1R cell structure cannot be vertically integrated in three dimensions, achieve a high-density three-dimensional memory, and reduce the cost.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a three-dimensional memory, comprising:

the device comprises a substrate, a plurality of layers of horizontal conductive electrodes formed on the substrate, and an isolation medium layer formed between the horizontal conductive electrodes; the horizontal conductive electrode is vertically provided with two multilayer structures, the inner sides of the multilayer structures are provided with vertical conductive electrodes, the multilayer structures comprise a gate tube material layer, a middle conductive electrode and a storage material layer from outside to inside, the horizontal conductive electrode is connected with the gate tube material layer, the vertical conductive electrode is connected with the storage material layer, and an isolation medium layer is used for isolating the gate tube material layer from the outside and the middle conductive electrode.

Furthermore, the horizontal conductive electrode, the gate tube material layer and the middle conductive electrode form a gate tube, the middle conductive electrode, the storage material layer and the vertical conductive electrode form a storage unit, and the gate tube is connected with the storage unit in series through the middle conductive electrode.

Further, the memory material layer comprises a resistance change memory material layer or a phase change memory material layer.

Further, the isolation medium layer material comprises a solid isolation medium or a gas isolation medium.

Further, an insulating medium layer is arranged between the substrate and the plurality of horizontal conductive electrodes.

Furthermore, a protective dielectric layer is arranged on the multiple layers of horizontal conductive electrodes and is separated by the multiple layers of structures.

A method of fabricating a three-dimensional memory, comprising the steps of:

step S01: providing a substrate, and alternately forming a plurality of layers of horizontal conductive electrodes and sacrificial dielectric layers on the substrate;

step S02: forming a groove downwards to penetrate through the plurality of layers of horizontal conductive electrodes and the sacrificial dielectric layers;

step S03: forming a gate tube material layer, a middle conductive electrode and a storage material layer in sequence along the inner wall of the groove to form a multilayer structure, and forming a vertical conductive electrode on the storage material layer;

step S04: removing the sacrificial dielectric layer;

step S05: continuously removing the gate tube material layer and the middle conductive electrode material at the junction with the sacrificial medium layer to form a gate tube structure which is isolated from each other in the vertical direction;

step S06: and filling an isolation dielectric layer between the horizontal conductive electrodes.

Further, the memory material layer comprises a resistance change memory material layer or a phase change memory material layer.

Further, in step S06, an isolation medium layer is formed by filling a solid isolation medium or a gas isolation medium between the horizontal conductive electrodes.

Further, the sacrificial medium layer in the step S04, the gate tube material layer in the step S05, and the middle conductive electrode material are removed by chemical etching or remote plasma etching.

According to the technical scheme, after the sacrificial medium layer materials among the plurality of layers of horizontal conductive electrodes which are separated from each other in the horizontal direction are removed, redundant gating materials and intermediate electrodes are further removed, so that the plurality of layers of storage layers which are separated from each other in the vertical direction are formed, a three-dimensional storage structure, particularly a vertical three-dimensional RRAM or PCRAM device structure, is realized, and can be compatible with a CMOS (complementary metal oxide semiconductor) process, the storage density is effectively improved, and the cost is very reduced.

Drawings

FIG. 1 is a schematic diagram of a three-dimensional memory structure according to a preferred embodiment of the invention.

FIG. 2 is a flow chart illustrating a method for fabricating a three-dimensional memory according to a preferred embodiment of the invention.

Fig. 3-9 are schematic diagrams illustrating the processing steps for fabricating a three-dimensional memory according to a preferred embodiment of the invention.

FIG. 10 is a schematic diagram of a 1S1R memory cell structure.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.

In the following description of the present invention, please refer to fig. 1, in which fig. 1 is a schematic diagram of a three-dimensional memory structure according to a preferred embodiment of the present invention. As shown in fig. 1, a three-dimensional memory of the present invention may include:

a silicon substrate 01;

the device comprises a plurality of layers of horizontal conductive electrodes 031-033 formed on a silicon substrate 01, and isolation medium layers 111-112 formed between the horizontal conductive electrodes 031-033.

In this embodiment, three horizontal conductive electrodes 031-033 and two isolation dielectric layers 111-112 disposed between the three horizontal conductive electrodes 031-033 are disposed on the silicon substrate 01.

In addition, an insulating medium layer 02 can be arranged between the silicon substrate 01 and the lowest horizontal conductive electrode 031 of the multiple horizontal conductive electrodes 031-033, and a protective medium layer 05 can be arranged on the highest horizontal conductive electrode 033 of the multiple horizontal conductive electrodes 031-033.

Each layer of horizontal conductive electrodes 031-033 and each layer of isolation dielectric layers 111-112 (including the protection dielectric layer 05) are vertically spaced by one or more U-shaped multi-layer structures 07-09 (two U-shaped multi-layer structures 07-09 are shown). The upper ends of the U-shaped multilayer structures 07-09 can be flush with the surface of the protective dielectric layer 05; the lower ends of the U-shaped multilayer structures 07-09 are located on the insulating medium layer 02.

Please refer to fig. 1. A vertical conductive electrode 10 is arranged in the U-shaped part of the multilayer structure 07-09. Wherein, one end of each layer of horizontal conductive electrodes 031-033 is connected with the outer side of the multilayer structure 07-09; the vertical conductive electrode 10 is connected to the inner sides of the multilayer structures 07-09.

In fact, the two vertical sides of the U-shape of the multi-layer structures 07-09 are respectively formed with one multi-layer structure 07-09, that is, each layer of horizontal conductive electrodes 031-033 and the isolation dielectric layers 111-112 (including the protection dielectric layer 05) are separated by two vertically arranged multi-layer structures 07-09. The inner sides of the two multilayer structures 07-09 are provided with vertical conductive electrodes 10, the horizontal conductive electrodes are connected with the outer sides of the two multilayer structures 07-09, and the vertical conductive electrodes 10 are connected with the inner sides of the two multilayer structures 07-09.

In this embodiment, the lower ends of two vertically arranged multi-layer structures 07-09 can be connected through the extension of each layer of material, so as to form a U-shaped multi-layer structure 07-09. But not limited to, the lower ends of the two vertically arranged multilayer structures 07-09 can be disconnected.

The multilayer structure 07-09 comprises a gate tube material layer 07, a middle conductive electrode 08 and a storage material layer 09 from outside to inside.

The gate tube is composed of horizontal conductive electrodes 031-033, a gate tube material layer 07 and a middle conductive electrode 08, the storage unit is composed of the middle conductive electrode 08, a storage material layer 09 and a vertical conductive electrode 10, and the gate tube is connected with the storage unit in series through the middle conductive electrode 08.

The memory material layer 09 may include a resistance change memory material layer or a phase change memory material layer.

The horizontal conductive electrodes 031-033 are connected to the gate tube material layer 07, and the vertical conductive electrode 10 is connected to the storage material layer 09.

The multilayer structures 07-09 are isolated by isolation dielectric layers 111-112. Two layers of isolation medium layers 111 and 112 penetrate into the gate tube material layer 07 and the middle conductive electrode 08 from the outer side, so that the gate tube material layer 07 and the middle conductive electrode 08 are isolated into three sections; wherein each section of gate tube material layer 07 is connected to one end of a corresponding layer of horizontal conductive electrodes 031, 032, 033. Since the gate tube material layer 07 and the middle conductive electrode 08 are vertically isolated by one end of the two isolation dielectric layers 111, 112, three gate tubes are formed which are vertically isolated and independent from each other.

As an alternative embodiment, the materials of the isolation dielectric layers 111-112 can include insulating solid isolation media or gas isolation media.

A method for fabricating a three-dimensional memory according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to fig. 2 in combination with fig. 3 to 9, fig. 2 is a flow chart illustrating a method for manufacturing a three-dimensional memory according to a preferred embodiment of the invention, and fig. 3 to 9 are process steps illustrating a method for manufacturing a three-dimensional memory according to a preferred embodiment of the invention. As shown in fig. 2, a method for fabricating a three-dimensional memory according to the present invention can be used to fabricate the above three-dimensional memory structure such as that shown in fig. 1, and can include the following steps:

step S01: a substrate is provided, and a plurality of horizontal conductive electrodes and sacrificial dielectric layers are alternately formed on the substrate.

Please refer to fig. 3. A silicon substrate 01 may be used, and an insulating dielectric layer 02 may be deposited on the silicon substrate 01.

Then, horizontal conductive electrodes 031-033 and sacrificial medium layers 041-042 are sequentially deposited on the insulating medium layer 02 to form three layers of horizontal conductive electrodes 031-033 and two layers of sacrificial medium layers 041-042, for example, and the three layers of horizontal conductive electrodes 031-033 are mutually isolated by the sacrificial medium layers 041-042. Finally, a protective dielectric layer 05 is deposited over the third horizontal conductive electrode 033.

Substrate 01 may be a silicon wafer on which the fabrication of the desired processing circuitry has been completed and on which the fabrication of the memory device is then resumed.

In this embodiment, a 12-inch silicon wafer can be used as the substrate 01, and 800 to 1200 angstroms, for example, 1000 angstroms of silicon dioxide can be deposited on the silicon wafer substrate 01 as the insulating dielectric layer 02.

Then, horizontal conductive electrode 031-033 materials and sacrificial medium layer 041-042 materials are deposited in sequence.

In this embodiment, TiN with a thickness of 200-400 angstroms, for example, 300 angstroms, can be deposited as the horizontal conductive electrodes 031-033, and amorphous silicon (a-Si) with a thickness of 400-600 angstroms, for example, 500 angstroms, can be deposited as the sacrificial dielectric layers 041-042. Finally, 900-1100 angstroms, for example 1000 angstroms, of silicon dioxide can be deposited as a protective dielectric layer 05 to form three horizontal conductive electrodes 031-033 spaced apart from each other in the horizontal direction.

Step S02: a trench is formed down through the multi-layer horizontal conductive electrode and the sacrificial dielectric layer.

Please refer to fig. 4. The three-layer horizontal conductive electrodes 031-033 can be etched by using photolithography and etching processes, and the grooves 06 are formed in the three-layer horizontal conductive electrodes 031-033.

In this embodiment, the protective dielectric layer 05, the sacrificial dielectric layers 041 to 042 and the horizontal conductive electrodes 031 to 033 in the multilayer film are etched by dry etching, and the etching is stopped on the insulating dielectric layer 02. Therefore, three layers of horizontal conductive electrodes 031-033 in the horizontal direction are patterned and used as one electrode terminal of the memory.

Step S03: and sequentially forming a gate tube material layer, a middle conductive electrode and a storage material layer along the inner wall of the groove to form a multilayer structure, and forming a vertical conductive electrode on the storage material layer.

Please refer to fig. 5. And depositing a gate tube material layer 07, an intermediate conductive electrode 08 and a storage material layer 09 in the groove 06 in sequence as the components of the multilayer structures 07-09.

Then, continuously depositing the vertical conductive electrode 10 material, and removing redundant multilayer structures 07-09 material and the vertical conductive electrode 10 material on the surface to form U-shaped multilayer structures 07-09 and the vertical conductive electrode 10 positioned in the U-shape of the multilayer structures 07-09. The vertical conductive electrode 10 is connected to the memory material layer 09 as a second electrode terminal of the memory.

In the embodiment, 5-15 nm, for example, 10 nm titanium oxide is deposited by ALD as the gate tube material layer 07; then, depositing Co of 5-15 nm, for example, 10 nm by ALD to serve as an intermediate conductive electrode 08; then, ALD is adopted to deposit hafnium oxide with the thickness of 5-15 nanometers, for example, 10 nanometers, to serve as a storage material layer 09, and a multilayer structure 07-09 is formed; finally, TiN is deposited by PVD to be used as the vertical conductive electrode 10, and the groove 06 is filled. And then, removing redundant multilayer structure 07-09 materials and vertical conductive electrode 10 materials on the surface of the structure by adopting a CMP process.

Step S04: and removing the sacrificial dielectric layer.

Please refer to fig. 6. The two sacrificial medium layers 041-042 between the three horizontal conductive electrodes 031-033 can be removed by a chemical etching method or a remote plasma etching method.

In this embodiment, a fluorinated xenon gas is used to etch the amorphous silicon sacrificial dielectric layers 041-042.

Step S05: and continuously removing the gate tube material layer and the middle conductive electrode material at the junction with the sacrificial medium layer to form a gate tube structure which is isolated from each other in the vertical direction.

Please refer to fig. 7. The gate tube material layer 07 in the multilayer structure 07-09 can be continuously and transversely etched along the channel formed after the sacrificial medium layers 041-042 are removed, and the gate tube material layer is stopped on the middle conductive electrode 08 layer.

In this embodiment, the titanium oxide exposed in the gate tube material layer 07 is removed by wet etching, so that the gate tube material layer 07 is isolated into three segments in the vertical direction.

Please continue to refer to fig. 8. And then, further etching the middle conductive electrode 08 along the channel formed after the sacrificial medium layers 041-042 and part of the gate tube material layer 07 are removed, and stopping on the storage material layer 09.

In this embodiment, the Co exposed in the middle conductive electrode 08 layer is removed by wet etching, so that the gate tube is isolated in the vertical direction.

Step S06: and filling an isolation dielectric layer between the horizontal conductive electrodes.

Please refer to fig. 9. The method can adopt methods such as chemical vapor deposition, atomic layer deposition and the like, and fills a solid insulating isolation dielectric material in a cavity formed after the original sacrificial dielectric layers 041-042, part of the gate tube material layer 07 and part of the middle conductive electrode 08 are removed, namely, the gaps among the three horizontal conductive electrodes 031-033 are filled with the solid insulating isolation dielectric material, and can also fill the gaps among the three horizontal conductive electrodes 031-033 with air without filling the solid insulating isolation dielectric material under the condition of ensuring the sufficient mechanical strength of the structure.

In this embodiment, an atomic layer deposition process is adopted to deposit insulating dielectric silicon dioxide between three layers of horizontal conductive electrodes 031-033, so as to form isolation dielectric layers 111-112 located between each layer of horizontal conductive electrodes 031-033, and to complete the manufacture of the three-dimensional memory.

In summary, in the three-dimensional memory and the manufacturing method thereof provided by the invention, by removing part of the gate tube material layer 07 and part of the middle conductive electrode 08 in the vertical direction in the multilayer structure 07-09 material, the gate tubes which are isolated and independent from each other are formed, so that the three-dimensional 1S1R memory structure and the manufacturing thereof are realized, which is beneficial to improving the storage density and reducing the cost.

The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.