阅读说明：本技术 用于仲裁对共享存储器的访问的方法以及对应的电子设备 (Method for arbitrating access to a shared memory and corresponding electronic device ) 是由 J-L·拉拜雷 于 2020-02-19 设计创作，主要内容包括：本公开涉及用于仲裁对共享存储器的访问权限的方法以及对应的电子设备,例如,仲裁对在第一接口和第二接口之间共享的存储器的访问权限。在向第一接口授予对存储器的当前访问权限的同时从第二接口传出的访问存储器的请求之后,触发具有最大计数时间的计数。如果授予第一接口的访问权限的占用的终止在所述最大计数之间的终止之前结束,则在该访问权限的占用的终止处为第二接口授予对存储器的访问权限,否则在最大计数时间的终止处为第二接口授予对存储器的访问权限。(The present disclosure relates to a method for arbitrating access rights to a shared memory, e.g. arbitrating access rights to a memory shared between a first interface and a second interface, and a corresponding electronic device. A count having a maximum count time is triggered following a request to access the memory that is issued from the second interface while the current access to the memory is granted to the first interface. If the termination of the occupation of the access rights granted to the first interface ends before the termination between the maximum counts, the access rights to the memory are granted to the second interface at the termination of the occupation of the access rights, otherwise the access rights to the memory are granted to the second interface at the termination of the maximum count time.)

1. A method for arbitrating access rights to a memory shared between a first interface and a second interface, comprising:

triggering a count having a maximum count time in response to a request to access the memory that is outgoing from the second interface while granting current access to the memory to the first interface;

granting access to the memory for the second interface at the termination of the access right if the termination of the access right granted to the first interface ends before the termination of the maximum count time; and

granting access to the memory for the second interface at the expiration of the maximum count time if the expiration of the access rights granted to the first interface does not occur before the expiration of the maximum count time.

2. The method of claim 1, wherein the first interface is configured to perform a write operation to the memory, the write operation having a time less than or equal to a maximum write time; and wherein the maximum count time is greater than the maximum write time of the write operation.

3. The method of claim 1, wherein the second interface comprises a control signal to switch between two logic states, further comprising:

performing a switch of the control signal to a first state after an access request is transmitted out of the second interface; and

triggering the counting in response to the switching of the control signal to the first state.

4. The method of claim 3:

wherein the switching of the control signal to the second state is performed at the termination of the access right granted to the first interface if the termination of the access right ends before the termination of the maximum count time;

wherein the switching of the control signal to the second state is performed at the expiration of the maximum count time if the expiration of the access right granted to the first interface does not occur before the expiration of the maximum count time; and

wherein access to the memory is granted to the second interface after the control signal switches to the second state.

5. The method of claim 1, wherein the first interface comprises one of a near field communication or a Radio Frequency Identification (RFID) radio frequency communication interface, and the second interface comprises I²C or SMBus bidirectional synchronous serial bus.

6. The method of claim 4, wherein the first interface comprises one of a near field communication or a Radio Frequency Identification (RFID) radio frequency communication interface, and the second interface comprises I²A C or SMBus bidirectional synchronous serial bus; and wherein the control signal of the second interface is a serial clock line signal.

7. The method of claim 6, wherein if the second interface is an SMBus bidirectional synchronous serial bus, the maximum count time is between 25ms and 35 ms.

8. The method of claim 7, wherein the access request outgoing from the second interface includes at least one byte, and the switching of the control signal to the first state occurs after a first byte of the access request from the second interface, and the control signal of the second interface is in a low state after the control signal is switched to the first state and in a high state after the control signal is switched to the second state.

9. An apparatus, comprising:

a first interface and a second interface;

a memory configured to be shared between at least the first interface and the second interface; and

arbitration circuitry configured to:

triggering a count having a maximum count time in response to a request to access the memory that is outgoing from the second interface while granting current access to the memory to the first interface;

granting access to the memory for the second interface at the termination of the access if the termination of the access to the first interface occurs before the termination of the maximum count time; and

granting access rights to the memory for the second interface at the expiration of the maximum count time if the expiration of the access granted to the first interface does not occur before the expiration of the maximum count time.

10. The apparatus of claim 9, wherein the first interface is configured to perform a write operation to the memory, the write operation having a time less than or equal to a maximum write time; and wherein the maximum count time is greater than the maximum write time.

11. The apparatus of claim 9, wherein the second interface comprises a control signal to switch between a first logic state and a second logic state, and wherein the arbitration circuitry is configured to:

switching the control signal to the first logic state after the access request is passed out of the second interface; and

triggering the counting when the control signal switches to the first logic state.

12. The apparatus of claim 11, wherein the arbitration circuitry is configured to:

switching the control signal to the second logic state at the termination of the access right granted to the first interface if the termination of the access right occurs before the termination of the maximum count time;

switching the control signal to the second logic state at the expiration of the maximum count time if the expiration of the access right granted to the first interface does not occur before the expiration of the maximum count time; and

granting access to the memory to the second interface after the control signal switches to the second logic state.

13. The apparatus of claim 9, wherein the first interface comprises one of a near field communication or a Radio Frequency Identification (RFID) radio frequency communication interface, and the second interface comprises I²C or SMBus bidirectional synchronous serial bus.

14. The apparatus of claim 12, wherein the control signal of the second interface is a serial clock line signal.

15. The device of claim 14, wherein if the second interface is an SMBus bi-directional synchronous serial bus, the maximum count time is between 25ms and 35 ms.

16. The apparatus of claim 15, wherein the access request outgoing from the second interface comprises at least one byte, and the arbitration circuitry is configured to perform the switching of the control signal to the first logic state after a first byte of the access request from the second interface, and to cause the control signal of the second interface to be in a low state after the control signal is switched to the first logic state and to be in a high state after the control signal is switched to the second logic state.

17. An electronic apparatus comprising the electronic device of claim 9 and control circuitry coupled to the electronic device.

18. The electronic device of claim 17, wherein the control circuitry comprises a microcontroller.

19. A communication system comprising the electronic apparatus of claim 17 and wireless communication circuitry coupled to the electronic device.

20. The communication system of claim 19, wherein the wireless communication circuitry comprises a near field communication or radio frequency identification reader.

21. A method for arbitrating access rights to a memory shared between a first interface and a second interface, the method comprising:

sending a request from the second interface to access the memory while current access to the memory is granted to the first interface;

starting counting in response to a request sent by the second interface to access the memory; and

granting access to the memory for the second interface if termination of access granted to the first interface does not occur before the threshold of counts.

22. The method of claim 21, wherein the first interface is configured to perform a write operation to the memory, the write operation having a time less than or equal to a maximum write time; and wherein the threshold count time is greater than the maximum write time of the write operation.

23. The method of claim 21, wherein the first interface comprises a near field communication or radio frequency identification radio frequency communication interface and the second interface comprises I²C or SMBus bidirectional synchronous serial bus.

Technical Field

Background

Generally, an electronic device for arbitrating access to a shared memory is configured as an interface that grants access rights to the memory (assuming the memory is available) to the first requested access.

In other words, when no access to the memory is currently being made, the electronic device is configured to accept an access request transmitted by any interface and first received by the electronic device.

Once access to the memory is granted, such electronic device is configured to suspend or deny subsequent access requests transmitted by the second interface until the end of granting access to the first interface.

When access to the memory has been granted, the conventional approach for the second interface is to repeat its access request periodically, known to those skilled in the art as a busy-wait process or a polling process, until access to the memory is available again.

However, when the access time granted to the memory of the first interface is long, such conventional methods often become expensive in terms of time and energy consumption due to the second interface repeating the access request multiple times.

Furthermore, at the end of the access right to seize the memory granted to the first interface, it cannot be automatically guaranteed to gain access to the memory through the second interface, since the electronic device can receive another access request from the first interface between the end of the access right granted to the first interface and the subsequent repetition of the access request from the second interface.

If the access requests from the first interface are frequent and unpredictable, the second interface will likely still be blocked and will remain busy waiting or polling.

In other words, in order to obtain access to the memory after one or more busy-waiting processes, fine and precise synchronization is generally required, and once granted, access to the memory may not be interrupted; this can be problematic or even dangerous for the overall security of the electronic device, since in the case of computer hacker hacking, access rights to the memory can be permanently monopolized entirely maliciously by one interface.

Therefore, new developments that enable low complexity and low power consumption are needed to avoid accesses to permanently blocked memory and to efficiently manage alternate accesses to memory.

Disclosure of Invention

According to one aspect, a method for arbitrating access rights to a memory shared at least between a first interface and a second interface is presented.

The method comprises the following steps: after a request for access to the memory coming out of the second interface while granting the current access to the memory to the first interface, a count having a maximum count time is triggered, and if termination of the tenure granting the access to the first interface ends before termination of the maximum count time, access to the memory is granted to the second interface at the termination of the tenure, otherwise access to the memory is granted to the second interface at the termination of the maximum count time.

Advantageously, this method makes it possible to help ensure the alternation of the access to the memory at the end of the maximum counting time or at the end of the occupation of the current access right (if the end of the occupation ends earlier than the end of said maximum counting time) when an access request from the second interface is received while the occupation of the access right to the memory has been granted for the first interface.

Thus, once access rights have been granted to the interface, access rights to the memory cannot be exclusively taken. The alternation of the access rights to the memory is guaranteed at the latest after the expiration of the maximum count time.

It should be noted that this method can advantageously be applied to each interface requesting access to the memory, or selectively to one or more interfaces, to allow the interface or interfaces to preferentially gain access to the memory.

Furthermore, it should be noted that triggering a count after an access request can be understood as: the counting is triggered when an access request is received or after a time interval following the reception.

According to one implementation mode, the first interface is capable of performing a write operation to the memory, the write operation having a time less than or equal to a maximum write time, and the maximum count time is selected to be greater than the maximum write time.

This makes it possible to allow the write operation currently performed on the memory to be completed, thereby advantageously avoiding the corruption of data written to the memory.

According to one embodiment, the second interface comprises a control signal that is switchable between two logic states.

Then, for example, the first switching of the control signal may be performed after an access request outgoing from the second interface, and the count may be triggered at the first switching of the control signal.

This may be, for example, at I²C-bus.

By way of indication, but not limitation, if, for example, termination of occupation of access rights granted to the first interface ends before or at termination of the maximum count time, a second switch of the control signal is performed at the termination of occupation and access rights to the memory are granted to the second interface after the second switch of the control signal.

In this case, this can also advantageously be at I²C-bus.

According to one mode of implementation, the first interface may be a near field communication or radio frequency identification radio frequency communication interface and the second interface may be I²C or SMBus bidirectional synchronous serial bus.

This method advantageously makes it possible to put I at the end of the maximum counting time in the worst case²The C or SMBus interface grants access to the memory.

By way of non-limiting example, in²In the case of the C interface, the control signal of the second interface is a Serial Clock Line (SCL) signal.

The control signal is advantageously used here to inform the control circuit arrangement (for example,is coupled to I²Microcontroller of C or SMBus interface) cannot currently access memory to satisfy it via I²A request to access memory by a C or SMBus interface.

According to yet another embodiment mode, if the second interface is an SMBus bi-directional synchronous serial bus, the maximum count time is chosen to be between 25ms and 35ms, which is compatible with the SMBus standard.

For example, in the second I²In the case of a C or SMBus interface, an access request coming out of the second interface may for example contain at least one byte, and a first switch occurs after the first byte of the access request from the second interface, and the control signals of the second interface are in a low state after the first switch and in a high state after the second switch, which may be denoted using the term SCL stretch.

A low state of the control signal indicates that the second interface is not ready to process a request to access the memory, and a high state of the control signal indicates that the second interface is again ready to process a request to access the memory.

According to another aspect, an electronic device is presented, comprising: at least a first interface and a second interface; a memory configured to be shared between at least first and second interfaces; and arbitration circuitry configured to trigger a count having a maximum count time after a request to access the memory that is issued from the second interface while granting current access to the memory to the first interface, and to grant access to the memory for the second interface at the end of the hold if the end of the hold granting access to the first interface ends before the end of the maximum count time, and to grant access to the memory for the second interface at the end of the maximum count time otherwise.

By way of indication but not limitation, the first interface is capable of performing a write operation to the memory having a time less than or equal to a maximum write time, and the maximum count time is advantageously selected to be greater than the maximum write time.

According to one embodiment, the second interface comprises a control signal capable of switching between two logic states, and the arbitration circuitry is configured to perform a first switching of the control signal following an access request coming out of the second interface, and to trigger a count upon the first switching of the control signal.

For example, the arbitration circuitry may be configured to: if the termination of the occupation of the access right granted to the first interface ends before the termination of the maximum count time, a second switching of the control signal is performed at the termination of the occupation of the access right, otherwise the second switching of the control signal is performed at the termination of the maximum count time, and the access right to the memory is granted to the second interface after the second switching of the control signal.

According to one embodiment, the first interface may be a near field communication or radio frequency identification radio frequency communication interface and the second interface may be I²C or SMBus bidirectional synchronous serial bus.

For example, the control signal of the second interface may be a serial clock line signal.

According to a further embodiment, if the second interface is an SMBus bi-directional synchronous serial bus, the maximum count time is selected to be between 25ms and 35 ms.

For example, the access request coming out of the second interface may comprise at least one byte, and the arbitration circuitry may for example be configured to perform a first switch after a first byte of the access request from the second interface and to bring the control signal of the second interface in a low state after the first switch and in a high state after the second switch.

According to another aspect, an electronic apparatus is presented, comprising an electronic device such as defined above and control circuitry coupled to the electronic device.

By way of indication but not limitation, the control circuitry may, for example, comprise a microcontroller.

According to another aspect, a communication system is proposed, comprising an electronic apparatus such as defined above and wireless communication circuitry coupled to the electronic device.

According to one embodiment, the communication circuitry includes a Near Field Communication (NFC) or Radio Frequency Identification (RFID) reader.

Drawings

Other advantages and features will become apparent upon examination of the detailed description of a purely non-limiting embodiment and example and the accompanying drawings, in which:

figure 1 shows schematically a communication system in which,

figure 2 schematically shows an exemplary embodiment of the arbitration circuit means in the form of a state machine diagram,

FIG. 3 shows a timing diagram, an

Fig. 4 shows a timing diagram.

Embodiments and examples relate to electronic devices and, more particularly, to electronic devices for arbitrating access rights to a shared memory, also referred to as shared memory arbitration.