阅读说明：本技术 Usb时钟产生电路 (USB clock generating circuit ) 是由 张歆 于 2020-05-18 设计创作，主要内容包括：本发明公开了一种USB时钟产生电路,包括晶振电路模块、为USB模块提供时钟信号的RC振荡器模块,RC振荡器模块连接于晶振电路模块并接收晶振电路模块提供的基准时钟；RC振荡器模块包括RCO子电路、同步脉冲发生子电路、计数器子电路、开关控制子电路和时钟合成子电路；RCO子电路输出第一控制信号；同步脉冲发生子电路连接于晶振电路模块并输出第二控制信号；计数器子电路连接于RCO子电路和同步脉冲发生子电路,并输出第三控制信号；时钟合成子电路经运算后输出USB模块所需的时钟信号。本发明技术方案通过晶振电路模块提供基准时钟,增加同步脉冲发生子电路以使基准时钟对RCO子电路进行同步,满足全速USB时钟的应用需求。(The invention discloses a USB clock generating circuit, which comprises a crystal oscillator circuit module and an RC oscillator module, wherein the RC oscillator module is used for providing clock signals for the USB module, and is connected with the crystal oscillator circuit module and receives a reference clock provided by the crystal oscillator circuit module; the RC oscillator module comprises an RCO sub-circuit, a synchronous pulse generation sub-circuit, a counter sub-circuit, a switch control sub-circuit and a clock synthesis sub-circuit; the RCO sub-circuit outputs a first control signal; the synchronous pulse generating sub-circuit is connected to the crystal oscillator circuit module and outputs a second control signal; the counter sub-circuit is connected with the RCO sub-circuit and the synchronous pulse generating sub-circuit and outputs a third control signal; the clock synthesis sub-circuit outputs the clock signal required by the USB module after operation. According to the technical scheme, the reference clock is provided through the crystal oscillator circuit module, and the synchronous pulse generating sub-circuit is added so that the reference clock can synchronize the RCO sub-circuit, and the application requirement of the full-speed USB clock is met.)

1. A USB clock generating circuit comprises a crystal oscillator circuit module and is characterized by further comprising an RC oscillator module which provides clock signals for the USB module, wherein the RC oscillator module is connected to the crystal oscillator circuit module and receives a reference clock provided by the crystal oscillator circuit module; the RC oscillator module comprises an RCO sub-circuit, a synchronous pulse generation sub-circuit, a counter sub-circuit, a switch control sub-circuit and a clock synthesis sub-circuit;

the RCO sub-circuit outputs a first control signal;

the synchronous pulse generating sub-circuit is connected to the crystal oscillator circuit module to receive the reference clock and output a second control signal;

the counter sub-circuit is connected to the RCO sub-circuit and the synchronous pulse generation sub-circuit and receives the first control signal and the second control signal, and the counter sub-circuit counts according to the first control signal and the second control signal and outputs a third control signal according to a counting value;

the switch control sub-circuit receives the second control signal and the third control signal to control on/off of the switch control sub-circuit respectively;

and the clock synthesis sub-circuit receives the first control signal and the second control signal, and outputs a clock signal required by the USB module after OR operation.

2. The USB clock generation circuit of claim 1, wherein the RCO sub-circuit includes a first current source, a first comparator, a first capacitor, a first field effect transistor, and a first inverter;

the first current source provides a current source for the RCO sub-circuit, the first comparator is connected to the first current source and compares the first current source with a threshold voltage, and an output end of the first comparator outputs a first control signal; one end of the first capacitor is connected to the first current source, and the other end of the first capacitor is grounded; the drain electrode of the first field effect transistor is connected to one end of the first current source and one end of the first capacitor, the grid electrode of the first field effect transistor is connected to the output end of the first phase inverter, and the drain electrode of the first field effect transistor is grounded; the output end of the first comparator is connected to the switch control sub-circuit, and the switch control sub-circuit is further connected to the input end of the first phase inverter.

3. The USB clock generation circuit of claim 2, wherein the switch control sub-circuit comprises a first nor gate unit, inputs of the first nor gate unit respectively receive the first control signal, the second control signal and the third control signal, and an output of the first nor gate unit is connected to an input of the first inverter.

4. The USB clock generation circuit of claim 2, wherein the synchronization pulse generation sub-circuit comprises a third inverter, a delay unit, a nand gate unit, and a fourth inverter;

the input end of the third inverter is connected to the crystal oscillator circuit module and receives the reference clock, and the output end of the third inverter is connected to the input end of the delay unit;

the input end of the nand gate unit is connected to the output end of the delay unit and the crystal oscillator circuit module, the output end of the nand gate unit is connected to the input end of the fourth inverter, and the output end of the fourth inverter outputs a second control signal.

5. The USB clock generation circuit of claim 1, wherein the RCO sub-circuit includes a first current source, a first comparator, a first capacitor, a first field effect transistor, a first inverter, and a second inverter;

the first current source provides a current source for the RCO sub-circuit, the first comparator is connected to the first current source and compares the first current source with a threshold voltage, and the output end of the first comparator outputs a first control signal through the first inverter and the second inverter; one end of the first capacitor is connected to the first current source, and the other end of the first capacitor is grounded; the drain electrode of the first field effect transistor is connected to one end of the first current source and one end of the first capacitor, the grid electrode of the first field effect transistor is connected to the output end of the second phase inverter, and the drain electrode of the first field effect transistor is grounded; the output end of the first comparator is connected to the input end of the first phase inverter, and the output end of the first phase inverter is connected to the input end of the second phase inverter.

6. The USB clock generation circuit of claim 5, wherein the switch control sub-circuit comprises a first switch coupled to the sync pulse generation sub-circuit and receiving a second control signal, and further comprising a second switch coupled to the counter sub-circuit and receiving a third control signal, the first switch coupled to the second switch, the second switch further coupled to one end of the first capacitor.

7. The USB clock generation circuit of claim 5, wherein the synchronization pulse generation sub-circuit comprises a second comparator, a NAND gate unit, a fourth inverter, a second field effect transistor and a second capacitor;

the second comparator is connected to the second current source, compares the second current source with a threshold voltage, and outputs a comparison result to the NAND gate unit; the input end of the NAND gate unit is respectively connected with the output end of the second comparator and the crystal oscillator circuit module, and the output end of the NAND gate unit is connected with the input end of the fourth inverter; the output end of the fourth inverter outputs a second control signal;

one end of the second capacitor is connected to the second current source, and the other end of the second capacitor is grounded; and the grid electrode of the second field effect transistor is connected to the crystal oscillator circuit module, the drain electrode of the second field effect transistor is connected to one end of the second capacitor, the second current source and the source electrode of the second field effect transistor are grounded.

8. The USB clock generating circuit of claim 1, wherein the CK input of the counter sub-circuit is connected to the RCO sub-circuit and receives the first control signal for counting rising edges of the first control signal; the RST input end of the counter sub-circuit is connected with the synchronous pulse generating sub-circuit and receives the second control signal, and the RST input end of the counter sub-circuit is used for clearing a count value when the second control signal is at a high level; the counter sub-circuit output outputs a third control signal.

9. The USB clock generation circuit of claim 1, wherein the clock synthesis sub-circuit comprises a second nor gate unit, a fifth inverter, and a divide-by-two sub-circuit; a first input end of the second nor gate unit is connected to the RCO sub-circuit and receives the first control signal, and a second input end of the second nor gate unit is connected to the synchronization pulse generation sub-circuit and receives the second control signal; the output end of the second NOR gate unit is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the frequency-halving sub-circuit to output a clock signal.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a USB clock generating circuit.

Background

At present, in a System-on-a-Chip (SOC), two types of methods are generally used for providing a clock for a digital circuit:

first, a crystal oscillator is used to generate a reference clock, and the reference clock is multiplied by an internal PLL (Phase Locked Loop) to generate a required clock frequency, as shown in fig. 1. The method has the advantages that: the frequency precision is high; the disadvantages are that: the crystal oscillator starts slowly, usually for more than 1ms, so that the digital circuit starts and waits for a long time.

Secondly, an RC oscillator is adopted, and a relatively accurate clock is obtained through calibration processing and provided to a digital circuit, as shown in fig. 2. The method has the advantages of quick oscillation starting, simple circuit and low cost. The disadvantages are that: the frequency accuracy is poor. For MCU applications this approach is generally satisfactory.

Whereas USB full speed requires a clock frequency that is an integer multiple of 12MHz, typically 48MHz, to be used by digital circuitry to sample the incoming data. In order to prevent sampling dislocation caused by excessive clock skew for a long time, the clock of the USB needs to have an accuracy of plus or minus 2500 ppm.

If the SOC needs to support USB full speed, the method I is feasible, but the cost is increased. Or the frequency of the crystal oscillator is limited, 24M or 48M, an additional phase-locked loop is omitted, and a 48MHz clock is generated by a simple frequency doubling circuit, but the flexibility of the product is limited (and the higher the frequency of the crystal oscillator is, the more expensive the crystal oscillator is). The second method does not have the defects, but the frequency accuracy is required to be within plus or minus 2500ppm under the process/temperature deviation, and extra circuit design effort and circuit area are required. There is also a third method, which adds extra processing in the digital domain to reduce the requirement for USB clock accuracy, but this also increases the cost and design difficulty.

Disclosure of Invention

The invention mainly aims to provide a USB clock generating circuit, aiming at reducing the circuit cost while ensuring the clock precision.

In order to achieve the above object, the present invention provides a USB clock generating circuit, which includes a crystal oscillator circuit module, and further includes an RC oscillator module for providing a clock signal to the USB module, where the RC oscillator module is connected to the crystal oscillator circuit module and receives a reference clock provided by the crystal oscillator circuit module; the RC oscillator module comprises an RCO sub-circuit, a synchronous pulse generation sub-circuit, a counter sub-circuit, a switch control sub-circuit and a clock synthesis sub-circuit; the RCO sub-circuit outputs a first control signal; the synchronous pulse generating sub-circuit is connected to the crystal oscillator circuit module to receive the reference clock and output a second control signal; the counter sub-circuit is connected to the RCO sub-circuit and the synchronous pulse generation sub-circuit and receives the first control signal and the second control signal, and the counter sub-circuit counts according to the first control signal and the second control signal and outputs a third control signal according to a counting value; the switch control sub-circuit receives the second control signal and the third control signal to control on/off of the switch control sub-circuit respectively; and the clock synthesis sub-circuit receives the first control signal and the second control signal, and outputs a clock signal required by the USB module after OR operation.

Preferably, the RCO sub-circuit includes a first current source, a first comparator, a first capacitor, a first field effect transistor, and a first inverter;

the first current source provides a current source for the RCO sub-circuit, the first comparator is connected to the first current source and compares the first current source with a threshold voltage, and an output end of the first comparator outputs a first control signal; one end of the first capacitor is connected to the first current source, and the other end of the first capacitor is grounded; the drain electrode of the first field effect transistor is connected to one end of the first current source and one end of the first capacitor, the grid electrode of the first field effect transistor is connected to the output end of the first phase inverter, and the drain electrode of the first field effect transistor is grounded; the output end of the first comparator is connected to the switch control sub-circuit, and the switch control sub-circuit is further connected to the input end of the first phase inverter.

Preferably, the switch control sub-circuit includes a first nor gate unit, inputs of the first nor gate unit respectively receive the first control signal, the second control signal and the third control signal, and an output of the first nor gate unit is connected to an input of the first inverter.

Preferably, the synchronization pulse generation sub-circuit comprises a third inverter, a delay unit, a nand gate unit and a fourth inverter;

the input end of the third inverter is connected to the crystal oscillator circuit module and receives the reference clock, and the output end of the third inverter is connected to the input end of the delay unit;

the input end of the nand gate unit is connected to the output end of the delay unit and the crystal oscillator circuit module, the output end of the nand gate unit is connected to the input end of the fourth inverter, and the output end of the fourth inverter outputs a second control signal.

Preferably, the RCO sub-circuit includes a first current source, a first comparator, a first capacitor, a first field effect transistor, a first inverter, and a second inverter;

the first current source provides a current source for the RCO sub-circuit, the first comparator is connected to the first current source and compares the first current source with a threshold voltage, and the output end of the first comparator outputs a first control signal through the first inverter and the second inverter; one end of the first capacitor is connected to the first current source, and the other end of the first capacitor is grounded; the drain electrode of the first field effect transistor is connected to one end of the first current source and one end of the first capacitor, the grid electrode of the first field effect transistor is connected to the output end of the second phase inverter, and the drain electrode of the first field effect transistor is grounded; the output end of the first comparator is connected to the input end of the first phase inverter, and the output end of the first phase inverter is connected to the input end of the second phase inverter.

Preferably, the switch control sub-circuit includes a first switch connected to the synchronization pulse generation sub-circuit and receiving a second control signal, and further includes a second switch connected to the counter sub-circuit and receiving a third control signal, the first switch is connected to the second switch, and the second switch is further connected to one end of the first capacitor.

Preferably, the synchronization pulse generation sub-circuit comprises a second comparator, a nand gate unit, a fourth inverter, a second field effect transistor and a second capacitor;

the second comparator is connected to the second current source, compares the second current source with a threshold voltage, and outputs a comparison result to the NAND gate unit; the input end of the NAND gate unit is respectively connected with the output end of the second comparator and the crystal oscillator circuit module, and the output end of the NAND gate unit is connected with the input end of the fourth inverter; the output end of the fourth inverter outputs a second control signal;

one end of the second capacitor is connected to the second current source, and the other end of the second capacitor is grounded; and the grid electrode of the second field effect transistor is connected to the crystal oscillator circuit module, the drain electrode of the second field effect transistor is connected to one end of the second capacitor, the second current source and the source electrode of the second field effect transistor are grounded.

Preferably, the CK input terminal of the counter sub-circuit is connected to the RCO sub-circuit and receives the first control signal, so as to count the rising edges of the first control signal; the RST input end of the counter sub-circuit is connected with the synchronous pulse generating sub-circuit and receives the second control signal, and the RST input end of the counter sub-circuit is used for clearing a count value when the second control signal is at a high level; the counter sub-circuit output outputs a third control signal.

Preferably, the clock synthesis sub-circuit comprises a second nor gate unit, a fifth inverter and a divide-by-two sub-circuit; a first input end of the second nor gate unit is connected to the RCO sub-circuit and receives the first control signal, and a second input end of the second nor gate unit is connected to the synchronization pulse generation sub-circuit and receives the second control signal; the output end of the second NOR gate unit is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the frequency-halving sub-circuit to output a clock signal.

According to the technical scheme, the reference clock is provided through the crystal oscillator circuit module, and the synchronous pulse generating sub-circuit, the counter sub-circuit, the switch control sub-circuit and the clock synthesizing sub-circuit are added, so that the reference clock can synchronize the RCO sub-circuit, and the application requirement of the full-speed USB clock can be met even under the condition that the accuracy of the RCO sub-circuit is low.

Drawings

FIG. 1 is a prior art clock generation circuit;

FIG. 2 is another prior art clock generation circuit;

FIG. 3 is a schematic diagram of a USB clock generating circuit according to the present invention;

FIG. 4 is a schematic diagram of an RC oscillator module in the USB clock generating circuit according to the present invention; ''

FIG. 5 is a schematic circuit diagram of an RC oscillator module according to a first embodiment of the present invention;

fig. 6 is a schematic circuit diagram of an RC oscillator module according to a second embodiment of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The invention is further described below with reference to the accompanying drawings.

The embodiment of the invention provides a USB clock generating circuit which is used for generating a full-speed USB clock with low cost.

As shown in fig. 3 and 4, the USB clock generation circuit includes a crystal oscillator circuit module, and the circuit further includes an RC oscillator module for providing a clock signal to the USB module, wherein the RC oscillator module is connected to the crystal oscillator circuit module and receives a reference clock CK _ XO provided by the crystal oscillator circuit module; the RC oscillator module comprises an RCO sub-circuit, a synchronous pulse generation sub-circuit, a counter sub-circuit, a switch control sub-circuit and a clock synthesis sub-circuit; the RCO sub-circuit outputs a first control signal RST _ M; the synchronous pulse generation sub-circuit is connected with the crystal oscillator circuit module to receive the reference clock CK _ XO and output a second control signal RST _ D; the counter sub-circuit is connected to the RCO sub-circuit and the synchronization pulse generation sub-circuit and receives the first control signal RST _ M and the second control signal RST _ D, and the counter sub-circuit counts according to the first control signal RST _ M and the second control signal RST _ D and outputs a third control signal CtoN according to a count value; the switch control sub-circuit receives the second control signal RST _ D and the third control signal CtoN to control on/off of the switch control sub-circuit, respectively; the clock synthesis sub-circuit receives the first control signal RST _ M and the second control signal RST _ D, and outputs a clock signal required by the USB module after OR operation.

According to the embodiment of the invention, on the premise that the system has the crystal oscillator circuit and the RCO sub-circuit, the synchronous pulse generation sub-circuit, the counter sub-circuit, the switch control sub-circuit and the clock synthesis sub-circuit are added, so that the RCO sub-circuit can be synchronized by using the reference clock CK _ XO of the crystal oscillator circuit, and the application requirement of the full-speed USB clock can be ensured even if the precision of the RCO sub-circuit is low.

As shown in fig. 5, in the first embodiment, a first current source CS _ M, a first comparator CMP _ M, a first capacitor CAP _ M, a first field effect transistor M1, a first inverter P1, and a second inverter P2 are included; the first current source CS _ M provides a current source for the RCO sub-circuit, the first comparator CMP _ M is connected to the first current source CS _ M and compares the first current source CS _ M with the threshold voltage VR, and an output terminal of the first comparator CMP _ M outputs the first control signal RST _ M through the first inverter P1 and the second inverter P2; one end of the first capacitor CAP _ M is connected to the first current source CS _ M, and the other end is grounded; the drain of the first field effect transistor M1 is connected to one end of the first current source CS _ M and the first capacitor CAP _ M, the gate is connected to the output end of the second inverter P2, and the drain is grounded; the output terminal of the first comparator CMP _ M is connected to the input terminal of the first inverter P1, and the output terminal of the first inverter P1 is connected to the input terminal of the second inverter P2.

The first current source CS _ M charges the first capacitor CAP _ M, the upper plate voltage VCAP _ M of the first capacitor CAP _ M increases in a ramp manner, when it is greater than the threshold voltage VR, the output of the first comparator CMP _ M is inverted, the first fet M1 is turned on, the first capacitor CAP _ M discharges charges, so that the upper plate voltage VCAP _ M of the first capacitor CAP _ M returns to 0 again, at this time, since the upper plate voltage VCAP _ M of the first capacitor CAP _ M is lower than the threshold voltage VR, the first comparator CMP _ M is inverted again, the first fet M1 is turned off, the first current source CS _ M charges the first capacitor CAP _ M again, the upper plate voltage VCAP _ M of the first capacitor CAP _ M increases in a ramp manner again, and so on, a pulse with a fixed frequency is formed to output the first control signal RST _ M.

As shown in fig. 5, the switch control sub-circuit includes a first switch S1 connected to the sync pulse generation sub-circuit and receiving the second control signal RST _ D, and further includes a second switch S2 connected to the counter sub-circuit and receiving the third control signal CtoN, the first switch S1 is connected to the second switch S2, and the second switch S2 is further connected to one end of the first capacitor CAP _ M. The first switch S1 and the second switch S2 in the switch control sub-circuit are controlled to be turned on/off by the second control signal RST _ D and the third control signal CtoN, respectively, and the first switch S1 and the second switch S2 are also connected to the RCO sub-circuit, so that the first control signal RST _ M can be synchronized with the reference clock CK _ XO when the first switch S1 and the second switch S2 are turned on.

As shown in fig. 5, in particular, the first switch S1 and the second switch S2 are both fets. The second control signal RST _ D is output to the gate of the first switch S1 for controlling the on/off of the first switch S1. The third control signal CtoN is output to the gate of the second switch S2 for controlling the on/off of the second switch S2. The drains of the first switch S1 and the second switch S2 are connected to one end of the first capacitor CAP _ M, and the sources of the first switch S1 and the second switch S2 are grounded.

As shown in fig. 5, the synchronization pulse generating sub-circuit includes a second comparator CMP _ D, a NAND gate unit NAND, a fourth inverter P4, a second field effect transistor M2, and a second capacitor CAP _ D; the second comparator CMP _ D is connected to the second current source CS _ D, compares the second current source CS _ D with the threshold voltage VR, and outputs a comparison result to the NAND gate unit NAND; the input end of the NAND gate unit is respectively connected with the output end of the second comparator CMP _ D and the crystal oscillator circuit module, and the output end of the NAND gate unit is connected with the input end of the fourth inverter P4; the output terminal of the fourth inverter P4 outputs the second control signal RST _ D; one end of the second capacitor CAP _ D is connected to the second current source CS _ D, and the other end is grounded; the gate of the second fet M2 is connected to the crystal oscillator circuit module, the drain is connected to one end of the second capacitor CAP _ D and the second current source CS _ D, and the source is grounded. The synchronization pulse generation sub-circuit receives the reference clock CK _ XO and outputs the second control signal RST _ D to control on/off of the first switch S1.

As shown in fig. 5, the CK input terminal CK of the counter sub-circuit is connected to the RCO sub-circuit and receives the first control signal RST _ M for counting the rising edges of the first control signal RST _ M; the RST input end RST of the counter sub-circuit is connected with the synchronous pulse generating sub-circuit and receives a second control signal RST _ D, and the RST input end RST is used for clearing the count value when the second control signal RST _ D is at a high level; the counter sub-circuit output terminal CKO outputs a third control signal CtoN.

In an embodiment, the counter sub-circuit triggers counting when the first control signal RST _ M rises, and the count value is incremented by 1 when the first control signal RST _ M rises. The counter sub-circuit clears the count value when the second control signal RST _ D is at a high level. When the count value of the counter sub-circuit is equal to the preset count value, the counter sub-circuit outputs a high level, and outputs 0 at the rest of the time.

Specifically, for example, when the rising edge of the reference clock CK _ XO is T =0, the reference clock CK _ XO is 16MHz, the preset count value N _ target is 5, and the period T _ rco of the first control signal RST _ M is 1/96 MHz:

at t <0, since the reference clock CK _ XO =0, the second control signal RST _ D is at a low level, assuming that other signals may be arbitrary values;

when t =0, the reference clock CK _ XO changes from 0 to 1, so that the second control signal RST _ D changes from low to high, the first switch S1 is turned on, the upper plate voltage VCAP _ M of the first capacitor CAP _ M is low, the count value of the counter sub-circuit is equal to 0, and the third control signal CtoN is low;

because the upper plate voltage VCAP _ D of the second capacitor CAP _ D is greater than the threshold voltage VR, after the second comparator CMP _ D delays, the second control signal RST _ D changes from high level to low level, at this time, the first switch S1 and the second switch S2 are both in an off state, the RCO sub-circuit starts to oscillate, each time the first control signal RST _ M generates one pulse, the count value of the counter sub-circuit increases by 1, and when the count value reaches a preset count value of 5, the third control signal CtoN changes from low level to high level, the upper plate voltage VCAP _ M of the first capacitor CAP _ M is pulled to low level, so as to prevent the 6 th pulse;

when the reference voltage CK _ XO changes from 0 to 1 again, the second control signal RST _ D changes from 0 to 1 as described above, the count value of the counter sub-circuit is cleared by 0, the third control signal CtoN is low again, and the state returns to the state at time t =0, and the process is repeated.

As shown in fig. 5, the clock synthesizing sub-circuit includes a second NOR gate unit NOR2, a fifth inverter P5, and a divide-by-two sub-circuit; a first input terminal of the second NOR gate unit NOR2 is connected to the RCO sub-circuit and receives the first control signal RST _ M, and a second input terminal thereof is connected to the sync pulse generation sub-circuit and receives the second control signal RST _ D; the output terminal of the second NOR gate unit NOR2 is connected to the input terminal of the fifth inverter P5, and the output terminal of the fifth inverter P5 is connected to the divide-by-two sub-circuit to output the clock signal.

In a specific embodiment, taking the reference clock CK _ XO as 16MHz as an example, the first control signal RST _ M and the second control signal RST _ D are OR-operated to obtain a pulse signal USB _96M with a frequency of 96MHz, and then the pulse signal USB _96M with the frequency of 96MHz is divided by two to obtain a 48MHz clock USB _48M with a duty ratio of 50%. In other embodiments, when the circuit has a low requirement on the duty ratio, the divide-by-two sub-circuit may be omitted, and the output signal is not divided.

Since the second control signal RST _ D is strictly aligned with the reference clock CK _ XO at 16MHz, and the RCO sub-circuit is forcibly reset every 5 cycles to synchronize the RCO sub-circuit with the reference clock CK _ XO, the frequency error of the finally output pulse train is not accumulated, and as long as the frequency deviation of the RCO sub-circuit is less than 5% from 96MHz, the control signal RST _ D can be used for full-speed USB.

In the second embodiment, in order to reduce the circuit area and reduce the circuit size, the second comparator CMP _ D, the second current source CS _ D and the second capacitor CAP _ D in the first embodiment may be omitted, and the implementation is purely digital, so as to reduce the additional cost to 0.

As shown in fig. 6, the USB clock generating circuit in the second embodiment includes a crystal oscillator circuit module, an RC oscillator module for providing a clock signal to the USB module, the RC oscillator module being connected to the crystal oscillator circuit module and receiving a reference clock CK _ XO provided by the crystal oscillator circuit module; the RC oscillator module comprises an RCO sub-circuit, a synchronous pulse generation sub-circuit, a counter sub-circuit, a switch control sub-circuit and a clock synthesis sub-circuit.

As shown in fig. 6, the RCO sub-circuit includes a first current source CS _ M, a first comparator CMP _ M, a first capacitor CAP _ M, a first field effect transistor M1, and a first inverter P1; the first current source CS _ M provides a current source for the RCO sub-circuit, the first comparator CMP _ M is connected with the first current source CS _ M and compares the first current source CS _ M with the threshold voltage VR, and the output end of the first comparator CMP _ M outputs a first control signal RST _ M; one end of the first capacitor CAP _ M is connected to the first current source CS _ M, and the other end is grounded; the drain of the first fet M1 is connected to one end of the first current source CS _ M and the first capacitor CAP _ M, the gate is connected to the output end of the first inverter P1, and the drain is grounded; the output terminal of the first comparator CMP _ M is connected to the switch control sub-circuit, which is further connected to the input terminal of the first inverter P1.

As shown in fig. 6, the switch control sub-circuit includes a first NOR gate unit NOR1, inputs of the first NOR gate unit NOR1 respectively receive a first control signal RST _ M, a second control signal RST _ D, and a third control signal CtoN, and an output of the first NOR gate unit NOR1 is connected to an input of the first inverter P1.

As shown in fig. 6, the synchronization pulse generation sub-circuit includes a third inverter P3, a delay unit DU, a NAND gate unit NAND, and a fourth inverter P4; the input end of the third inverter P3 is connected to the crystal oscillator circuit module and receives the reference clock CK _ XO, and the output end of the third inverter P3 is connected to the input end of the delay unit DU; the input end of the NAND gate unit NAND is connected to the output end of the delay unit DU and the crystal oscillator circuit module, the output end of the NAND gate unit NAND is connected to the input end of the fourth inverter P4, and the output end of the fourth inverter P4 outputs the second control signal RST _ D.

As shown in fig. 6, the CK input terminal CK of the counter sub-circuit is connected to the RCO sub-circuit and receives the first control signal RST _ M for counting the rising edges of the first control signal RST _ M; the RST input end RST of the counter sub-circuit is connected with the synchronous pulse generating sub-circuit and receives a second control signal RST _ D, and the RST input end RST is used for clearing the count value when the second control signal RST _ D is at a high level; the counter sub-circuit output terminal CKO outputs a third control signal CtoN.

As shown in fig. 6, the clock synthesis sub-circuit includes a second NOR gate unit NOR2 and a fifth inverter P5; a first input terminal of the second NOR gate unit NOR2 is connected to the RCO sub-circuit and receives the first control signal RST _ M, and a second input terminal thereof is connected to the sync pulse generation sub-circuit and receives the second control signal RST _ D; the output terminal of the second NOR gate unit NOR2 is connected to the input terminal of the fifth inverter P5, and the output terminal of the fifth inverter P5 outputs the clock signal.

It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.