阅读说明：本技术 集成电路芯片的凸点（Bump）盘布局方法 (Bump (Bump) board layout method for integrated circuit chip ) 是由 陈绕所 于 2018-12-27 设计创作，主要内容包括：提供了集成电路芯片的凸点(Bump)盘布局方法。所提供的集成电路设计中的凸点(Bump)盘布局方法,包括：放置电路单元；从被放置的电路单元选出对凸点盘带来的影响敏感的一个或多个电路单元；获取所述一个或多个电路单元所在的一个或多个敏感区域；在所设计的集成电路表层放置凸点盘；识别位于所述一个或多个敏感区域在集成电路表层的对应区域的一个或多个凸点盘；以及调整所述一个或多个凸点盘的位置使其离开所述一个或多个敏感区域在集成电路表层的对应区域。(A Bump (Bump) pad layout method for an integrated circuit chip is provided. A Bump (Bump) pad layout method in an integrated circuit design is provided, comprising: placing a circuit unit; selecting one or more circuit units from the placed circuit units, wherein the one or more circuit units are sensitive to influences caused by the bump pads; acquiring one or more sensitive areas where the one or more circuit units are located; placing a bump plate on the surface layer of the designed integrated circuit; identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface of the integrated circuit; and adjusting the position of the one or more bump pads away from the corresponding area of the one or more sensitive areas on the surface of the integrated circuit.)

1. A method of Bump (Bump) pad layout in an integrated circuit design, comprising:

placing a circuit unit;

selecting one or more circuit units from the placed circuit units, wherein the one or more circuit units are sensitive to influences caused by the bump pads;

acquiring one or more sensitive areas where the one or more circuit units are located;

placing a bump plate on the surface layer of the designed integrated circuit;

identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface of the integrated circuit; and

and adjusting the position of the one or more convex point disks to be away from the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit.

2. The method of claim 1, further comprising:

and if the position of the first bump pad which can leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the integrated circuit design cannot be found, deleting the first bump pad.

3. The method of claim 1 or 2, further comprising:

for a first bump pad positioned in a corresponding area of the first sensitive area on the surface layer of the integrated circuit, determining the center of the first sensitive area on the first corresponding area of the surface layer of the integrated circuit;

changing the position of the first bump pad in a direction away from the center of the first corresponding region such that the first bump pad is away from the first corresponding region.

4. The method of claim 1, further comprising:

if the position of the first salient point disk, which enables the first salient point disk to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and not violate the constraint condition of the integrated circuit design, cannot be found, marking the first salient point disk as a to-be-deleted state; and

and adjusting the positions of other bump pads except the first bump pad in the one or more bump pads to enable the other bump pads to leave the corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit.

5. The method of claim 4, further comprising:

and deleting all the bump disks marked as the states to be deleted.

6. The method of claim 5, wherein

The one or more sensitive areas are areas where VCOs of the P LL cell are located.

7. The method of one of claims 1-6, further comprising:

the RD L design is made to establish connections between the bump pads and the circuit cells.

8. The method according to one of claims 1 to 7, wherein

The corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit is the area obtained by projecting the one or more sensitive areas on the surface layer of the designed integrated circuit.

9. The method of claim 8, wherein

The one or more sensitive areas are located at each layer of the integrated circuit having the 3D structure or at a plurality of layers adjacent to the surface layer.

10. A computer comprising a memory, a processor and a program stored on the memory and executable on the processor, wherein the processor implements the Bump (Bump) pad layout method in the integrated circuit design of any of claims 1 to 9 when executing the program.

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a method for improving the yield of an integrated circuit chip by reasonably arranging a bump pad on the surface of the chip.

Background

In order to solve the problem of IR Drop, more and more integrated circuit CHIPs begin to choose a design using F L IP-CHIP (flip-CHIP package). to implement flip-CHIP packaging, a plurality of bumps (bumps) are provided on the CHIP surface as contact areas for connecting the internal leads of the CHIP with the external package solder balls.

Disclosure of Invention

Particularly inside the chip, a pressure sensitive circuit, particularly an analog circuit such as P LL (Phase-L ock L oop), exists in the area adjacent to the bump, and the existence of the bump may cause the electrical characteristics of the chip to be unstable, and the yield of the chip to be taped is reduced.

The inventor further finds that a Voltage Controlled Oscillator (VCO) in the P LL is particularly sensitive to the bumps, and therefore proposes the present application to avoid the P LL, especially the VCO area of the P LL, when the bumps are laid out, so as to reduce the influence of the bumps on the yield of the chip, and enable the chip to be produced in mass production.

According to a first aspect of the present application, there is provided a Bump (Bump) pad layout method in a first integrated circuit design according to the first aspect of the present application, comprising: placing a circuit unit; selecting one or more circuit units from the placed circuit units, wherein the one or more circuit units are sensitive to influences caused by the bump pads; acquiring one or more sensitive areas where the one or more circuit units are located; placing a bump plate on the surface layer of the designed integrated circuit; identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface of the integrated circuit; and adjusting the position of the one or more bump pads away from the corresponding area of the one or more sensitive areas on the surface of the integrated circuit.

According to the bump pad layout method in the first integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the second integrated circuit design of the first aspect of the present application, further comprising: and if the position of the first bump pad which can leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the integrated circuit design cannot be found, deleting the first bump pad.

The bump pad layout method in the first or second integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the third integrated circuit design according to the first aspect of the present application, further comprising: for a first bump pad positioned in a corresponding area of the first sensitive area on the surface layer of the integrated circuit, determining the center of the first sensitive area on the first corresponding area of the surface layer of the integrated circuit; changing the position of the first bump pad in a direction away from the center of the first corresponding region such that the first bump pad is away from the first corresponding region.

According to the bump pad layout method in the first integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the fourth integrated circuit design of the first aspect of the present application, further comprising: if the position of the first salient point disk, which enables the first salient point disk to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and not violate the constraint condition of the integrated circuit design, cannot be found, marking the first salient point disk as a to-be-deleted state; and adjusting the positions of other bump pads except the first bump pad in the one or more bump pads to enable the other bump pads to be separated from the corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit.

According to the bump pad layout method in the fourth integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the fifth integrated circuit design of the first aspect of the present application, further comprising: and deleting all the bump disks marked as the states to be deleted.

There is provided a bump pad layout method in a sixth integrated circuit design according to the first aspect of the present application, wherein the one or more circuit cells are analog circuit cells, according to one of the bump pad layout methods in the first to fifth integrated circuit designs according to the first aspect of the present application.

According to the bump pad layout method in the sixth integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the seventh integrated circuit design of the first aspect of the present application, wherein the one or more circuit units are P LL units, radio frequency units and/or analog-to-digital conversion units.

According to the bump pad layout method in the seventh integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the eighth integrated circuit design of the first aspect of the present application, wherein the one or more sensitive regions are regions where VCOs of P LL cells are located.

According to one of the bump pad layout methods in the first to eighth integrated circuit designs of the first aspect of the present application, the bump pad layout method in the ninth integrated circuit design according to the first aspect of the present application is provided, further comprising performing RD L design to establish a connection between the bump pad and the circuit unit.

According to one of the bump pad layout methods in the first to ninth integrated circuit designs of the first aspect of the present application, there is provided the bump pad layout method in the tenth integrated circuit design of the first aspect of the present application, wherein the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit is an area obtained by projecting the one or more sensitive areas on the surface layer of the designed integrated circuit.

In accordance with one of the bump pad layout methods in the tenth integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the ninth integrated circuit design of the eleventh aspect of the present application, wherein the one or more sensitive regions are located at each layer of the integrated circuit having the 3D structure or at a plurality of layers adjacent to the surface layer.

According to a second aspect of the present application, there is provided a first computer according to the second aspect of the present application, comprising a memory, a processor and a program stored on the memory and executable on the processor, wherein the program, when executed by the processor, implements one of the methods of bump pad layout in an integrated circuit design according to the first aspect of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a top view of a chip according to an embodiment of the present application;

FIG. 2 shows a schematic diagram of a bump-on-chip layout according to an embodiment of the present application;

FIG. 3 shows a schematic diagram of a bump-on-chip layout according to yet another embodiment of the present application; and

fig. 4 shows a flow chart of a chip design according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 shows a top view of the chip. In fig. 1, the normal line of the chip surface is parallel to the line of sight.

The layer where the leads connecting the Bump pads are located is referred to as RD L (Redistribution layer, Redistribution L eye), the network formed by the leads connecting the Bump pads is referred to as RD L network, and the Bump pads may also be directly disposed on the top metal layer of the chip.

It is understood that the RD L network and the bumps may be located on different layers of the chip, and when the bumps are visible, the leads of the RD L network cannot be directly observed due to the shielding of the chip structure.

Fig. 2 shows a schematic diagram of a bump layout on a chip according to an embodiment of the present application.

The surface of the chip is provided with a plurality of bump pads, and below the surface, in the area indicated by the box 240, P LL cells are placed, whereas the P LL cells include VCOs, occupying the area indicated by the shaded box 260.

According to an embodiment of the present application, because the VCO is sensitive to bumps, the bump pads are placed on the surface layer of the chip, avoiding the underlying VCO area block 260. referring to FIG. 2, block 260 has 4 bump pads (210, 212, 214, and 216) around the corresponding locations on the surface layer. by changing the placement of these bump pads a sufficient distance from the corresponding areas of block 260 on the surface layer. by way of example, referring also to FIG. 2, bump pad 220 and bump pad 222 are moved to the right and bump pad 210 and bump pad 212 are moved to the left with respect to the original locations of the bump pads. by moving bump pad 222, the spacing of the leads coupling bump pad 222 to the leads coupling bump pad 230 is moved too small and bump pad 230 is moved to the right so that the spacing of the leads of the network coupling RD L meets specified constraints.A significant factor of the electrical stability of the electrical circuit quality P32 formed during growth of the bump pads LL is ensured by changing the placement of the 4 bump pads (210, 212, 214, and 216) so that their corresponding blocks 260 on the surface layer of the chip are avoided.

While the other bump pads in fig. 2 are placed in their original positions because there is no circuitry sensitive to the effects of pressure, etc. on the bump pads, which is underneath the area where these bump pads are located.

Fig. 3 shows a schematic diagram of a bump-on-chip layout according to yet another embodiment of the present application.

Within the area of the chip shown in fig. 3, a plurality of VCO areas are provided, each illustrated by blocks (310, 320, 330 and 340).

According to the default arrangement rule of the cam plates, for example, in block 310, 2 cam plates (shown as 350 and 352) should be placed. Since block 310 is occupied by the VCO, its corresponding chip surface area cannot be populated with bump pads. Moreover, because there is a constraint condition on the distance between adjacent bump pads, the distance between adjacent bump pads is not less than a specified threshold, and an attempt to adjust the bump pads 350 and 352 cannot find a proper position on the surface layer of the chip. In the case where the placement requirements of the bump pads conflict with those of the areas corresponding to the VCOs, the placement requirements of the areas corresponding to the VCOs are preferentially satisfied, thereby eliminating the two bump pads (350 and 352) that cause the conflict.

Similarly, in the corresponding table regions of the blocks (320, 330 and 340) where the VCO is located, the bump pads may also need to be deleted or not placed.

Fig. 4 shows a flow chart of a chip design according to an embodiment of the present application.

The chip design flow illustrated in fig. 4, after being applied to, for example, a layout (Floorplan) design, lays out (410) one or more circuit cells of the designed chip, selects a circuit cell that is sensitive to an influence (e.g., pressure) caused by a bump from among the laid out electrical cells, selects, for example, a P LL cell, an analog-to-digital conversion cell, a radio frequency cell, or other analog circuit cells, marks a sensitive area (420) of the selected circuit cell that is sensitive to the influence caused by the bump, marks, for example, a P LL cell, a VCO area where the pressure is sensitive, marks, for the radio frequency cell, a receiver area and a transmitter area where the receiver and the transmitter are located, marks, for the analog-to-digital conversion cell, a sampling circuit area where the sampling circuit is located, and the like.

With continued reference to fig. 4, a bump pad (430) is placed on the surface layer region of the chip. There are a plurality of bump pads, and generally, a plurality of bump pads are disposed in an array form at equal intervals on the chip surface. For the placed one or more bump pads, it is identified whether they are located in the corresponding areas of the chip surface where the sensitive areas marked in step 420 are located (440). The sensitive region is formed on the surface layer by projecting the sensitive region on the surface layer of the chip relative to the surface layer on which the bump pad is placed. The sensitive area may be the same size and shape as its counterpart on the surface layer, or scaled to the same shape but different size. For the 3D structured chip, the sum of the areas formed by the projection of the sensitive area of each layer (or multiple layers adjacent to the surface layer) of the 3D structure on the surface layer is used as the corresponding area of the sensitive area of the 3D structured chip on the surface layer.

For the bump pads located in the corresponding areas of the sensitive area, the bump pads are removed from the sensitive area by adjusting the positions of the bump pads (450). For example, the sensitive area is determined at the center of the corresponding area on the chip surface, the position of the bump pad is changed in a direction away from the center with respect to the center, or the bump pad is moved in a direction away from the center on a line connecting the bump pad and the center. Still alternatively, the bump pad is moved in a direction parallel to the long or short side of the paper surface in fig. 1 to 3, and away from the center. If the position for placing the bump pad can be found by moving the bump pad so that the bump pad is away from the sensitive area in the corresponding area on the chip surface without violating other constraints of the chip design (e.g., the distance from other bump pads is not less than a specified threshold), the bump pad is placed in the found position. And if the position meeting all the constraint conditions cannot be found to place the convex point disk, deleting the convex point disk. As yet another example, for a bump pad located in a corresponding area of the sensitive area, the bump pad and one or more surrounding bump pads are moved as a whole to find a suitable location for placement of the bump pad. Still alternatively, for a bumped disk that cannot find a suitable placement, it is temporarily marked to be deleted, rather than deleting the bumped disk, and the process goes to step 440 to process other bumped disks located in the surface area corresponding to the sensitive area.

After step 450, the process goes to step 440 where other bumped pads located in the surface area corresponding to the sensitive area are processed, and if there are no bumped pads located in the surface area corresponding to the sensitive area, the process goes to step 460 where RD L (redistribution layer) design is performed to establish connections between the bumped pads and the electrical components (circuit units).

Optionally, in step 440, if there are some bumped disks marked as pending deletion, after other bumped disks are placed in the proper positions, the proper positions are found again for the bumped disks marked as pending deletion. If the appropriate location still cannot be found, the cam disks are deleted.

According to the embodiment of the application, the sensitive areas existing in one or more layers in the chip are identified, the corresponding areas of the sensitive areas are marked in the surface layer provided with the salient points, and the salient point disc is prevented from being placed in the corresponding areas, so that the influence of the salient point disc on the sensitive areas in the chip is reduced or even eliminated, and the success rate and the yield of chip flow are improved.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.