阅读说明：本技术 一种基于soi工艺的静电放电保护结构 (Electrostatic discharge protection structure based on SOI technology ) 是由 单毅 董业民 陈晓杰 于 2019-08-06 设计创作，主要内容包括：本发明公开了一种基于SOI工艺的静电放电保护结构,包括SOI衬底以及位于SOI衬底上的ESD保护器件；ESD保护器件包括第一导电区域、第二导电区域和第三导电区域,第一导电区域、第二导电区域和第三导电区域位于同一平面上,第三导电区域分别与第一导电区域和第二导电区域接触；第一导电区域上形成有第一电极,第二导电区域上形成有第二电极,第三导电区域的上方设有用于硅化物阻挡层,硅化物阻挡层将第一电极与第二电极隔离。本发明通过硅化物阻挡层将第一电极与第二电极隔离开,在发生ESD冲击时,寄生三极管导通,泄放ESD电流,对被保护电路起到保护作用。本发明的静电放电保护结构使得ESD电流流向更深区域,能够有效地提升器件的静电放电保护能力。(The invention discloses an electrostatic discharge protection structure based on an SOI (silicon on insulator) process, which comprises an SOI (silicon on insulator) substrate and an ESD (electro-static discharge) protection device positioned on the SOI substrate; the ESD protection device comprises a first conductive area, a second conductive area and a third conductive area, wherein the first conductive area, the second conductive area and the third conductive area are positioned on the same plane, and the third conductive area is respectively contacted with the first conductive area and the second conductive area; a first electrode is formed on the first conductive region, a second electrode is formed on the second conductive region, a silicide blocking layer is arranged above the third conductive region, and the first electrode is separated from the second electrode by the silicide blocking layer. The first electrode and the second electrode are isolated by the silicide barrier layer, and when ESD impact occurs, the parasitic triode is conducted to discharge ESD current, so that a protected circuit is protected. The electrostatic discharge protection structure enables ESD current to flow to a deeper area, and can effectively improve the electrostatic discharge protection capability of the device.)

1. An electrostatic discharge protection structure based on an SOI process is characterized by comprising an SOI substrate and an ESD protection device positioned on the SOI substrate;

the ESD protection device comprises a first conductive region (1), a second conductive region (2) and a third conductive region (3), wherein the first conductive region (1), the second conductive region (2) and the third conductive region (3) are located on the same plane, and the third conductive region (3) is respectively contacted with the first conductive region (1) and the second conductive region (2);

a first electrode (7) is formed on the first conductive region (1), a second electrode (8) is formed on the second conductive region (2), a silicide blocking layer (6) for blocking silicide formation is arranged above the third conductive region (3), and the first electrode (7) is isolated from the second electrode (8) by the silicide blocking layer (6).

2. The SOI process based electrostatic discharge protection structure according to claim 1, characterized in that the area of the silicide blocking layer (6) is formed to cover the area above the third conductive region (3).

3. The SOI process-based electrostatic discharge protection structure according to claim 1, wherein the SOI substrate comprises a back substrate, a buried oxide layer (4) and a top silicon layer sequentially arranged from bottom to top, and the first conductive region (1), the second conductive region (2) and the third conductive region (3) are all formed to penetrate into the buried oxide layer (4).

4. The SOI process based electrostatic discharge protection structure according to claim 3, wherein the first conductive region (1) is formed as a first conductivity type doped source region, the second conductive region (2) is formed as a first conductivity type doped drain region, the third conductive region (3) is formed as a second conductivity type well region, and the ESD protection device is configured as a MOS transistor.

5. The SOI process-based electrostatic discharge protection structure according to claim 4, wherein the ESD protection device comprises a plurality of the MOS transistors, and the plurality of the MOS transistors are connected in parallel.

6. The SOI process based electrostatic discharge protection structure according to claim 3, wherein the first conductive region (1) is formed as a first conductive type ion implantation region, the second conductive region (2) is formed as a second conductive type ion implantation region, the third conductive region (3) is formed as a first conductive type or a second conductive type well region, and the ESD protection device is configured as a diode.

7. The SOI process-based electrostatic discharge protection structure of claim 6, wherein the ESD protection device comprises a plurality of the diodes, and the plurality of the diodes are connected in parallel.

8. The SOI process-based electrostatic discharge protection structure according to claim 5 or 7, wherein the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.

9. The SOI process-based electrostatic discharge protection structure according to claim 3, wherein shallow trench isolation structures (5) are provided on both sides of the ESD protection device, and the shallow trench isolation structures (5) are deep into the buried oxide layer (4).

10. The SOI process-based electrostatic discharge protection structure according to claim 1, wherein the first electrode (7) is connected to a positive electrode, and the second electrode (8) is connected to a negative electrode; or the first electrode (7) is connected with a negative electrode, and the second electrode (8) is connected with a positive electrode.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an electrostatic discharge protection structure based on an SOI (silicon on insulator) process.

Background

Static electricity is an objective natural phenomenon and is generated in various ways, such as contact, friction, induction between electrical appliances and the like. Static electricity is characterized by long-term accumulation, high voltage, low electricity, low current and short action time. Static electricity poses a serious hazard in at least two areas. Triboelectrification and human body static electricity are two major hazards in the electronic industry, and often cause unstable operation and even damage of electronic and electric products. Electrostatic Discharge (ESD) protection is an important link in Integrated Circuit (IC) design, and with the process being more and more advanced, especially in a novel SOI (Silicon-On-Insulator) process, due to the existence of a Buried Oxide (BOX), the top layer Silicon thickness is much thinner than that of a conventional bulk Silicon process, which makes it more difficult to Discharge current, and at the same time, the current tends to concentrate, which makes the heat dissipation problem of the device more serious, so that the device is more easily burned, and the Electrostatic Discharge protection capability of the device becomes a greater bottleneck.

The NMOS transistor is a cross-sectional schematic diagram of a two-finger parallel NMOS structure, as shown in FIG. 1, wherein, when a positive ESD pulse is applied to PAD, a parasitic triode NPN formed by a drain (N +) -P well-source (N +) is turned on to drain an ESD current and protect other protected circuits, in order to reduce a short channel effect generated when the NMOS is turned on in a normal channel, an N-type L DD lightly doped region (N L DD) and a P-type HA L O doped region (PHA L O) are arranged at a boundary of the source and the drain, however, due to the existence of the N L DD/L O region, when the electrostatic discharge phenomenon occurs, a tip discharge phenomenon is very easily generated at a junction of N L DD/PHA L O, thereby causing breakdown and causing the device to be burned down.

Accordingly, there is a need to provide an esd protection structure to solve the above-mentioned problems.

Disclosure of Invention

The invention aims to provide an electrostatic discharge protection structure based on an SOI (silicon on insulator) process, which is used for overcoming the technical problem of poor ESD (electro-static discharge) protection performance of the electrostatic discharge protection structure based on the SOI process in the prior art.

The invention is realized by the following technical scheme:

the invention provides an electrostatic discharge protection structure based on an SOI (silicon on insulator) process, which comprises an SOI (silicon on insulator) substrate and an ESD (electro-static discharge) protection device positioned on the SOI substrate; the ESD protection device comprises a first conductive area, a second conductive area and a third conductive area, wherein the first conductive area, the second conductive area and the third conductive area are positioned on the same plane, and the third conductive area is respectively contacted with the first conductive area and the second conductive area; a first electrode is formed on the first conductive region, a second electrode is formed on the second conductive region, a silicide blocking layer for blocking silicide formation is arranged above the third conductive region, and the first electrode is isolated from the second electrode by the silicide blocking layer.

Further, the area of the silicide block layer is formed to cover the region above the third conductive region.

Further, the SOI substrate includes a back substrate, a buried oxide layer, and a top silicon layer sequentially disposed from bottom to top, and the first conductive region, the second conductive region, and the third conductive region are all formed to penetrate into the buried oxide layer.

Further, the first conductive region is formed as a first conductive-type doped source region, the second conductive region is formed as a first conductive-type doped drain region, the third conductive region is formed as a second conductive-type well region, and the ESD protection device is configured as a MOS transistor.

Further, the ESD protection device includes a plurality of the MOS transistors, which are connected in parallel.

Further, the first conductive region is formed as a first conductive type ion implantation region, the second conductive region is formed as a second conductive type ion implantation region, the third conductive region is formed as a first conductive type or second conductive type well region, and the ESD protection device is configured as a diode.

Further, the ESD protection device includes a plurality of the diodes, which are connected in parallel.

Further, the first conductive type is a P type, and the second conductive type is an N type; or, the first conductivity type is N-type, and the second conductivity type is P-type.

Furthermore, shallow trench isolation structures are arranged on two sides of the ESD protection device and penetrate into the oxygen burying layer.

Further, the first electrode is connected with a positive electrode, and the second electrode is connected with a negative electrode; or the first electrode is connected with the negative electrode, and the second electrode is connected with the positive electrode.

The implementation of the invention has the following beneficial effects:

according to the electrostatic discharge protection structure based on the SOI process, the first electrode and the second electrode are separated through the silicide barrier layer, and when ESD impact occurs, a parasitic triode formed by the first conductive area, the second conductive area and the third conductive area is conducted to form a low-resistance path to discharge ESD current, so that the electrostatic discharge protection effect is achieved on other protected circuits. Compared with the mode of using the grid electrode to protect the circuit in the prior art, the electrostatic discharge protection structure eliminates the phenomenon of device breakdown and burnout caused by point discharge of the grid electrode because the grid electrode is not used, and enables ESD current to flow to a deeper area, thereby avoiding the current from concentrating on the surface of the device, preventing the device from being burnt out due to overheating caused by overlarge local current, and effectively improving the electrostatic discharge protection capability of the device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic cross-sectional view of a prior art NMOS transistor based on SOI process;

fig. 2 is a schematic cross-sectional view of an electrostatic discharge protection structure based on SOI process according to an embodiment of the present invention.

Wherein the reference numerals correspond to: the structure comprises a first conductive region 1, a fourth conductive region 1 '-1, a second conductive region 2, a third conductive region 3, a fifth conductive region 3' -4, an oxygen buried layer 5, a shallow trench isolation structure 6, a silicide blocking layer 7, a first electrode 8 and a second electrode 8.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following examples. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms first, second, third and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.