阅读说明：本技术 一种硅控整流器及其制造方法 (Silicon controlled rectifier and manufacturing method thereof ) 是由 朱天志 黄冠群 陈昊瑜 邵华 于 2020-04-28 设计创作，主要内容包括：本发明提供了一种硅控整流器及其制造方法,硅控整流器包括：P型衬底80；P型衬底80中的N型阱60和P型阱70；N型阱60的上部具有构成阳极的P型重掺杂区20和N型重掺杂区28,N型重掺杂区28靠近N型阱60和P型阱70之间的交界面,N型重掺杂区28与交界面之间为N型阱60的有源区；以及P型阱70的上部具有构成阴极的P型重掺杂区26和N型重掺杂区24,N型重掺杂区24靠近交界面,N型重掺杂区24与交界面之间具有与N型重掺杂区24邻接的浅沟槽隔离,浅沟槽隔离与交界面之间为P型阱70的有源区。根据本发明所提供的制造方法所制造的硅控整流器能够提高无回滞效应硅控整流器的触发电压,有利于减少多级串联应用所需的串联级数,能够节省版图面积。(The invention provides a silicon controlled rectifier and a manufacturing method thereof, wherein the silicon controlled rectifier comprises: a P-type substrate 80; an N-type well 60 and a P-type well 70 in a P-type substrate 80; the upper part of the N-type well 60 is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28 which form an anode, the N-type heavily doped region 28 is close to the interface between the N-type well 60 and the P-type well 70, and an active region of the N-type well 60 is arranged between the N-type heavily doped region 28 and the interface; and the upper part of the P-type well 70 is provided with a P-type heavily doped region 26 and an N-type heavily doped region 24 which form a cathode, the N-type heavily doped region 24 is close to an interface, shallow trench isolation adjacent to the N-type heavily doped region 24 is arranged between the N-type heavily doped region 24 and the interface, and an active region of the P-type well 70 is arranged between the shallow trench isolation and the interface. The silicon controlled rectifier manufactured by the manufacturing method provided by the invention can improve the trigger voltage of the silicon controlled rectifier without hysteresis effect, is beneficial to reducing the series stages required by multistage series application, and can save the layout area.)

1. A silicon controlled rectifier, comprising:

a P-type substrate (80);

an N-type well (60) and a P-type well (70) in the P-type substrate (80), the N-type well (60) and the P-type well (70) having an interface therebetween;

the upper part of the N-type well (60) is provided with a P-type heavily doped region (20) and an N-type heavily doped region (28) which form the anode of the silicon controlled rectifier, the N-type heavily doped region (28) is close to the interface, and an active region of the N-type well (60) is arranged between the N-type heavily doped region (28) and the interface; and

the upper portion of the P-type trap (70) is provided with a P-type heavily doped region (26) and an N-type heavily doped region (24) which form a cathode of the silicon controlled rectifier, the N-type heavily doped region (24) is close to the interface, shallow trench isolation (90) is arranged between the N-type heavily doped region (24) and the interface, the shallow trench isolation (90) is adjacent to the N-type heavily doped region (24), and an active region of the P-type trap (70) is arranged between the shallow trench isolation (90) and the interface.

2. The silicon controlled rectifier of claim 1, wherein a width D1 of the active region between the heavily N-doped region (28) and the interface is related to a trigger voltage of the silicon controlled rectifier.

3. The SCR of claim 2 wherein the width D1 is 0-2 μm.

4. The silicon controlled rectifier of claim 2 wherein the trigger voltage of the silicon controlled rectifier is further related to a width D3 of an active region between the shallow trench isolation (90) and the interface.

5. The SCR of claim 4 wherein the width D3 is 0-5 μm.

6. The SCR of claim 1 wherein the heavily P-doped region (20) and the heavily N-doped region (28) are between active regions of the N-well (60).

7. The SCR of claim 6 wherein the width D2 of the N-type heavily doped region (26) and the width S of the active region between the P-type heavily doped region (20) and the N-type heavily doped region (28) are associated with a no-hysteresis effect condition of the SCR.

8. The SCR of claim 7 wherein the width D2 is 0.4-10 microns and the width S is 0-2 microns.

9. A method for manufacturing a silicon controlled rectifier includes:

providing a P-type substrate (80);

forming an N-type well (60) and a P-type well (70) in the P-type substrate (80), the N-type well (60) and the P-type well (70) having an interface therebetween;

forming a P-type heavily doped region (20) and an N-type heavily doped region (28) which form an anode of the silicon controlled rectifier on the upper part of the N-type well (60), wherein the N-type heavily doped region (28) is close to the interface, and an active region of the N-type well (60) is arranged between the N-type heavily doped region (28) and the interface;

forming a P-type heavily doped region (26) and an N-type heavily doped region (24) which form a cathode of the silicon controlled rectifier on the upper part of the P-type well (70), wherein the N-type heavily doped region (24) is close to the interface; and

and forming shallow trench isolation (90) between the N-type heavily doped region (24) and the interface, wherein the shallow trench isolation (90) is adjacent to the N-type heavily doped region (24), and an active region of the P-type trap (70) is arranged between the shallow trench isolation (90) and the interface.

10. The method of manufacturing of claim 9, further comprising: and adjusting the width D1 of the active region between the N-type heavily doped region (28) and the interface to adjust the trigger voltage of the silicon controlled rectifier.

11. The method of manufacturing of claim 10, wherein the width D1 is 0-2 microns.

12. The method of manufacturing of claim 10, further comprising: adjusting a width D3 of an active region between the shallow trench isolation (90) and the interface to adjust a trigger voltage of the silicon controlled rectifier.

13. The method of manufacturing of claim 12, wherein the width D3 is adjusted within a range of 0-5 microns.

14. The method of manufacturing of claim 9, wherein between the heavily P-doped region (20) and the heavily N-doped region (28) is an active region of the N-well (60).

15. The method of manufacturing of claim 14, further comprising: and adjusting the width D2 of the N-type heavily doped region (26) and the width S of an active region between the P-type heavily doped region (20) and the N-type heavily doped region (28) to adjust the no-hysteresis effect state of the silicon controlled rectifier.

16. The method of manufacturing of claim 15, wherein the width D2 is adjusted in the range of 0.4-10 microns and the width S is adjusted in the range of 0-2 microns.

Technical Field

The invention relates to the field of semiconductors, in particular to a silicon controlled rectifier structure without hysteresis effect and a manufacturing method thereof.

Background

The design of the anti-static protection of the high-voltage circuit is always a technical problem because the core of the high-voltage circuit is that a high-voltage device (for example, L DMOS) is not suitable for the anti-static protection design like a common low-voltage device, because the hysteresis effect curve of the high-voltage device shows poor characteristics, which are reflected in the following two points that 1, the maintaining voltage (Vh) is too low and is often greatly lower than the working voltage of the high-voltage circuit, the latch-up effect is easily caused when the high-voltage circuit works normally, and 2, the secondary breakdown Current (It2) is too low, which is caused by that L DMOS generate local Current congestion due to the structural characteristics of the device when the ESD Current is discharged (L oclized Current crowning).

Therefore, when the anti-static protection design of the high-voltage circuit is solved, two ideas are usually adopted to realize the following steps: 1. the structure of a high-voltage device used for the anti-static protection module is adjusted, and the hysteresis effect curve of the high-voltage device is optimized, so that the high-voltage device is suitable for anti-static protection design, but the high-voltage device is difficult to practice due to the structural characteristics of the high-voltage device; 2. a certain number of low-voltage anti-static protection devices are connected in series to form an anti-static protection circuit capable of bearing high voltage. For the second concept, because the characteristics of the low voltage esd protection devices are relatively easy to adjust and control, the industry, especially integrated circuit design companies, often prefer to use a method of connecting a certain number of low voltage esd protection devices in series to achieve the esd protection design of the high voltage circuit.

Because of the requirement of the anti-static protection design window of the high-voltage circuit, there is a certain requirement on the hysteresis effect characteristic of the low-voltage anti-static protection device, and it is often required that the hysteresis effect is as small as possible, and preferably no hysteresis effect is required, that is, the holding voltage and the trigger voltage of the hysteresis effect are basically consistent. The low-voltage PMOS device is a common electrostatic protection device without hysteresis effect, because the parasitic PNP triode has smaller current gain when hysteresis effect occurs, but the low-voltage PMOS device has the defect that the secondary breakdown current (It2) of the hysteresis effect is smaller, and therefore, the anti-electrostatic protection device without hysteresis effect and with higher secondary breakdown current is researched and developed in the industry.

The industry has proposed a new type of No-hysteretic effect silicon controlled rectifier (No-Snapback SCR) in 2015. as shown in fig. 1, the SCR 100 includes a P-type substrate 180 having an N-well 160 and a P-well 170 therein, the N-well 160 and the P-well 170 abutting each other to form a PN Junction (PN Junction) at the interface of the N-well 160 and the P-well 170. A heavily P-doped region 122 is formed at an upper portion of the interface of the N-well 160 and the P-well 170. An N-type heavily doped region 128, a P-type heavily doped region 120 and an N-type heavily doped region 130 are sequentially formed on the upper portion of the N-type well 160. The heavily P-doped region 120 and the heavily N-doped region 130 form an anode a of the scr 100. The heavily doped N-type region 128 is close to the heavily doped P-type region 122, and a distance is formed between the heavily doped N-type region 128 and the heavily doped P-type region 122. The heavily doped N-type region 128, the heavily doped P-type region 120, and the heavily doped N-type region 130 are spaced apart from each other by the shallow trench isolation 110. The P-well 170 has a heavily P-doped region 126 and a heavily N-doped region 124 formed thereon, which form the cathode K of the scr. The heavily doped N-type region 124 is adjacent to the heavily doped P-type region 122, and the heavily doped P-type region 122, the heavily doped N-type region 124, and the heavily doped P-type region 126 are separated from each other by the shallow trench isolation 110.

Experimental data of the scr without hysteresis effect as shown in fig. 1 show that when the sizes of the N-type heavily doped region 128 and the P-type heavily doped region 122 reach a certain degree (greater than 4um), the scr exhibits the characteristic of no hysteresis effect, and is very suitable for the requirement of series connection of low-voltage devices for the anti-static protection design of a high-voltage circuit. However, the novel silicon controlled rectifier without hysteresis effect has the disadvantage that the size of the device is large, and particularly when multistage series connection is needed, the layout area is large.

Based on the scr without hysteresis shown in fig. 1, a further scr without hysteresis as shown in fig. 2 has been proposed in the industry by chinese patent (grant No.: CN 108183101B). The cathode portion of the scr 200 shown in fig. 2 is the same as the cathode portion of the scr 100, and for the N-type heavily doped region 128 that is originally floating and directly connected to the anode a, i.e. the N-type heavily doped region 228 in fig. 2, this enables the N-type heavily doped region 228 to effectively reduce the probability that holes migrate to the interface of the N-type well 260/the P-type well 270 after being injected from the P-type heavily doped region 220 to the N-type well 260, that is, the efficiency of the N-type heavily doped region 228 as a guard ring is further improved, so the width of the N-type heavily doped region 228 can be designed to be smaller, and the layout area is saved. In addition, the heavily doped N-type region 228 serves as an N-type well 260 connection point (Pick up), so that the heavily doped N-type region 130, which is connected to the N-type well 260 connection point in the existing thyristor without hysteresis in fig. 1, can be further removed, thereby further saving the layout area.

However, with the development of semiconductor technology, the pursuit of saving layout area is further increased, and therefore, in order to further reduce the layout area occupied by the scr without hysteresis effect, the trigger voltage of the scr without hysteresis effect needs to be further increased, so that the number of series stages required when the multistage series is applied to high-voltage anti-static protection can be reduced.

In view of the above, it is desirable to develop a hysteretic-effect-free scr capable of further increasing the trigger voltage, so as to reduce the number of series stages required for the multi-stage series application in the high-voltage anti-static protection, thereby achieving the purpose of saving layout area.

Disclosure of Invention

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

In order to further improve the trigger voltage of the scr without hysteresis effect and further save the layout area, an aspect of the present invention provides a scr, which specifically includes:

a P-type substrate (80);

an N-type well (60) and a P-type well (70) in the P-type substrate (80), the N-type well (60) and the P-type well (70) having an interface therebetween;

the upper part of the N-type well (60) is provided with a P-type heavily doped region (20) and an N-type heavily doped region (28) which form the anode of the silicon controlled rectifier, the N-type heavily doped region (28) is close to the interface, and an active region of the N-type well (60) is arranged between the N-type heavily doped region (28) and the interface; and

the upper part of the P-type trap (70) is provided with a P-type heavily doped region (26) and an N-type heavily doped region (24) which form the cathode of the silicon controlled rectifier, the N-type heavily doped region (24) is close to the interface, a shallow trench isolation (90) is arranged between the N-type heavily doped region (24) and the interface, the shallow trench isolation (90) is adjacent to the N-type heavily doped region (24), and the active region of the P-type trap (70) is arranged between the shallow trench isolation (90) and the interface.

In an embodiment of the scr, optionally, a width D1 of the active region between the heavily N-doped region (28) and the interface is related to a trigger voltage of the scr.

In an embodiment of the scr, the width D1 is optionally 0-2 μm.

In an embodiment of the scr, optionally, the trigger voltage of the scr is further related to a width D3 of an active region between the shallow trench isolation (90) and the interface.

In an embodiment of the scr, the width D3 is optionally 0-5 μm.

In an embodiment of the scr, optionally, an active region of the N-well (60) is located between the P-type heavily doped region (20) and the N-type heavily doped region (28).

In an embodiment of the scr, optionally, the width D2 of the N-type heavily doped region (26) and the width S of the active region between the P-type heavily doped region (20) and the N-type heavily doped region (28) are associated with a no-hysteresis effect state of the scr.

In an embodiment of the scr, the width D2 is 0.4-10 microns, and the width S is 0-2 microns.

The invention also provides a manufacturing method of the silicon controlled rectifier, which specifically comprises the following steps:

providing a P-type substrate (80);

forming an N-type well (60) and a P-type well (70) in the P-type substrate (80), the N-type well (60) and the P-type well (70) having an interface therebetween;

forming a P-type heavily doped region (20) and an N-type heavily doped region (28) which form an anode of the silicon controlled rectifier on the upper part of the N-type well (60), wherein the N-type heavily doped region (28) is close to the interface, and an active region of the N-type well (60) is arranged between the N-type heavily doped region (28) and the interface;

forming a P-type heavily doped region (26) and an N-type heavily doped region (24) which form a cathode of the silicon controlled rectifier on the upper part of the P-type well (70), wherein the N-type heavily doped region (24) is close to the interface; and

and forming shallow trench isolation (90) between the N-type heavily doped region (24) and the interface, wherein the shallow trench isolation (90) is adjacent to the N-type heavily doped region (24), and an active region of the P-type well (70) is arranged between the shallow trench isolation (90) and the interface.

In an embodiment of the foregoing manufacturing method, optionally, the method further includes: and adjusting the width D1 of the active region between the N-type heavily doped region (28) and the interface to adjust the trigger voltage of the silicon controlled rectifier.

In an embodiment of the manufacturing method, optionally, the width D1 is 0 to 2 micrometers.

In an embodiment of the foregoing manufacturing method, optionally, the method further includes: the width D3 of the active region between the STI 90 and the interface is adjusted to adjust the trigger voltage of the SCR.

In an embodiment of the manufacturing method, the width D3 is optionally adjusted within a range of 0-5 μm.

In an embodiment of the manufacturing method, optionally, an active region of the N-type well (60) is located between the P-type heavily doped region (20) and the N-type heavily doped region (28).

In an embodiment of the foregoing manufacturing method, optionally, the method further includes: and adjusting the width D2 of the N-type heavily doped region (26) and the width S of the active region between the P-type heavily doped region (20) and the N-type heavily doped region (28) to adjust the no-hysteresis effect state of the silicon controlled rectifier.

In an embodiment of the manufacturing method, optionally, the width D2 is adjusted within a range of 0.4-10 microns, and the width S is adjusted within a range of 0-2 microns.

According to the silicon controlled rectifier, the reverse breakdown voltage of a parasitic PN diode determining the trigger voltage of the silicon controlled rectifier is increased, so that the trigger voltage of the silicon controlled rectifier without hysteresis effect is increased within a certain range, the reduction of series stages required by multistage series connection applied to high-voltage anti-static protection is facilitated, and the purpose of saving the layout area is achieved. The manufacturing method of the silicon controlled rectifier provided by the invention is compatible with the existing CMOS process, and can manufacture the silicon controlled rectifier without hysteresis effect, which can further improve the trigger voltage, under the condition of not increasing the manufacturing complexity.

Drawings

The above features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.

Fig. 1 shows a schematic structural diagram of a prior art scr.

Fig. 2 shows a schematic structure diagram of another scr in the prior art.

Fig. 3 is a schematic flow chart illustrating an embodiment of a method for manufacturing a scr according to an aspect of the present invention.

Fig. 4 is a schematic structural diagram of an embodiment of a scr provided by an aspect of the present invention.

Fig. 5 is a schematic diagram illustrating an application scenario of the scr provided by an aspect of the present invention.

Reference numerals

100. 200 silicon controlled rectifier

110 shallow trench isolation

120. 122, 126P type heavily doped region

124. 128, 130N type heavily doped region

160N type well

170P type trap

180P type substrate

210 shallow trench isolation

220. 222, 226P type heavily doped region

224. 228N type heavily doped region

260N type well

270P type trap

280P type substrate

10 shallow trench isolation

20. 26P type heavily doped region

24. 28N type heavily doped region

60N type well

70P type trap

80P type substrate

90 shallow trench isolation

Detailed Description

In order to further improve the trigger voltage of the SCR without hysteresis effect, the invention provides a SCR structure and a manufacturing method thereof. Other embodiments are also provided.

The following description is presented to enable any person skilled in the art to make and use the invention and is incorporated in the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the practice of the invention may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Note that where used, the designations left, right, front, back, top, bottom, positive, negative, clockwise, and counterclockwise are used for convenience only and do not imply any particular fixed orientation. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object.

The terms "over.," under., "" between., "(between)," and ". on.," as used herein refer to the relative position of this layer with respect to other layers. Likewise, for example, a layer deposited or placed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Further, a layer deposited or placed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with the second layer. In addition, the relative position of one layer with respect to the other layers is provided (assuming deposition, modification and removal of the thin film operations with respect to the starting substrate without regard to the absolute orientation of the substrate).

As described above, the present invention provides a scr without hysteresis effect and a method for manufacturing the same, which can further increase the trigger voltage, and specifically, fig. 3 shows a schematic flow chart of the method for manufacturing the scr as shown in fig. 4.

As shown in fig. 3, step S101 is performed to provide a substrate. The substrate may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate may comprise an elemental semiconductor material, a compound semiconductor material, and/or an alloy semiconductor material. Examples of elemental semiconductor materials may be, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide. Examples of alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. In an embodiment, the substrate is a P-type substrate doped P-type.

In step S102, an N-type doped N-type well 60 and a P-type doped P-type well 70 are formed. Wherein each well is formed by at least three to five steps including but not limited to epitaxial growth, native oxide growth, ion implantation using a reticle, and again high energy ion implantation and an annealing process.

In step S102, the N-type well 60 is formed adjacent to the P-type well 70 with an interface between the N-type well 60 and the P-type well 70 where a PN junction can be formed.

Step S103, forming Shallow Trench Isolation (STI) in the corresponding position, where the STI process includes but is not limited to Shallow Trench etching, oxide filling, and oxide planarization. The shallow trench etching includes, but is not limited to, isolation oxide layer, nitride deposition, shallow trench isolation using a mask, and STI shallow trench etching. Wherein the STI oxide fill includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide fill, or PVD (physical vapor deposition) oxide fill. Wherein the planarization of the silicon wafer surface can be achieved by a variety of methods. The planarization of the wafer can be achieved by filling the gap with SOG (spin-on-glass) which can be composed of 80% solvent and 20% silicon dioxide, baking the SOG after deposition, evaporating the solvent to leave the silicon dioxide in the gap, or by etching back the entire surface to reduce the thickness of the entire wafer. Planarization processes, including but not limited to trench oxide polishing (chemical mechanical polishing may be used) and nitride removal, may also be effectively performed by CMP processes (also referred to as polishing processes). It should be appreciated by those skilled in the art that the above-mentioned shallow trench isolation can effectively achieve device-to-device electrical isolation between substrates.

In step S104, an N-type heavily doped region 28 is formed in the upper portion of the N-type well 60 near the interface, and an N-type heavily doped region 24 is formed in the upper portion of the P-type well 70 near the interface. In the present embodiment, the N-type dopant may include a dopant, such As arsenic (As), phosphorus (P), other group V element, or a combination thereof. In one embodiment, heavily N-doped region 28 and heavily N-doped region 24 have the same ion doping concentration. The interface between the heavily doped N-type region 28 and the P/N well is spaced apart by a distance, i.e., the interface between the heavily doped N-type region 28 and the P/N well is the active region of the N-type well 60. The shallow trench isolation 90 formed in step S103 is located between the interface between the heavily doped N-type region 24 and the P/N well, the shallow trench isolation 90 is adjacent to the heavily doped N-type region 24, and the interface between the shallow trench isolation 90 and the P/N well is separated by a distance S, i.e., the interface between the shallow trench isolation 90 and the P/N well is the active region of the P-well 70.

Since the N-well 60 with the width D1 and the P-well 70 with the width D3 are respectively arranged on two sides of the interface, after the originally arranged P-type doped region at the interface is removed, the reverse breakdown voltage of the parasitic diode P-well 70/N-well 60 (N-type heavily doped region 28) inside the silicon controlled rectifier is determined by the width D1 of the active region of the N-well 60 between the N-type heavily doped region 28 and the interface and the width D3 of the active region of the P-well 70 between the shallow trench isolation 90 and the interface.

In the above embodiment, after the originally disposed P-type doped region at the interface is removed, since the P-end of the parasitic PN diode has a very low ion doping concentration, which is substantially equivalent to the N-type well 60, the upper limit of the reverse breakdown voltage of the parasitic P-i-N diode, which determines the trigger voltage inside the scr, is determined not by the PN junction formed by the P +/N-type well 60, but by the PN junction formed by the P-type well 70 and the N-type well 60, that is, the reverse breakdown voltage can be increased compared to the conventional structure, so as to increase the trigger voltage of the hysteresis effect.

The trigger voltage of the silicon controlled rectifier can be effectively improved within a certain range by improving the reverse breakdown voltage of a parasitic PN diode which determines the trigger voltage in the silicon controlled rectifier, and the performance of the device can be improved under the condition that the size of the device is not changed. Or the design size of the device can be reduced within a certain range under the condition of keeping the trigger voltage unchanged, so that the effect of saving the layout area can be achieved.

In one embodiment, the trigger voltage of the scr is adjusted by adjusting the width D1 of the active region of the N-well 60 between the heavily N-doped region 28 and the interface. In one embodiment, the width D1 can be adjusted to 0-2um to adjust the trigger voltage so that the SCR has trigger voltages meeting different requirements.

In another embodiment, the trigger voltage of the scr is also adjusted by adjusting the width D3 of the active region between the shallow trench isolation 90 and the interface. The width D3 of the active region between the shallow trench isolation 90 and the interface affects the width of the P-well 70/N-well 60 (N-type heavily doped region 28) of the parasitic diode in the depletion region of the P-well 70, and affects the reverse breakdown voltage of the parasitic PN diode, and in turn affects the trigger voltage of the scr. In one embodiment, the width of D3 can be adjusted within the range of 0-5 um to adjust the trigger voltage of the formed SCR.

In the above embodiment, the N-type heavily doped region 28 is directly connected to the anode a, which enables the N-type heavily doped region 28 to effectively reduce the probability that holes injected from the P-type heavily doped region 20 to the N-type well 60 migrate to reach the interface of the N-type well 60/the P-type well 70, that is, the efficiency of the N-type heavily doped region 28 as a guard ring is further improved, so the width of the N-type heavily doped region 28 can be designed to be smaller, and the layout area is saved. It is understood that in the above-described embodiment, the heavily doped N-type region 28 and the heavily doped N-type region 24 have the same ion doping concentration, so that the efficiency of the heavily doped N-type region 28 as a guard ring can be ensured.

In step S105, a P-type heavily doped region 20 is formed in the N-well 60 and a P-type heavily doped region 26 is formed in the P-well 70. In this embodiment, the P-type dopant may have a dopant, such as boron (B) or other group III element. In one embodiment, it is understood that heavily P-doped region 20 and heavily P-doped region 26 have the same ion doping concentration.

In the combining step 103, an active region of the N-type well 60 is located between the P-type heavily doped region 20 and the N-type heavily doped region 28 in the N-type well 60, and the arrangement of the active region between the P-type heavily doped region 20 and the N-type heavily doped region 28, i.e., the structure without shallow trench isolation, will affect the distribution of carrier holes after being injected into the N-type well 60 from P + 20. And shallow trench isolation is formed between the P-type heavily doped region 26 and the N-type heavily doped region 24 in the cathode portion of the scr.

In step S106, the P-type heavily doped region 20 and the N-type heavily doped region 28 are connected to the anode and the P-type heavily doped region 26 and the N-type heavily doped region 24 are connected to the cathode. The direct connection of the N-type heavily doped region 28 to the anode a not only can effectively improve the efficiency of the N-type heavily doped region 28 as a protection ring, but also can play a role of a junction of the N-type well 60, so that the N-type heavily doped region of the junction of the N-type well 60 does not need to be additionally arranged, and the layout area is saved.

It should be noted that although the flow of the manufacturing method provided by an aspect of the present invention is described in a manner of forming the shallow trench isolation, then forming the N-type doped region, and finally forming the P-type doped region, in practice, a person skilled in the art may form the shallow trench isolation, the N-type doped region, and the P-type doped region according to the existing or future flow, and the order of forming the shallow trench isolation, the N-type doped region, and the P-type doped region should not unduly limit the scope of the present invention.

Accordingly, the manufacturing method provided according to an aspect of the present invention can form a hysteretic-free scr that further increases the trigger voltage. Moreover, the manufacturing process is compatible with the existing CMOS process, and the manufacturing complexity and the manufacturing cost are not additionally increased.

More specifically, in another embodiment of the manufacturing method provided by an aspect of the present invention, the hysteresis-free state of the scr can be further adjusted by adjusting the width D2 of the heavily N-doped region 26 and the width S of the active region between the heavily P-doped region 20 and the heavily N-doped region 28. In one embodiment, D2 can be adjusted to 0.4-10um and width S can be adjusted to 0-2um to adjust the SCR to enter the state without hysteresis effect.

Specifically, if D2 is larger, the scr is easier to enter the no-hysteresis effect state, and those skilled in the art can determine an appropriate D2 according to the difficulty of entering the no-hysteresis effect state. In addition, the distribution of carrier holes after being injected from P +20 into the N-type well 60 can be improved by adjusting the width S of the active region between the P-type heavily doped region 20 and the N-type heavily doped region 28, so as to improve the efficiency of the N-type heavily doped region 28 as a guard ring, i.e., improve the efficiency of recombination annihilation of the carrier holes by the N-type heavily doped region 28.

Fig. 4 shows a schematic structural diagram of a silicon controlled rectifier provided according to another aspect of the present invention. As shown in fig. 4, the scr provided by the present invention includes a P-type substrate 80. An N-type well 60 and a P-type well 70 are formed on the upper portion of a P-type substrate 80, and an interface is formed between the N-type well 60 and the P-type well 70; to form a PN junction at the interface. The upper part of the N-type well 60 is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28 which form the anode of the silicon controlled rectifier, the N-type heavily doped region 28 is close to the interface, and an active region of the N-type well 60 is arranged between the N-type heavily doped region 28 and the interface. The P-well 70 has a heavily doped P-type region 26 and a heavily doped N-type region 24, which form the cathode of the scr, and the heavily doped N-type region 24 is close to the interface. A shallow trench isolation 90 is formed between the heavily doped N-type region 24 and the interface, the shallow trench isolation 90 is adjacent to the heavily doped N-type region 24, and an active region of the P-well 70 is formed between the shallow trench isolation 90 and the interface.

Since the two sides of the interface are the N-well 60 with the width D1 and the P-well 70 of D3, respectively, the reverse breakdown voltage of the parasitic diode P-well 70/N-well 60 (N-type heavily doped region 28) inside the scr is determined by the width D1 of the active region of the N-well 60 between the N-type heavily doped region 28 and the interface and the width D3 of the active region of the P-well 70 between the shallow trench isolation 90 and the interface. After the P-type doped region originally arranged at the interface is removed, the ion doping concentration of the P end of the parasitic diode is reduced, so that the reverse breakdown voltage of the parasitic diode is improved, and the trigger voltage of the silicon controlled rectifier is determined by the reverse breakdown voltage, so that the trigger voltage of the silicon controlled rectifier can be effectively improved within a certain range. Or the design size of the device can be reduced within a certain range under the condition of keeping the trigger voltage unchanged, so that the effect of saving the layout area can be achieved.

In one embodiment, the trigger voltage of the scr is adjusted by adjusting the width D1 of the active region of the N-well 60 between the heavily N-doped region 28 and the interface. In one embodiment, the width D1 can be adjusted to 0-2um to adjust the trigger voltage so that the SCR has trigger voltages meeting different requirements.

In the above embodiment, the trigger voltage of the scr is also related to the width D3 of the active region between the shallow trench isolation 90 and the interface. The width D3 of the active region between the shallow trench isolation 90 and the interface affects the width of the P-well 70/N-well 60 (heavily N-doped region 28) of the parasitic diode in the depletion region of the P-well 70, and affects the reverse breakdown voltage of the parasitic diode, and in turn affects the trigger voltage of the scr. In one embodiment, the width of D3 is in the range of 0-5 um, so that the SCR has trigger voltage meeting different requirements.

In the above embodiment, the N-type heavily doped region 28 is directly connected to the anode a, which enables the N-type heavily doped region 28 to effectively reduce the probability that holes injected from the P-type heavily doped region 20 to the N-type well 60 migrate to reach the interface of the N-type well 60/the P-type well 70, that is, the efficiency of the N-type heavily doped region 28 as a guard ring is further improved, so the width of the N-type heavily doped region 28 can be designed to be smaller, and the layout area is saved. It is understood that in the above-described embodiment, the heavily doped N-type region 28 and the heavily doped N-type region 24 have the same ion doping concentration, so that the efficiency of the heavily doped N-type region 28 as a guard ring can be ensured.

As shown in fig. 4, an active region of the N-type well 60 is located between the P-type heavily doped region 20 and the N-type heavily doped region 28 in the N-type well 60 of the scr provided by the present invention, and the arrangement of the active region between the P-type heavily doped region 20 and the N-type heavily doped region 28, i.e. the structure without shallow trench isolation, will affect the distribution of carrier holes after being injected from P +20 into the N-type well 60. And shallow trench isolation is formed between the P-type heavily doped region 26 and the N-type heavily doped region 24 in the cathode portion of the scr.

More specifically, the width D2 of the heavily doped N-type region 26 and the width S of the active region between the heavily doped P-type region 20 and the heavily doped N-type region 28 are related to the no hysteresis effect state of the scr. The larger the D2, the easier it is for the scr to enter the no-hysteretic state, and one skilled in the art can determine the appropriate D2 based on how easy it is to enter the no-hysteretic state. In addition, the width S of the active region between the P-type heavily doped region 20 and the N-type heavily doped region 28 can improve the distribution of carrier holes after injection from P +20 into the N-type well 60, so as to improve the efficiency of the N-type heavily doped region 28 as a guard ring, i.e., improve the efficiency of recombination annihilation of the carrier holes by the N-type heavily doped region 28. In one embodiment, D2 is in the range of 0.4-10um and S is in the range of 0-2 um.

According to the above description, the silicon controlled rectifier provided by one aspect of the invention improves the trigger voltage of the silicon controlled rectifier without hysteresis effect within a certain range by improving the reverse breakdown voltage of the parasitic PN diode which determines the trigger voltage, and is beneficial to reducing the series stages required when the multistage series is applied to high-voltage anti-static protection, thereby achieving the purpose of saving layout area. The manufacturing method of the silicon controlled rectifier provided by the invention is compatible with the existing CMOS process, and can manufacture the silicon controlled rectifier without hysteresis effect, which can further improve the trigger voltage, under the condition of not increasing the manufacturing complexity.

Fig. 5 also shows an application scenario diagram of the silicon controlled rectifier provided by the invention. As shown in fig. 5, the scr provided by the present invention can effectively act as a protection circuit when applied to an ESD protection circuit.

Thus, embodiments for a silicon controlled rectifier and method of making the same have been described. Although the present disclosure has been described with respect to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Reference in the specification to one embodiment or an embodiment is intended to include within at least one embodiment of a circuit or method a particular feature, structure, or characteristic described in connection with the embodiment. The appearances of the phrase one embodiment in various places in the specification are not necessarily all referring to the same embodiment.