阅读说明：本技术 用于逻辑电路的全速测试的系统芯片及其操作方法 (System chip for full speed testing of logic circuits and method of operating the same ) 是由 申范锡 朴真秀 于 2019-12-05 设计创作，主要内容包括：一种系统芯片包括：第一核中的第一扫描寄存器,该第一扫描寄存器最靠近第一核的输入端口；第一扫描寄存器的反馈路径上的反相电路；第一核中的第二扫描寄存器；以及逻辑电路,其位于第一扫描寄存器与第二扫描寄存器之间的数据路径上。在用于逻辑电路的全速测试的测试模式中,反相电路通过反转从第一扫描寄存器输出的扫描数据产生测试数据,第一扫描寄存器响应于时钟信号的第一脉冲存储测试数据,逻辑电路基于从第一扫描寄存器输出的测试数据产生结果数据,并且第二扫描寄存器响应于时钟信号的第二脉冲存储结果数据。(A system-on-chip comprising: a first scan register in the first core, the first scan register being closest to the input port of the first core; an inverter circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit located on a data path between the first scan register and the second scan register. In a test mode for full speed testing of a logic circuit, an inverter circuit generates test data by inverting scan data output from a first scan register storing the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data output from the first scan register, and a second scan register storing the result data in response to a second pulse of the clock signal.)

1. A system-on-chip including a plurality of cores, comprising:

a first scan register in a first core of the plurality of cores, the first scan register being closest to an input port of the first core;

an inverter circuit on a feedback path of the first scan register;

a second scan register in the first core; and

logic circuitry located on a data path between the first scan register and the second scan register, wherein:

in a test mode for full speed testing of the logic circuit, the inverting circuit generates test data by inverting scan data output from the first scan register,

the first scan register stores the test data in response to a first pulse of a clock signal,

the logic circuit generates result data based on the test data output from the first scan register, and

the second scan register stores the result data in response to the second pulse of the clock signal.

2. The system-on-chip of claim 1, wherein the second pulse is adjacent to the first pulse.

3. The system chip of claim 1, wherein the frequency of the clock signal is the same as the frequency of an operating clock signal in normal functioning of the system chip.

4. The system chip of claim 1, wherein a transition delay fault of the logic circuit is identified by comparing target data with the result data stored in the second scan register.

5. The system-on-chip of claim 1, further comprising:

a selection circuit that supplies one of the functional data output from the input port and the test data output from the inversion circuit to the first scan register, wherein,

in the test mode, the selection circuit selects the test data to supply the test data to the first scan register.

6. The system chip of claim 5, wherein the functional data is provided from a top core of the plurality of cores.

7. A system-on-chip including a plurality of cores, comprising:

a first scan register in a first core of the plurality of cores, the first scan register being closest to an output port of the first core;

a first inverting circuit on a feedback path of the first scan register;

a second scan register in a second core of the plurality of cores, the second scan register being closest to an input port of the second core; and

logic circuitry located on a data path between the first scan register and the second scan register, wherein:

in a test mode for full speed testing of the logic circuit, the first inverting circuit generates first test data by inverting scan data output from the first scan register,

the first scan register stores the first test data in response to a first pulse of a clock signal,

the logic circuit generates result data based on the first test data output from the first scan register, and

the second scan register stores the result data in response to a second pulse of the clock signal.

8. The system on chip of claim 7, wherein the second pulse is adjacent to the first pulse.

9. The system chip of claim 7, wherein the frequency of the clock signal is the same as the frequency of an operating clock signal in normal functioning of the system chip.

10. The system chip of claim 7, wherein a transition delay fault of the logic circuit is identified by comparing target data with the result data stored in the second scan register.

11. The system-on-chip of claim 7, further comprising:

a first selection circuit that receives functional data and the first test data output from the first inversion circuit and supplies one of the functional data and the first test data to the first scan register, wherein,

in the test mode, the first selection circuit selects the first test data to supply the first test data to the first scan register.

12. The system-on-chip of claim 11, further comprising:

a second inverting circuit on a feedback path of the second scan register; and

a second selection circuit that supplies one of the result data output from the input port and second test data output from the second inversion circuit to the second scan register, wherein,

in the test mode, the second selection circuit provides the result data to the second scan register.

13. The system chip of claim 7, wherein the second core is a top-level core.

14. A method of operating a system chip for full speed testing of logic circuits on a data path between a first scan register and a second scan register, the method comprising the steps of:

outputting scan data through the first scan register in response to a clock signal having a first frequency;

providing the first scan register with test data generated by inverting the scan data output from the first scan register;

outputting the test data through the first scan register in response to a first pulse of a clock signal having a second frequency;

outputting result data by the logic circuit based on the test data output from the first scan register;

outputting the result data through the second scan register in response to a second pulse of the clock signal having the second frequency.

15. The method of claim 14, wherein the second pulse is adjacent to the first pulse.

16. The method of claim 14, wherein the second frequency is the same as a frequency of an operating clock signal in a normal function of the system chip.

17. The method of claim 14, wherein a transition delay fault of the logic circuit is identified by comparing target data with the result data stored in the second scan register.

18. The method of claim 14, wherein the system chip comprises a first core comprising a first input port and a first output port and a second core comprising a second input port and a second output port, and wherein,

the first output port is connected to the second input port.

19. The method of claim 18, wherein the first scan register and the second scan register are included in the first core, and wherein,

the first scan register is the input wrapper register closest to the first input port.

20. The method of claim 18, wherein the first scan register is included in the first core, and wherein:

the second scan register is included in the second core,

the first scan register is the output wrapper register closest to the first output port, and

the second scan register is the input wrapper register closest to the second input port.

Technical Field

Embodiments of the inventive concept described herein relate to a system chip, and more particularly, to a system chip that performs full speed testing of a logic circuit and an operating method of the system chip.

Background

A system on chip (SoC) is a semiconductor chip in which a system that performs various functions is implemented. Logic circuits in system chips have been tested using design for testability (DFT) techniques. Among DFT techniques, scan test is a test technique for testing a logic circuit by verifying output data based on input scan pattern data (scan pattern data). Faults of the logic circuit, such as stuck-at faults, transition delay faults, and the like, may be identified based on scan testing. Full speed testing, which is scan testing, may be performed to identify transitional delay faults of the logic circuit.

As the demand for more complex computing increases, socs on which a plurality of cores are mounted (hereinafter, referred to as "multi-core socs") are widely used. As the amount of data exchange between the multiple cores in a multi-core SoC test increases, it may be necessary to test interface circuits between the multiple cores. However, when the cores are tested individually, full speed testing of the interface circuits may not be properly and efficiently performed.

Disclosure of Invention

Drawings

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, wherein:

FIG. 1 shows a system on a chip (SoC) in accordance with an example embodiment;

FIG. 2 shows one example of the first core of FIG. 1;

FIG. 3A illustrates a register in accordance with an illustrative embodiment;

FIG. 3B illustrates an example of the register of FIG. 3A;

FIG. 4 illustrates an SoC for full speed testing of logic circuits in accordance with an exemplary embodiment;

FIG. 5 illustrates a timing diagram of a clock signal and a scan enable signal for full speed testing in accordance with an exemplary embodiment;

FIG. 6 illustrates exemplary operation of the SoC of FIG. 4 based on the clock signal and the scan enable signal of FIG. 5;

FIG. 7 illustrates a flow chart of exemplary operation of the SoC of FIG. 4 for full speed testing;

FIG. 8 illustrates an SoC for full speed testing of logic circuits in accordance with an exemplary embodiment;

FIG. 9 illustrates an SoC for full speed testing of logic circuits in accordance with an exemplary embodiment;

FIG. 10 illustrates an SoC for full speed testing of logic circuits in accordance with an exemplary embodiment;

FIG. 11 illustrates an SoC for full speed testing of logic circuits in accordance with an exemplary embodiment;

FIG. 12 shows a test system according to an example embodiment; and

fig. 13 shows an exemplary configuration of an electronic system to which the SoC is applied according to an exemplary embodiment.

An embodiment is a system-on-chip including a plurality of cores, the system-on-chip comprising: a first scan register in a first core of the plurality of cores, the first scan register being closest to an input port of the first core; an inverter circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit located on a data path between the first scan register and the second scan register. In a test mode for full speed testing of a logic circuit, an inverter circuit generates test data by inverting scan data output from a first scan register storing the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data output from the first scan register, and a second scan register storing the result data in response to a second pulse of the clock signal.